Merge branch 'flang' into 'master'

fc: add support for the flang compiler

See merge request ita1024/waf!2372

ChangeLog

@@ -1,6 +1,12 @@
+NEW IN WAF 2.1.1
+----------------
+* Fixed some argparse regressions
+* Fixed 'waf --version'
+* Updated most project examples
+
 CHANGES IN WAF 2.1.0
 --------------------
-* While the Waf file runs on Python 2 and 3, creating it requires version 3
+* While the Waf file runs on Python 2 and 3, creating it requires Python 3
 + Added wafcache
 + waf_unit_test: Added task in returned tuples, custom reports should be adapted
 ~ Ensure ConfigurationContext.load and Context.load definitions are consistent and remove unused *k parameters

README.md

@@ -9,7 +9,7 @@ Waf is a Python-based framework for configuring, compiling and installing applic
 * *Extensibility*: though many programming languages and compilers are already supported by default, many others are available as extensions
 * *IDE support*: Eclipse, Visual Studio and Xcode project generators (`waflib/extras/`)
 * *Documentation*: the application is based on a robust model documented in [The Waf Book](https://waf.io/book/) and in the [API docs](https://waf.io/apidocs/)
-* *Python compatibility*: cPython 2.5 to 3.x, Jython 2.5, IronPython, and PyPy
+* *Python compatibility*: cPython 2.7 to 3.x, Jython 2.7 and PyPy
 
 Learn more about Waf by reading [The Waf Book](https://waf.io/book/). For researchers and build system writers, Waf also provides a framework and examples for creating [custom build systems](https://gitlab.com/ita1024/waf/tree/master/build_system_kit) and [package distribution systems](https://gitlab.com/ita1024/waf/blob/master/playground/distnet/README.rst).
 
@@ -17,8 +17,6 @@ Download the project from our page on [waf.io](https://waf.io/), consult the [ma
 
 ## HOW TO CREATE THE WAF SCRIPT
 
-Python >= 2.7 is required to generate the waf script:
-
 ```sh
 python ./waf-light configure build
 ```

TODO

@@ -1,4 +0,0 @@
-Waf 2.1
--------
-
-- Fix the circular imports ccroot<->c_config.py

demos/dbus/main.c

@@ -1,3 +0,0 @@
-int main() {
-	return 0;
-}

demos/dbus/test.xml

@@ -1,10 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<node name="/org/freedesktop/DBus/Properties">
- <interface name="org.freedesktop.DBus.Properties">
-   <method name="Set">
-     <arg type="s" name="interface_name"/>
-     <arg type="s" name="property_name"/>
-     <arg type="v" name="value"/>
-   </method>
- </interface>
-</node>

demos/dbus/wscript

@@ -1,21 +0,0 @@
-#! /usr/bin/env python
-# encoding: utf-8
-# Thomas Nagy, 2010 (ita)
-
-VERSION = '1.0'
-
-def options(opt):
-	opt.load('compiler_c')
-
-def configure(conf):
-	conf.load('compiler_c dbus')
-	conf.find_program('glib-genmarshal') # required on a few systems
-
-def build(bld):
-	tg = bld.program(
-		includes = '.',
-		source = bld.path.ant_glob('*.c'),
-		target = 'gnome-hello')
-
-	tg.add_dbus_file('test.xml', 'test_prefix', 'glib-server')
-

demos/java/animals/wscript

@@ -8,7 +8,7 @@ def build(bld):
 
 		# javac
 		srcdir    = 'src',
-		compat    = '1.7',
+		compat    = '8',
 
 		# jar
 		basedir   = '.',

demos/java/bengala/wscript

@@ -4,7 +4,7 @@ def build(bld):
 
 	bld(features  = 'javac',
 		srcdir      = 'src',
-		compat      = '1.7',
+		compat      = '8',
 		use         = 'cats-src',
 		name        = 'bengala-cat',
 		recurse_use = True,

demos/java/cats/wscript

@@ -4,7 +4,7 @@ def build(bld):
 
 	bld(features  = 'javac',
 		srcdir    = 'src',
-		compat    = '1.7',
+		compat    = '8',
 		use       = 'animals',
 		name      = 'cats-src',
 	)

demos/java/wscript

@@ -36,7 +36,7 @@ def build(bld):
 	bld(features   = 'javac jar javadoc',
 		srcdir     = 'src/', # folder containing the sources to compile
 		outdir     = 'src', # folder where to output the classes (in the build directory)
-		compat     = '1.6', # java compatibility version number
+		compat     = '8', # java compatibility version number
 		sourcepath = ['src', 'sup'],
 		classpath  = ['.', '..'],
 		#jaropts = ['-C', 'default/src/', '.'], # can be used to give files

demos/jni/src/jni/source/StringUtils.c

@@ -1,6 +1,6 @@
 #include "StringUtils.h"
 #include <string.h>
-
+#include <ctype.h>
 
 JNIEXPORT jboolean JNICALL Java_StringUtils_isAlpha(JNIEnv *env, jclass clazz,
         jstring jStr)

demos/qt5/foo.cpp

@@ -35,4 +35,3 @@ Bar_private::Bar_private() : QWidget(NULL) {
 }
 
 #include "foo.moc"
-

demos/variants/wscript

@@ -45,7 +45,7 @@ def build(bld):
 	#
 	# the config set 'debug' is loaded automatically when the 'debug' variant is used
 	if not bld.variant:
-		bld.fatal('Call "waf build_debug" or "waf build_release", and read the comments in the wscript file!')
+		bld.fatal('Call "waf build_debug" or "waf build_release" (same with "clean_debug") and read the comments in the wscript file!')
 
 	# the includes='.' add the build directory path to the command arguments
 	# (look at the -I flags by using waf -v)

playground/R/src/test.R

@@ -1,22 +0,0 @@
-#!/usr/bin/env Rscript
-
-require(R.utils)
-require(tools)
-
-cmdArgs <- commandArgs(asValues = TRUE, excludeReserved = FALSE, excludeEnvVars = TRUE, os = "current")
-
-if(!is.null(cmdArgs[["numTrees"]])) nTrees <- (as.integer(cmdArgs[["numTrees"]])) else nTrees <- 500
-
-ffff <- cmdArgs[["ffff"]]
-print(paste("nTrees =", nTrees, sep = " "))
-
-Sweave(ffff)
-texi2dvi("testSweave.tex", pdf = TRUE)
-
-Stangle(ffff)
-source("testSweave.R")
-
-print(paste("Current Date/Time: ", date(), sep=""))
-
-(sessionInfoObj <- sessionInfo())
-

playground/R/src/testSweave.Rnw

@@ -1,13 +0,0 @@
-\documentclass{article}
-\SweaveOpts{eps=FALSE}
-
-<<setup, echo=FALSE, results=hide>>=
-options(width=80)
-@ 
-
-\begin{document}
-Estimate a random Forest model composed of
-\Sexpr{format(nTrees, big.mark = ',')}
-trees.
-
-\end{document}

playground/R/wscript

@@ -1,29 +0,0 @@
-#! /usr/bin/env python
-# encoding: utf-8
-
-VERSION = '1.0.0'
-APPNAME = 'testR'
-
-top = '.'
-out = 'build'
-
-def configure(ctx):
-	ctx.find_program('texi2dvi')
-	ctx.load('R')
-
-def build(ctx):
-	ctx(
-		rule   = '${R} CMD BATCH ${tsk.generator.ropts} ${tsk.generator.fopt % tsk.inputs[1].abspath()} -- ${SRC[0].abspath()} foo.log',
-		source = 'src/test.R src/testSweave.Rnw',
-		target = 'src/testSweave.pdf',
-		cwd    = ctx.path.find_node('src').get_bld().abspath(),
-		install_path = '${PREFIX}/share',
-		shell = False,
-		ropts = '--no-restore --no-save --no-readline --numTrees=1000',
-		fopt = '--ffff=%s'
-	)
-
-def dist(ctx):
-	ctx.algo = 'zip'
-	ctx.excl = ' **/waf-* **/.waf-* **/*~ **/*.orig **/*.pyc **/*.pyo **/*.bak **/.lock-w* **/*.log **/*.lot **/*.lof **/*.lst **/*.aux **/*.bbl **/*.blg **/*.out **/*.toc'
-

playground/compress/wscript

@@ -25,7 +25,7 @@ import random, bz2, os, threading
 lock = threading.Lock()
 
 def options(opt):
-	opt.add_option('--num', action='store', type='int', default=200, help='amount of compressed files to create')
+	opt.add_option('--num', action='store', type=int, default=200, help='amount of compressed files to create')
 
 # values for storing the min and max
 gzip  = [10000000, 0]

playground/javatest/wscript

@@ -6,6 +6,8 @@
 # Simple script to demonstrate integration of Java Unit testing inside
 # standard waf_unit_test using either TestNG or JUnit
 #
+# try:
+#   waf configure --jtpath=/usr/share/java/testng.jar:/usr/share/java/jcommander.jar clean build
 
 def test_results(bld):
 	"""

playground/maxjobs2/compute/wscript

@@ -1,11 +1,13 @@
 #! /usr/bin/env python
-
-# The following example shows how several build processes can collaborate
-# to stop spawning new processes when a special task of type K is executed
-# this may be useful for link tasks for example
+#
+# several processes can wait on a resource limit
+# in this case the maximum amount of "very busy" tasks is one across several processes
+# also:
+# - this example is posix-only (fcntl)
+# - it assumes that the lock file "busy_lock.txt" is already created by another process
 
 def options(opt):
-	opt.add_option('--loops', action='store', type='int', default=5, help='amount of cpu-intensive loops to perform')
+	opt.add_option('--loops', action='store', type=int, default=5, help='amount of cpu-intensive loops to perform')
 
 def configure(conf):
 	busy = conf.path.find_node('look_busy.py').abspath()
@@ -33,60 +35,47 @@ def lock_maxjob(self):
 	# lock the file, telling other build processes to avoid spawining tasks during that time
 	while True:
 		try:
-			self.lockfd = os.open(self.generator.bld.lockfile, os.O_TRUNC | os.O_CREAT | os.O_RDWR)
-			fcntl.flock(self.lockfd, fcntl.LOCK_EX | fcntl.LOCK_NB)
+			# each task/thread will have its own "lockfd"
+			# it is important to not create too many of them
+			if not getattr(self, 'lockfd', None):
+				with lock:
+					self.lockfd = os.open(self.generator.bld.lockfile, os.O_TRUNC | os.O_CREAT | os.O_RDWR)
+			with lock:
+				fcntl.flock(self.lockfd, fcntl.LOCK_EX | fcntl.LOCK_NB)
 		except EnvironmentError as e:
 			if e.errno in (errno.EACCES, errno.EAGAIN):
 				time.sleep(0.3)
 				continue
 			raise
-		os.write(self.lockfd, "%d" % os.getpid())
+
+		os.write(self.lockfd, b"%d %s\n" % (os.getpid(), repr(threading.current_thread()).encode()))
 		self.start_time = time.time()
 		break
 
 def release_maxjob(self):
 	# release the lock file
-	print("> long task %d" % (time.time() - self.start_time))
-	try:
-		os.remove(self.generator.bld.lockfile)
-		os.close(self.lockfd)
-	except OSError as e:
-		# of someone else has removed the lock... bad luck! but do not fail here
-		print("unexpected failure", e)
-		pass
-
-def wait_maxjob(self):
-	# wait on the lock file.. up to a certain limit
-	while True:
+	with lock:
 		try:
-			ini = os.stat(self.generator.bld.lockfile).st_mtime
+			fcntl.flock(self.lockfd, fcntl.LOCK_UN)
+			os.close(self.lockfd)
 		except OSError as e:
-			return
-		diff = time.time() - ini
-		if diff > 300: # stale lock file? wait 5 minutes
-			return
-		time.sleep(0.5)
+			# of someone else has removed the lock... bad luck! but do not fail here
+			pass
+		except Exception as e:
+			print(e)
+		#print("lock released!", threading.current_thread())
 
 # the method process is called by threads...
 def process2(self):
-
 	if getattr(self.generator, 'exclusive', False):
-		lock.acquire()
-		try:
-			self.lock_maxjob()
-		finally:
-			lock.release()
-	else:
-		self.wait_maxjob()
+		self.lock_maxjob()
 
+	# regular work
 	ret = self.process_bound_maxjobs()
 
 	if getattr(self.generator, 'exclusive', False):
-		lock.acquire()
-		try:
-			self.release_maxjob()
-		finally:
-			lock.release()
+		self.release_maxjob()
+
 	return ret
 
 def process(self):
@@ -99,5 +88,3 @@ Task.Task.process_bound_maxjobs = Task.Task.process
 Task.Task.process = process
 Task.Task.lock_maxjob = lock_maxjob
 Task.Task.release_maxjob = release_maxjob
-Task.Task.wait_maxjob = wait_maxjob
-

playground/maxjobs2/wscript

@@ -8,6 +8,9 @@ def configure(conf):
 def build(bld):
 	p = bld.srcnode.find_node('compute').abspath()
 
+	lockf = bld.srcnode.make_node('busy_lock.txt')
+	lockf.write('')
+
 	bld.jobs = JOBS = 3
 	for i in range(JOBS):
 		bld(rule='waf configure build -o test%d'%i, cwd=p, always=True)

playground/pep8/wscript

@@ -1,26 +0,0 @@
-#!/usr/bin/env python
-# encoding: utf-8
-
-from waflib.TaskGen import extension
-
-top = '.'
-out = 'build'
-
-
-@extension('.py', 'wscript')
-def check_syntax(self, node):
-    self.create_task('Pep8', node)
-
-
-def options(opt):
-    opt.load('pep8')
-
-
-def configure(conf):
-    # warning after this comment
-    
-    conf.load('pep8')
-
-
-def build(bld):
-    bld(source='wscript')

playground/protoc_gen_java/proto.source

@@ -1,3 +1,4 @@
+syntax = "proto2";
 package udp.tc.tests;
 
 option java_package = "com.udp.tc.tests";
@@ -6,7 +7,6 @@ option cc_generic_services = false;
 option java_generic_services = false;
 option py_generic_services = false;
 
-
 message IncludeMe {
     required int32 test = 1;
     optional uint32 blah = 2;

playground/protoc_gen_java/wscript

@@ -13,8 +13,12 @@ def options(opt):
 
 def configure(conf):
 	conf.load('compiler_cxx java protoc')
-	# Here you have to point to your protobuf-java JAR
-	conf.env.CLASSPATH_PROTOBUF = ['/usr/share/maven-repo/com/google/protobuf/protobuf-java/3.0.0/protobuf-java-3.0.0.jar']
+
+	# set this
+	protobuf = '/usr/share/maven-repo/com/google/protobuf/protobuf-java-util/3.21.12/protobuf-java-util-3.21.12.jar'
+	if not os.path.exists(protobuf):
+		conf.fatal("set the path to the protobuf library in this example, for example %s" % protobuf)
+	conf.env.CLASSPATH_PROTOBUF = protobuf
 
 def build(bld):
 
@@ -26,11 +30,11 @@ def build(bld):
 	)
 
 	# cxx doesn't have a problem with this, just knows gen.proto will pop up later
-        bld(
+	bld(
 		features = 'cxx cxxshlib',
 		source = [ bld.path.find_or_declare(genp.target) ],
-                name     = 'somelib',
-                target   = 'somelib'
+		name     = 'somelib',
+		target   = 'somelib'
 	)
 
 	# but for java:

playground/pyqt5/wscript

@@ -14,9 +14,11 @@ def options(opt):
 	opt.load('python pyqt5')
 
 def configure(conf):
-	# Recent UIC/RCC versions require explicit python generator selection
-	conf.env.QT_PYUIC_FLAGS = ['-g', 'python']
-	conf.env.QT_PYRCC_FLAGS = ['-g', 'python']
+	# Recent UIC/RCC versions may require explicit python generator selection
+	#conf.env.QT_PYUIC_FLAGS = ['-g', 'python']
+	#conf.env.QT_PYRCC_FLAGS = ['-g', 'python']
+	#
+	#
 	# Load also python to demonstrate mixed calls
 	conf.load('python pyqt5')
 	conf.check_python_version((2,7,4))

playground/rst/wscript

@@ -3,6 +3,8 @@
 import os, re, subprocess
 from waflib import Options, TaskGen, Utils
 
+top = out = '.'
+
 def options(opt):
 	opt.load('rst')
 	opt.load('tex')
@@ -20,32 +22,20 @@ def build(bld):
 
 	bld(
 	 target='generated.rst',
-	 rule=lambda tsk: Utils.writef( tsk.outputs[0].abspath(), "Generated contents in %s" % tsk.outputs[0].name),
+	 rule=lambda tsk: tsk.outputs[0].write("Generated contents in %s" % tsk.outputs[0].name),
 	)
-	
+
 	bld(
 	 target='generated.csv',
-	 rule=lambda tsk: Utils.writef( tsk.outputs[0].abspath(), "a,b,c\n1,2,%s" % tsk.outputs[0].name),
+	 rule=lambda tsk: tsk.outputs[0].write("a,b,c\n1,2,%s" % tsk.outputs[0].name),
 	)
-	
+
 	bld(
 	 target='generated.html',
-	 rule=lambda tsk: Utils.writef( tsk.outputs[0].abspath(), "<p>Generated HTML data</p>"),
+	 rule=lambda tsk: tsk.outputs[0].write("<p>Generated HTML data</p>"),
 	)
 
-	bld(
-	 features='rst',
-	 target='test1.html',
-	 source='test1.rst',
-	)
-	
-	bld(
-	 features='rst',
-	 target='test1.pdf',
-	 source='test1.rst',
-	)
-
-	for x in bld.path.ant_glob("**/*.svg"):
+	for x in bld.path.ant_glob("**/*.svg", remove=False):
 		bld(
 		 rule='inkscape --export-area-drawing --export-png=${TGT[0].bldpath()} ${SRC[0].bldpath()}',
 		 source=x,
@@ -57,9 +47,24 @@ def build(bld):
 		 target=x.change_ext('.pdf'),
 		)
 
+	bld.add_group()
+
+	bld(
+	 features='rst',
+	 target='test1.html',
+	 source='test1.rst',
+	)
+
+	if bld.env.RST2PDF:
+		bld(
+			features='rst',
+			target='test1.pdf',
+			source='test1.rst',
+		)
+
 	bld(
 	 target='generated.tex',
-	 rule=lambda tsk: Utils.writef( tsk.outputs[0].abspath(), "Generated contents in %s" % tsk.outputs[0].name),
+	 rule=lambda tsk: tsk.outputs[0].write("Generated contents in %s" % tsk.outputs[0].name)),
 	)
 
 	bld(

playground/shrinking_sets/wscript

@@ -1,56 +0,0 @@
-#! /usr/bin/env python
-
-def options(ctx):
-	pass
-
-def configure(ctx):
-	ctx.load('mem_reducer')
-	pass
-
-def build(bld):
-	bld(features='make_a_lot')
-
-"""
-Testcase for the mem_reducer.py tool
-"""
-
-import itertools, random
-from waflib import Utils, Task, TaskGen, Runner
-
-random.seed(0)
-class a(Task.Task):
-	def run(self):
-		self.outputs[0].write('a')
-class b(Task.Task):
-	after = ['a']
-	def run(self):
-		self.outputs[0].write('b')
-class c(Task.Task):
-	after = ['b', 'c']
-	def run(self):
-		self.outputs[0].write('c')
-class d(Task.Task):
-	after = ['c', 'a']
-	def run(self):
-		self.outputs[0].write('d')
-
-@TaskGen.feature('make_a_lot')
-def make_a_lot_of_tasks(self):
-	src = self.path.find_resource('wscript')
-	for x in range(9000):
-		anode = self.path.find_or_declare('a%d' % x)
-		self.create_task('a', [src], [anode])
-
-		bnode = self.path.find_or_declare('b%d' % x)
-		self.create_task('b', [src], [bnode])
-
-		cnode = self.path.find_or_declare('c%d' % x)
-		self.create_task('c', [src], [cnode])
-
-		dnode = self.path.find_or_declare('d%d' % x)
-		self.create_task('d', [src], [dnode])
-
-	# shuffle the tasks, but in the same order
-	#random.seed(0)
-	#random.shuffle(self.tasks)
-

playground/slow_qt/wscript

@@ -1,33 +0,0 @@
-#! /usr/bin/env python
-# encoding: utf-8
-# Thomas Nagy, 2005, 2011 (ita)
-
-"""
-Including the moc files *is* the best practice (KDE), not doing it is easy,
-but makes the compilations about 30-40% slower on average.
-
-This is the slow version that creates _moc.cpp files (a bad idea!)
-"""
-
-VERSION='0.0.2'
-APPNAME='qt4_test2'
-
-top = '.'
-out = 'build'
-
-def options(opt):
-	opt.load('compiler_cxx qt4')
-
-def configure(conf):
-	conf.load('compiler_cxx qt4')
-	conf.load('slow_qt4')
-
-def build(bld):
-	bld(
-		features = 'qt4 cxx cxxprogram',
-		uselib   = 'QTCORE QTGUI QTOPENGL QTSVG',
-		source   = 'main.cpp foo.cpp',
-		includes = '.',
-		target   = 'window',
-	)
-

playground/slow_qt_example/foo.cpp

@@ -20,5 +20,4 @@ FooP::FooP() {
 
 }
 
-#include "foo_cpp_moc.cpp"
-
+#include "foo_cpp_mywindow_moc.cpp"

playground/slow_qt_example/wscript

@@ -0,0 +1,35 @@
+#! /usr/bin/env python
+# encoding: utf-8
+# Thomas Nagy, 2005, 2011 (ita)
+
+"""
+Process Q_OBJECT classes in source (foo.cpp) and header (foo.h) files.
+The generated files can be included or they will be built as additional files.
+
+The file slow_qt.py assumes that C++ files will include the generated code,
+and that header files will not.
+"""
+
+VERSION='0.0.3'
+APPNAME='slow_qt'
+
+top = '.'
+out = 'build'
+
+def options(opt):
+	opt.load('compiler_cxx qt5')
+
+def configure(conf):
+	conf.load('compiler_cxx qt5')
+	conf.load('slow_qt')
+
+def build(bld):
+	bld(
+		features = 'qt5 cxx cxxprogram',
+		uselib   = 'QT5CORE QT5GUI QT5OPENGL QT5SVG',
+		source   = 'main.cpp foo.cpp',
+		deps     = 'foo.h',
+		includes = '.',
+		target   = 'window',
+		name     = 'mywindow',
+	)

playground/stale_files/wscript

@@ -19,6 +19,13 @@ def configure(conf):
 	conf.load('compiler_c stale')
 
 def build(bld):
+	import waflib.Build
+	bld.post_mode = waflib.Build.POST_AT_ONCE
+
+	# the file foo.h is removed when bar.h is creatd
+	# or the other way round
+	# but both foo.h and bar.h will not be found in the build directory
+
 	import random
 	if random.randint(0, 1):
 		bld(rule='touch ${TGT}', target='foo.h')

playground/track_files_timestamps/wscript

@@ -12,7 +12,7 @@ from waflib import Logs, Options
 
 def options(opt):
 	opt.load('compiler_c')
-	opt.load('build_file_tracker')
+	opt.load('build_file_timestamp')
 
 def configure(conf):
 	conf.load('compiler_c')

playground/updates/wscript

@@ -1,15 +1,87 @@
 #! /usr/bin/env python
 
 """
-An example to show how multiple tasks can modify the same file
+Multiple tasks can modify the same file(s)
 """
 
 def configure(conf):
 	pass
 
 def build(bld):
-	bld.env.A = "test (change me) "
-	bld(rule="echo '${A}' > ${TGT}", target='foo.txt', name='foo')
-	bld(rule='echo `cat ${SRC}     ${SRC}`  > ${SRC}', source='foo.txt', name='one')
-	bld(rule='echo `cat ${SRC} ${SRC}`  > ${SRC}', source='foo.txt', after=['one'], name='two')
+	bld.env.A = 'test 1'
+	bld.env.B = 'test 2'
+	bld.env.C = 'test 3'
 
+	# recommended approach: just chain the commands/compilers/scripts
+	# (the "rule" parameter is a tuple of strings)
+	bld(
+		rule=("echo '${A}' > ${TGT}", "echo '${B}' >> ${TGT}", "echo '${B}' >> ${TGT}"),
+		target='bar.txt',
+		name='bar',
+		cls_keyword=lambda _: "single_chain",
+	)
+
+	# When tasks and targets are independent (update the same file "foo.txt"):
+	#
+	# 1. the initial task must depends on anything that can cause a rebuild, for example "cls_vars=['A', 'B', 'C']"
+	# 2. the order must be described strictly, for example: "after='update_foo1'"
+	# 3. "features='update_source'" is required to avoid rebuilds when the same input file is set: "source='foo.txt'"
+	bld(rule="echo '${A}' > ${TGT}", target='foo.txt', name='create_foo', cls_keyword=lambda _: "foo1", vars=['A', 'B', 'C'])
+	bld(rule="echo '${B}' >> ${SRC}", source='foo.txt', name='update_foo1', cls_keyword=lambda _:"foo2", after=['create_foo'], features='update_source')
+	bld(rule="echo '${C}' >> ${SRC}", source='foo.txt', name='update_foo2', cls_keyword=lambda _:"foo3", after=['update_foo1'], features='update_source')
+
+	# can be tested using
+	# rule="if [ $$(( $$RANDOM %% 2)) -eq 0 ]; then exit 1; fi; echo '${C}' >> ${SRC}"
+
+# --------------------------------------------------------------------------------------------
+
+from waflib.TaskGen import feature, after_method
+from waflib import Task
+
+def recompute_post_run(self):
+	# In general, inputs are assumed to be unchanged between builds
+	# which is also a safeguard when developers modify source files while building
+	#
+	# For the case above, the caches should be cleared for specific tasks
+
+	if getattr(self, 'busy_recompute', None):
+		# simple lock required due to traversing the entire task tree below
+		return
+	self.busy_recompute = True
+
+	# traverse the task tree: other tasks that use the same inputs need their caches cleared too
+	# this traversal (and the lock) are unnessary if a file is updated only once
+	for idx, group in enumerate(self.generator.bld.groups):
+		if idx > self.generator.bld.current_group:
+			# ignore downstream tasks
+			break
+
+		for tg in group:
+			for tsk in tg.tasks:
+				if not tsk.hasrun:
+					# ignore downstream tasks
+					continue
+
+				for in_node in self.inputs:
+					if in_node in tsk.inputs:
+						# assume that "recompute_post_run" is set on those tasks too
+						tsk.post_run()
+						break
+	delattr(self, 'busy_recompute')
+
+	# delete caches before recomputing
+	for node in self.inputs:
+		del node.ctx.cache_sig[node]
+	del self.cache_sig
+
+	# this assumes that the method post_run can be called more than once with similar effects
+	return Task.Task.post_run(self)
+
+@feature('update_source')
+@after_method('process_source', 'process_rule')
+def update_source(self):
+	# assume that all task objects are created at this point
+	# more "after_method" annotations might be necessary, depending
+	# on the project
+	for task in self.tasks:
+		task.__class__.post_run = recompute_post_run

playground/xilinx-ise/.gitignore

@@ -1,43 +0,0 @@
-*~
-*.bgn
-*.bit
-*.bld
-*.drc
-*.lso
-*.ncd
-*.ngc
-*.ngd
-*.ngr
-*.pad
-*.par
-*.pcf
-*.prj
-*.ptwx
-*.syr
-*.twr
-*.twx
-*.unroutes
-*.ut
-*.xpi
-*.xst
-*_bitgen.xwbt
-*_map.map
-*_map.mrp
-*_map.ncd
-*_map.ngm
-*_map.xrpt
-*_ngdbuild.xrpt
-*_pad.csv
-*_pad.txt
-*_par.xrpt
-*_summary.xml
-*_usage.xml
-*_xst.xrpt
-_ngo
-_xmsgs
-c4che
-config.log
-usage_statistics_webtalk.html
-xlnx_auto_0_xdb
-xst
-webtalk.log

playground/xilinx-ise/src/rs1.ucf

@@ -1,8 +0,0 @@
-NET "DLED_2"  LOC = "AB5" | IOSTANDARD = LVTTL | DRIVE = 24 ;
-NET "DLED_3"  LOC = "AA5" | IOSTANDARD = LVTTL | DRIVE = 24 ;
-NET "DLED_4"  LOC = "AA4" | IOSTANDARD = LVTTL | DRIVE = 24 ;
-NET "DLED_5"  LOC = "AB4" | IOSTANDARD = LVTTL | DRIVE = 24 ;
-
-NET "BUTTON_1"  LOC = "AA3"  | IOSTANDARD = LVTTL | PULLUP ;
-NET "BUTTON_2"  LOC = "Y4"   | IOSTANDARD = LVTTL | PULLUP ;
-

playground/xilinx-ise/src/top.vhd

@@ -1,34 +0,0 @@
---+-------------------------------------------------------------------------------------------------+
---|
---|	VHDL example for waf build automation tool
---|
---+-------------------------------------------------------------------------------------------------+
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity waf_demo is
-port (
-	-- buttons
-    BUTTON_1 : in std_logic;
-    BUTTON_2 : in std_logic;
-
-	-- leds
-	DLED_2 : out std_logic;
-	DLED_3 : out std_logic;
-	DLED_4 : out std_logic;
-	DLED_5 : out std_logic
-);
-end waf_demo;
-
-architecture inside of waf_demo is 
-
-begin
-
-	DLED_5 <= '1';
-	DLED_4 <= BUTTON_2;
-	DLED_3 <= '0';
-	DLED_2 <= not BUTTON_1;
-
-end inside;
-

playground/xilinx-ise/waf_demo.xise

@@ -1,372 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="src/top.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
-    </file>
-    <file xil_pn:name="src/rs1.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
-    <property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc3s1500" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|pci_7seg|pci_7seg_arch" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="src/top_pci_7seg.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pci_7seg" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="pci_7seg" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="pci_7seg_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="pci_7seg_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="pci_7seg_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="pci_7seg_translate.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Description" xil_pn:value="Example of project including verilog components" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="pci_7seg" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Error Report" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Error Report" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="iMPACT Project File" xil_pn:value="cJ_impact.ipf" xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="waf_demo" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-11T13:05:14" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_mapSmartGuideFileName" xil_pn:value="" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_parSmartGuideFileName" xil_pn:value="" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>

playground/xilinx-ise/wscript

@@ -1,273 +0,0 @@
-#!/usr/bin/env python
-# encoding: utf-8
-# waf example, builds a Xilinx FPGA bitstream
-
-__copyright__  = '(c) Jérôme Carretero <cJ-waf@zougloub.eu> 2012'
-
-"""
-This script builds an FPGA bitstream in an automated fashion.
-The Xilinx ISE IDE does the same thing, but needs mouse interaction.
-
-Notes:
-
-- this is quite sad, but the Xilinx toolchain tools want to operate
-  in the source folder, so top==out
-
-- Xilinx toolchain tools generate file with timestamps,
-  so an unsignificant change can still trigger domino cascade
-  of compilations.
-
-- a "xilinx" wrapper is used; this file performs set up of the
-  PATH for Xilinx tools (not done yet by the wscript)
-
-TODO:
-
-- make a tool
-- remove hard-coded .xst / .ut data (ISE generates that from the .xise)
-- CPLD toolchain (only works for FPGA)
-
-"""
-
-top = out = "." # mandatory
-
-import os
-import shutil
-import waflib
-from lxml import etree
-
-def options(opt):
-	pass
-
-def configure(cfg):
-	pass
-
-def build(bld):
-
-	if not os.path.exists("xst/projnav.tmp"):
-		os.makedirs("xst/projnav.tmp")
-	
-	nsmap={"pn": "http://www.xilinx.com/XMLSchema"}
-
-	xise = "waf_demo.xise"
-	fn = "waf_demo"
-	xml = etree.parse(xise)
-
-	def get(txt):
-		try: return xml.xpath('//pn:property[@pn:name = "%s"]/@pn:value' % txt, namespaces=nsmap)[0]
-		except: pass
-
-	device = get("Device") # or "xc3s1500"
-	package = get("Package") # or "fg456"
-	speed = get("Speed Grade") # or "-4"
-
-	# Set .prj file contents and collect HDL sources
-	hdl = []
-	prj = []
-	for x in xml.xpath('//pn:files/pn:file[@pn:type = "FILE_VHDL"]/@pn:name', namespaces=nsmap):
-		prj.append('vhdl work "%s"' % x)
-		hdl.append(x)
-	for x in xml.xpath('//pn:files/pn:file[@pn:type = "FILE_VERILOG"]/@pn:name', namespaces=nsmap):
-		prj.append('verilog work "%s"' % x)
-		hdl.append(x)
-	
-	ucf = xml.xpath('//pn:files/pn:file[@pn:type = "FILE_UCF"]/@pn:name', namespaces=nsmap)[0] or "src/pci_7seg.ucf"
-
-	def make_prj(self):
-		self.outputs[0].write("\n".join(prj))
-	
-	def make_xst(self):
-		self.outputs[0].write("""
-set -tmpdir "xst/projnav.tmp"
-set -xsthdpdir "xst"
-run
--ifn %(fn)s.prj
--ifmt mixed
--ofn %(fn)s
--ofmt NGC
--p %(device)s%(speed)s-%(package)s
--top %(fn)s
--opt_mode Speed
--opt_level 1
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--verilog2001 YES
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--mux_style Auto
--decoder_extract YES
--priority_extract Yes
--shreg_extract YES
--shift_extract YES
--xor_collapse YES
--rom_style Auto
--auto_bram_packing NO
--mux_extract Yes
--resource_sharing YES
--async_to_sync NO
--mult_style Auto
--iobuf YES
--max_fanout 500
--bufg 8
--register_duplication YES
--register_balancing No
--slice_packing YES
--optimize_primitives NO
--use_clock_enable Yes
--use_sync_set Yes
--use_sync_reset Yes
--iob Auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
-""" % locals())
-
-
-
-	def make_ut(self):
-		self.outputs[0].write("""
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g ConfigRate:6
--g CclkPin:PullUp
--g M0Pin:PullUp
--g M1Pin:PullUp
--g M2Pin:PullUp
--g ProgPin:PullUp
--g DonePin:PullUp
--g HswapenPin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g DCMShutdown:Disable
--g DCIUpdateMode:AsRequired
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Match_cycle:Auto
--g Security:None
--g DonePipe:No
--g DriveDone:No""")
-
-
-	bld(
-	 name='prj',
-	 target="%s.prj" % fn,
-	 rule=make_prj,
-	 source=[xise],
-	)
-
-	bld(
-	 name='xst',
-	 target='%s.xst' % fn,
-	 rule=make_xst,
-	 source=[xise],
-	)
-	bld(
-	 name='ut',
-	 target='%s.ut' % fn,
-	 rule=make_ut,
-	 source=[xise],
-	)
-
-	bld(
-	 name='synth',
-	 target=['%s%s' % (fn, ext) for ext in ('.syr', '.ngc', '.ngr', '.lso', '_xst.xrpt') ],
-	 rule='xilinx xst -intstyle ise -ifn ${SRC[0].abspath()} -ofn ${TGT[0].abspath()}; true',
-	 source=['%s.xst' % fn, '%s.prj' % fn] + hdl,
-	)
-
-	bld(
-	 name='ngdbuild',
-	 target=['%s%s' % (fn, ext) for ext in ('.ngd', '_ngdbuild.xrpt') ],
-	 rule='xilinx ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ${SRC[1].abspath()} -p %(device)s-%(package)s%(speed)s ${SRC[0].bldpath()} ${TGT[0].bldpath()}' % locals(),
-	 source=['%s.ngc' % fn, ucf],
-	)
-
-	bld(
-	 name='map',
-	 target=['%s%s' % (fn, ext) for ext in ('_map.ncd', '.pcf', '_map.map', '_map.mrp', '_map.ngm', '_map.xrpt', '.bld') ],
-	 rule='xilinx map -intstyle ise -p %(device)s-%(package)s%(speed)s -cm area -ir off -pr b -c 100 -o ${TGT[0].bldpath()} ${SRC[0].bldpath()} ${TGT[1].bldpath()}' % locals(),
-	 source=['%s.ngd' % fn],
-	)
-
-	bld(
-	 name='par',
-	 target=['%s%s' % (fn, ext) for ext in ('.ncd', '.pad', '.par', '.ptwx', '.unroutes', '.xpi', '_pad.csv', '_pad.txt', '_par.xrpt') ],
-	 rule='xilinx par -w -intstyle ise -ol high -t 1 ${SRC[0].bldpath()} ${TGT[0].bldpath()} ${SRC[1].bldpath()}',
-	 source=['%s_map.ncd' % fn, '%s.pcf' % fn],
-	)
-
-	bld(
-	 name='trce',
-	 target=['%s%s' % (fn, ext) for ext in ('.twx', '.twr') ],
-	 rule='xilinx trce -intstyle ise -e 3 -s 4 -n 3 -xml ${TGT[0].bldpath()} ${SRC[0].bldpath()} -o ${TGT[1].bldpath()} ${SRC[1].bldpath()}; true',
-	 source=['%s_map.ncd' % fn, '%s.pcf' % fn],
-	)
-
-	bld(
-	 name='bitgen',
-	 target=['%s%s' % (fn, ext) for ext in ('.bit', '.bgn', '.drc', '_bitgen.xwbt', '_summary.xml', '_usage.xml') ],
-	 rule='xilinx bitgen -intstyle ise -f ${SRC[1].bldpath()} ${SRC[0].bldpath()} ${TGT[0].bldpath()}',
-	 source=['%s.ncd' % fn, '%s.ut' % fn],
-	)
-
-	if bld.cmd == 'clean':
-		for tgen in bld.get_all_task_gen():
-			for tgt in waflib.Utils.to_list(tgen.target):
-				if os.path.exists(tgt):
-					os.remove(tgt)
-		for x in (
-		 'usage_statistics_webtalk.html',
-		 'webtalk_pn.xml',
-		 'webtalk.log',
-		 ):
-			if os.path.exists(x):
-				os.remove(x)
-
-		for x in (
-		 '_ngo',
-		 '_xmsgs',
-		 'iseconfig',
-		 'xlnx_auto_0_xdb',
-		 'xst',
-		 ):
-			try:
-				shutil.rmtree(x)
-			except:
-				pass
-
-def distclean(ctx):
-	import os, shutil
-	from waflib import Context
-
-	for fn in os.listdir('.'):
-		if fn.startswith(('.conf_check_', ".lock-w")) \
-		 or fn in (Context.DBFILE, 'config.log') \
-		 or fn == 'c4che':
-			if os.path.isdir(fn):
-				shutil.rmtree(fn)
-			else:
-				os.remove(fn)
-
-

waf-light

@@ -32,7 +32,7 @@ POSSIBILITY OF SUCH DAMAGE.
 
 import os, sys, inspect
 
-VERSION="2.1.0"
+VERSION="2.1.1"
 REVISION="x"
 GIT="x"
 INSTALL="x"

waflib/Context.py

@@ -18,13 +18,13 @@ else:
 	import imp
 
 # the following 3 constants are updated on each new release (do not touch)
-HEXVERSION=0x2010000
+HEXVERSION=0x2010100
 """Constant updated on new releases"""
 
-WAFVERSION="2.1.0"
+WAFVERSION="2.1.1"
 """Constant updated on new releases"""
 
-WAFREVISION="4e171c87adf3401e817a7d434f82aa9510ff0d72"
+WAFREVISION="bdd70055df77462fdf8967c3ede1de343ba05cce"
 """Git revision when the waf version is updated"""
 
 WAFNAME="waf"

waflib/Options.py

@@ -41,11 +41,10 @@ class ArgParser(argparse.ArgumentParser):
 	Command-line options parser.
 	"""
 	def __init__(self, ctx):
-		argparse.ArgumentParser.__init__(self, add_help=False)
+		argparse.ArgumentParser.__init__(self, add_help=False, conflict_handler='resolve')
 		self.ctx = ctx
 		self.usage = self.get_usage()
 
-
 	def _get_formatter(self):
 		"""Initialize the argument parser to the adequate terminal width"""
 		return self.formatter_class(prog=self.prog, width=Logs.get_term_cols())
@@ -134,7 +133,8 @@ class OptionsContext(Context.Context):
 		p('--zones',          dest='zones',   default='',    action='store', help='debugging zones (task_gen, deps, tasks, etc)')
 		p('--profile',        dest='profile', default=0,     action='store_true', help=argparse.SUPPRESS)
 		p('--pdb',            dest='pdb',     default=0,     action='store_true', help=argparse.SUPPRESS)
-		p('-h', '--help',     dest='whelp',   default=0,     action='store_true', help="show this help message and exit")
+		p('-h', '--help',     dest='whelp',   default=0,     action='store_true', help='show this help message and exit')
+		p('--version',        dest='version', default=False, action='store_true', help='show the Waf version and exit')
 
 		gr = self.add_option_group('Configuration options')
 
@@ -209,9 +209,12 @@ class OptionsContext(Context.Context):
 		return count
 
 	def add_option(self, *k, **kw):
-		if 'type' in kw and kw['type'] == 'int':
+		if 'type' in kw and type(kw['type']) == str:
 			Logs.warn('Invalid "type=str" in add_option (must be a class, not a string)')
-			kw['type'] = int
+			if kw['type'] == 'int':
+				kw['type'] = int
+			elif kw['type'] == 'string':
+				kw['type'] = str
 		return self.add_argument(*k, **kw)
 
 	def add_argument(self, *k, **kw):

waflib/Scripting.py

@@ -51,6 +51,9 @@ def waf_entry_point(current_directory, version, wafdir):
 
 	ctx = Context.create_context('options')
 	(options, commands) = ctx.parse_cmd_args(allow_unknown=True)
+	if options.version:
+		print('%s %s (%s)'%(Context.WAFNAME, Context.WAFVERSION, Context.WAFREVISION))
+		sys.exit(0)
 	if options.top:
 		start_dir = Context.run_dir = Context.top_dir = options.top
 		no_climb = True

waflib/TaskGen.py

@@ -619,9 +619,13 @@ def process_rule(self):
 		cls = Task.task_factory(name, rule, _vars, shell=shell, color=color)
 
 		if cls_str:
+			if isinstance(cls_str, str):
+				raise ValueError('cls_str should be a function %r' % self)
 			setattr(cls, '__str__', self.cls_str)
 
 		if cls_keyword:
+			if isinstance(cls_keyword, str):
+				raise ValueError('cls_keyword should be a function %r' % self)
 			setattr(cls, 'keyword', self.cls_keyword)
 
 		if deep_inputs:

waflib/Tools/cs.py

@@ -179,7 +179,7 @@ def options(opt):
 
 		$ waf configure --with-csc-binary=/foo/bar/mcs
 	"""
-	opt.add_option('--with-csc-binary', type='string', dest='cscbinary')
+	opt.add_option('--with-csc-binary', type=str, dest='cscbinary')
 
 class fake_csshlib(Task.Task):
 	"""

waflib/Tools/javaw.py

@@ -487,6 +487,15 @@ def configure(self):
 	for x in 'javac java jar javadoc'.split():
 		self.find_program(x, var=x.upper(), path_list=java_path, mandatory=(x not in ('javadoc')))
 
+	if not self.env.JAVA_HOME:
+		# needed for jni
+		if self.env.JAVAC and len(Utils.to_list(self.env.JAVAC)) == 1:
+			# heuristic to find the correct JAVA_HOME
+			javac_path = Utils.to_list(self.env.JAVAC)[0]
+			java_dir = os.path.dirname(os.path.dirname(os.path.realpath(javac_path)))
+			if os.path.exists(os.path.join(java_dir, 'lib')):
+				self.env.JAVA_HOME = [java_dir]
+
 	if 'CLASSPATH' in self.environ:
 		v.CLASSPATH = self.environ['CLASSPATH']
 
@@ -572,7 +581,7 @@ def check_jni_headers(conf):
 	f = dir.ant_glob('**/*jvm.(so|dll|dylib)')
 	libDirs = [x.parent.abspath() for x in f] or [javaHome]
 
-	# On windows, we need both the .dll and .lib to link.  On my JDK, they are
+	# On windows, we need both the .dll and .lib to link. On my JDK, they are
 	# in different directories...
 	f = dir.ant_glob('**/*jvm.(lib)')
 	if f:

waflib/Tools/msvc.py

@@ -99,8 +99,8 @@ def options(opt):
 		m = re.match(r'(^\d+\.\d+).*', vsver)
 		if m:
 			default_ver = 'msvc %s' % m.group(1)
-	opt.add_option('--msvc_version', type='string', help = 'msvc version, eg: "msvc 10.0,msvc 9.0"', default=default_ver)
-	opt.add_option('--msvc_targets', type='string', help = 'msvc targets, eg: "x64,arm"', default='')
+	opt.add_option('--msvc_version', type=str, help = 'msvc version, eg: "msvc 10.0,msvc 9.0"', default=default_ver)
+	opt.add_option('--msvc_targets', type=str, help = 'msvc targets, eg: "x64,arm"', default='')
 	opt.add_option('--no-msvc-lazy', action='store_false', help = 'lazily check msvc target environments', default=True, dest='msvc_lazy')
 
 class MSVCVersion(object):

waflib/Tools/perl.py

@@ -151,6 +151,6 @@ def options(opt):
 	"""
 	Add the ``--with-perl-archdir`` and ``--with-perl-binary`` command-line options.
 	"""
-	opt.add_option('--with-perl-binary', type='string', dest='perlbinary', help = 'Specify alternate perl binary', default=None)
-	opt.add_option('--with-perl-archdir', type='string', dest='perlarchdir', help = 'Specify directory where to install arch specific files', default=None)
+	opt.add_option('--with-perl-binary', type=str, dest='perlbinary', help = 'Specify alternate perl binary', default=None)
+	opt.add_option('--with-perl-archdir', type=str, dest='perlarchdir', help = 'Specify directory where to install arch specific files', default=None)
 

waflib/Tools/qt5.py

@@ -889,8 +889,8 @@ def options(opt):
 	"""
 	opt.add_option('--want-rpath', action='store_true', default=False, dest='want_rpath', help='enable the rpath for qt libraries')
 	for i in 'qtdir qtbin qtlibs'.split():
-		opt.add_option('--'+i, type='string', default='', dest=i)
+		opt.add_option('--'+i, type=str, default='', dest=i)
 
 	opt.add_option('--translate', action='store_true', help='collect translation strings', dest='trans_qt5', default=False)
-	opt.add_option('--qtextralibs', type='string', default='', dest='qtextralibs', help='additional qt libraries on the system to add to default ones, comma separated')
+	opt.add_option('--qtextralibs', type=str, default='', dest='qtextralibs', help='additional qt libraries on the system to add to default ones, comma separated')
 

waflib/Tools/ruby.py

@@ -180,7 +180,7 @@ def options(opt):
 	"""
 	Add the ``--with-ruby-archdir``, ``--with-ruby-libdir`` and ``--with-ruby-binary`` options
 	"""
-	opt.add_option('--with-ruby-archdir', type='string', dest='rubyarchdir', help='Specify directory where to install arch specific files')
-	opt.add_option('--with-ruby-libdir', type='string', dest='rubylibdir', help='Specify alternate ruby library path')
-	opt.add_option('--with-ruby-binary', type='string', dest='rubybinary', help='Specify alternate ruby binary')
+	opt.add_option('--with-ruby-archdir', type=str, dest='rubyarchdir', help='Specify directory where to install arch specific files')
+	opt.add_option('--with-ruby-libdir', type=str, dest='rubylibdir', help='Specify alternate ruby library path')
+	opt.add_option('--with-ruby-binary', type=str, dest='rubybinary', help='Specify alternate ruby binary')
 

waflib/extras/boost.py

@@ -131,28 +131,28 @@ BOOST_TOOLSETS = {
 
 def options(opt):
 	opt = opt.add_option_group('Boost Options')
-	opt.add_option('--boost-includes', type='string',
+	opt.add_option('--boost-includes', type=str,
 				   default='', dest='boost_includes',
 				   help='''path to the directory where the boost includes are,
 				   e.g., /path/to/boost_1_55_0/stage/include''')
-	opt.add_option('--boost-libs', type='string',
+	opt.add_option('--boost-libs', type=str,
 				   default='', dest='boost_libs',
 				   help='''path to the directory where the boost libs are,
 				   e.g., path/to/boost_1_55_0/stage/lib''')
 	opt.add_option('--boost-mt', action='store_true',
 				   default=False, dest='boost_mt',
 				   help='select multi-threaded libraries')
-	opt.add_option('--boost-abi', type='string', default='', dest='boost_abi',
+	opt.add_option('--boost-abi', type=str, default='', dest='boost_abi',
 				   help='''select libraries with tags (gd for debug, static is automatically added),
 				   see doc Boost, Getting Started, chapter 6.1''')
 	opt.add_option('--boost-linkage_autodetect', action="store_true", dest='boost_linkage_autodetect',
 				   help="auto-detect boost linkage options (don't get used to it / might break other stuff)")
-	opt.add_option('--boost-toolset', type='string',
+	opt.add_option('--boost-toolset', type=str,
 				   default='', dest='boost_toolset',
 				   help='force a toolset e.g. msvc, vc90, \
 						gcc, mingw, mgw45 (default: auto)')
 	py_version = '%d%d' % (sys.version_info[0], sys.version_info[1])
-	opt.add_option('--boost-python', type='string',
+	opt.add_option('--boost-python', type=str,
 				   default=py_version, dest='boost_python',
 				   help='select the lib python with this version \
 						(default: %s)' % py_version)

waflib/extras/build_file_timestamp.py

@@ -3,12 +3,11 @@
 # Thomas Nagy, 2015
 
 """
-Force files to depend on the timestamps of those located in the build directory. You may
+Force files to also depend on the timestamps of those located in the build directory. You may
 want to use this to force partial rebuilds, see playground/track_output_files/ for a working example.
 
 Note that there is a variety of ways to implement this, one may want use timestamps on source files too for example,
-or one may want to hash the files in the source directory only under certain conditions (md5_tstamp tool)
-or to hash the file in the build directory with its timestamp
+or one may want to hash theA files in the source directory only under certain conditions (md5_tstamp tool)
 """
 
 import os
@@ -18,11 +17,8 @@ def get_bld_sig(self):
 	if not self.is_bld() or self.ctx.bldnode is self.ctx.srcnode:
 		return Utils.h_file(self.abspath())
 
-	try:
-		# add the creation time to the signature
-		return self.sig + str(os.stat(self.abspath()).st_mtime)
-	except AttributeError:
-		return None
+	val = Utils.h_file(self.abspath()) + str(os.stat(self.abspath()).st_mtime).encode('latin-1')
+	return val
 
 Node.Node.get_bld_sig = get_bld_sig
 

waflib/extras/cpplint.py

@@ -59,23 +59,23 @@ CPPLINT_STR = ('${CPPLINT} '
 
 
 def options(opt):
-    opt.add_option('--cpplint-filters', type='string',
+    opt.add_option('--cpplint-filters', type=str,
                    default='', dest='CPPLINT_FILTERS',
                    help='add filters to cpplint')
-    opt.add_option('--cpplint-length', type='int',
+    opt.add_option('--cpplint-length', type=int,
                    default=80, dest='CPPLINT_LINE_LENGTH',
                    help='specify the line length (default: 80)')
-    opt.add_option('--cpplint-level', default=1, type='int', dest='CPPLINT_LEVEL',
+    opt.add_option('--cpplint-level', default=1, type=int, dest='CPPLINT_LEVEL',
                    help='specify the log level (default: 1)')
-    opt.add_option('--cpplint-break', default=5, type='int', dest='CPPLINT_BREAK',
+    opt.add_option('--cpplint-break', default=5, type=int, dest='CPPLINT_BREAK',
                    help='break the build if error >= level (default: 5)')
-    opt.add_option('--cpplint-root', type='string',
+    opt.add_option('--cpplint-root', type=str,
                    default='', dest='CPPLINT_ROOT',
                    help='root directory used to derive header guard')
     opt.add_option('--cpplint-skip', action='store_true',
                    default=False, dest='CPPLINT_SKIP',
                    help='skip cpplint during build')
-    opt.add_option('--cpplint-output', type='string',
+    opt.add_option('--cpplint-output', type=str,
                    default='waf', dest='CPPLINT_OUTPUT',
                    help='select output format (waf, emacs, vs7, eclipse)')
 

waflib/extras/dcc.py

@@ -68,5 +68,5 @@ def options(opt):
 	"""
 	Add the ``--with-diab-bindir`` command-line options.
 	"""
-	opt.add_option('--with-diab-bindir', type='string', dest='diabbindir', help = 'Specify alternate diab bin folder', default="")
+	opt.add_option('--with-diab-bindir', type=str, dest='diabbindir', help = 'Specify alternate diab bin folder', default="")
 

waflib/extras/fc_flang.py

@@ -0,0 +1,96 @@
+#! /usr/bin/env python
+# encoding: utf-8
+# Detection of the flang Fortran compiler
+
+import re
+from waflib.Tools import fc,fc_config,fc_scan
+from waflib.Configure import conf
+from waflib.Tools.compiler_fc import fc_compiler
+fc_compiler['linux'].append('fc_flang')
+
+@conf
+def find_flang(conf):
+	fc = conf.find_program(['flang'], var='FC')
+	conf.get_nfort_version(fc)
+	conf.env.FC_NAME = 'FLANG'
+	conf.env.FC_MOD_CAPITALIZATION = 'lower'
+
+@conf
+def flang_flags(conf):
+	v = conf.env
+	v['_FCMODOUTFLAGS'] = []
+	v['FCFLAGS_DEBUG'] = []
+	v['FCFLAGS_fcshlib'] = []
+	v['LINKFLAGS_fcshlib'] = []
+	v['FCSTLIB_MARKER'] = ''
+	v['FCSHLIB_MARKER'] = ''
+
+@conf
+def get_flang_version(conf, fc):
+	cmd = fc + ['-dM', '-E', '-']
+	env = conf.env.env or None
+
+	try:
+		out, err = conf.cmd_and_log(cmd, output=0, input='\n'.encode(), env=env)
+	except Errors.WafError:
+		conf.fatal('Could not determine the FLANG compiler version for %r' % cmd)
+	if out.find('__clang__') < 0:
+		conf.fatal('Not a flang compiler')
+
+	k = {}
+	out = out.splitlines()
+	for line in out:
+		lst = shlex.split(line)
+		if len(lst)>2:
+			key = lst[1]
+			val = lst[2]
+			k[key] = val
+
+	def isD(var):
+		return var in k
+
+	# Some documentation is available at http://predef.sourceforge.net
+	# The names given to DEST_OS must match what Utils.unversioned_sys_platform() returns.
+	if not conf.env.DEST_OS:
+		conf.env.DEST_OS = ''
+	for i in MACRO_TO_DESTOS:
+		if isD(i):
+			conf.env.DEST_OS = MACRO_TO_DESTOS[i]
+			break
+	else:
+		if isD('__APPLE__') and isD('__MACH__'):
+			conf.env.DEST_OS = 'darwin'
+		elif isD('__unix__'): # unix must be tested last as it's a generic fallback
+			conf.env.DEST_OS = 'generic'
+
+	if isD('__ELF__'):
+		conf.env.DEST_BINFMT = 'elf'
+	elif isD('__WINNT__') or isD('__CYGWIN__') or isD('_WIN32'):
+		conf.env.DEST_BINFMT = 'pe'
+		if not conf.env.IMPLIBDIR:
+			conf.env.IMPLIBDIR = conf.env.LIBDIR # for .lib or .dll.a files
+		conf.env.LIBDIR = conf.env.BINDIR
+	elif isD('__APPLE__'):
+		conf.env.DEST_BINFMT = 'mac-o'
+
+	if not conf.env.DEST_BINFMT:
+		# Infer the binary format from the os name.
+		conf.env.DEST_BINFMT = Utils.destos_to_binfmt(conf.env.DEST_OS)
+
+	for i in MACRO_TO_DEST_CPU:
+		if isD(i):
+			conf.env.DEST_CPU = MACRO_TO_DEST_CPU[i]
+			break
+
+	Logs.debug('fc_flang: dest platform: ' + ' '.join([conf.env[x] or '?' for x in ('DEST_OS', 'DEST_BINFMT', 'DEST_CPU')]))
+	conf.env.FC_VERSION = (k['__clang_major__'], k['__clang_minor__'], k['__clang_patchlevel__'])
+
+	return k
+
+
+def configure(conf):
+	conf.find_flang()
+	conf.find_ar()
+	conf.fc_flags()
+	conf.fc_add_flags()
+	conf.flang_flags()

waflib/extras/freeimage.py

@@ -32,7 +32,7 @@ from waflib.Configure import conf
 
 
 def options(opt):
-	opt.add_option('--fi-path', type='string', default='', dest='fi_path',
+	opt.add_option('--fi-path', type=str, default='', dest='fi_path',
 				   help='''path to the FreeImage directory \
 						where the files are e.g. /FreeImage/Dist''')
 	opt.add_option('--fip', action='store_true', default=False, dest='fip',

waflib/extras/parallel_debug.py

@@ -454,9 +454,9 @@ def make_picture(producer):
 def options(opt):
 	opt.add_option('--dtitle', action='store', default='Parallel build representation for %r' % ' '.join(sys.argv),
 		help='title for the svg diagram', dest='dtitle')
-	opt.add_option('--dwidth', action='store', type='int', help='diagram width', default=800, dest='dwidth')
-	opt.add_option('--dtime', action='store', type='float', help='recording interval in seconds', default=0.009, dest='dtime')
-	opt.add_option('--dband', action='store', type='int', help='band width', default=22, dest='dband')
-	opt.add_option('--dmaxtime', action='store', type='float', help='maximum time, for drawing fair comparisons', default=0, dest='dmaxtime')
+	opt.add_option('--dwidth', action='store', type=int, help='diagram width', default=800, dest='dwidth')
+	opt.add_option('--dtime', action='store', type=float, help='recording interval in seconds', default=0.009, dest='dtime')
+	opt.add_option('--dband', action='store', type=int, help='band width', default=22, dest='dband')
+	opt.add_option('--dmaxtime', action='store', type=float, help='maximum time, for drawing fair comparisons', default=0, dest='dmaxtime')
 	opt.add_option('--dnotooltip', action='store_true', help='disable tooltips', default=False, dest='dnotooltip')
 

waflib/extras/qt4.py

@@ -683,13 +683,13 @@ def options(opt):
 	opt.add_option('--want-rpath', action='store_true', default=False, dest='want_rpath', help='enable the rpath for qt libraries')
 
 	opt.add_option('--header-ext',
-		type='string',
+		type=str,
 		default='',
 		help='header extension for moc files',
 		dest='qt_header_ext')
 
 	for i in 'qtdir qtbin qtlibs'.split():
-		opt.add_option('--'+i, type='string', default='', dest=i)
+		opt.add_option('--'+i, type=str, default='', dest=i)
 
 	opt.add_option('--translate', action="store_true", help="collect translation strings", dest="trans_qt4", default=False)
 

waflib/extras/rst.py

@@ -39,7 +39,7 @@ rst_progs = "rst2html rst2xetex rst2latex rst2xml rst2pdf rst2s5 rst2man rst2odt
 def parse_rst_node(task, node, nodes, names, seen, dirs=None):
 	# TODO add extensibility, to handle custom rst include tags...
 	if dirs is None:
-		dirs = (node.parent,node.get_bld().parent)
+		dirs = (node.parent, node.parent.get_bld())
 
 	if node in seen:
 		return

waflib/extras/scala.py

@@ -32,6 +32,7 @@ def apply_scalac(self):
 	else:
 		outdir = self.path.get_bld()
 	outdir.mkdir()
+	self.outdir = outdir
 	self.env['OUTDIR'] = outdir.abspath()
 
 	self.scalac_task = tsk = self.create_task('scalac')

waflib/extras/slow_qt.py

@@ -4,23 +4,23 @@
 """
 Create _moc.cpp files
 
-The builds are 30-40% faster when .moc files are included,
-you should NOT use this tool. If you really
-really want it:
+The builds are 30-40% faster when .moc files are directly included,
+so the usage of this tool is discouraged.
 
 def configure(conf):
-	conf.load('compiler_cxx qt4')
-	conf.load('slow_qt4')
+	conf.load('compiler_cxx qt5')
+	conf.load('slow_qt')
 
-See playground/slow_qt/wscript for a complete example.
+See playground/slow_qt/wscript for a complete example,
+and run with "waf --zones=slow_qt" to display the moc files that should be generated
 """
 
 from waflib.TaskGen import extension
-from waflib import Task
-import waflib.Tools.qt4
+from waflib import Task, Logs
+import waflib.Tools.qt5
 import waflib.Tools.cxx
 
-@extension(*waflib.Tools.qt4.EXT_QT4)
+@extension(*waflib.Tools.qt5.EXT_QT5)
 def cxx_hook(self, node):
 	return self.create_compiled_task('cxx_qt', node)
 
@@ -28,7 +28,6 @@ class cxx_qt(Task.classes['cxx']):
 	def runnable_status(self):
 		ret = Task.classes['cxx'].runnable_status(self)
 		if ret != Task.ASK_LATER and not getattr(self, 'moc_done', None):
-
 			try:
 				cache = self.generator.moc_cache
 			except AttributeError:
@@ -49,19 +48,23 @@ class cxx_qt(Task.classes['cxx']):
 							# no corresponding file, continue
 							continue
 
-					# the file foo.cpp could be compiled for a static and a shared library - hence the %number in the name
-					cxx_node = x.parent.get_bld().make_node(x.name.replace('.', '_') + '_%d_moc.cpp' % self.generator.idx)
+					# the file foo.cpp could be compiled for a static and a shared library
+					# one workaround is to use a %number in the name
+					#cxx_node = x.parent.get_bld().make_node(x.name.replace('.', '_') + '_%d_moc.cpp' % self.generator.idx)
+
+					# another workaround is to add the target name
+					cxx_node = x.parent.get_bld().make_node(x.name.replace('.', '_') + '_%s_moc.cpp' % self.generator.name)
 					if cxx_node in cache:
 						continue
 					cache[cxx_node] = self
 
+					Logs.debug('slow_qt: will create a file named %s', cxx_node.abspath())
+
 					tsk = Task.classes['moc'](env=self.env, generator=self.generator)
 					tsk.set_inputs(x)
 					tsk.set_outputs(cxx_node)
 
 					if x.name.endswith('.cpp'):
-						# moc is trying to be too smart but it is too dumb:
-						# why forcing the #include when Q_OBJECT is in the cpp file?
 						gen = self.generator.bld.producer
 						gen.outstanding.append(tsk)
 						gen.total += 1
@@ -93,4 +96,3 @@ class cxx_qt(Task.classes['cxx']):
 				return Task.ASK_LATER
 
 		return ret
-

waflib/extras/softlink_libs.py

@@ -8,7 +8,7 @@ from os import tmpfile, linesep
 
 def options(opt):
 	grp = opt.add_option_group('Softlink Libraries Options')
-	grp.add_option('--exclude', default='/usr/lib,/lib', help='No symbolic links are created for libs within [%default]')
+	grp.add_option('--exclude', default='/usr/lib,/lib', help='No symbolic links are created for libs within [%(default)s]')
 
 def configure(cnf):
 	cnf.find_program('ldd')

waflib/extras/ticgt.py

@@ -160,16 +160,16 @@ def ti_dsplink_set_platform_flags(cfg, splat, dsp, dspbios_ver, board):
 
 
 def options(opt):
-	opt.add_option('--with-ti-cgt', type='string', dest='ti-cgt-dir', help = 'Specify alternate cgt root folder', default="")
-	opt.add_option('--with-ti-biosutils', type='string', dest='ti-biosutils-dir', help = 'Specify alternate biosutils folder', default="")
-	opt.add_option('--with-ti-dspbios', type='string', dest='ti-dspbios-dir', help = 'Specify alternate dspbios folder', default="")
-	opt.add_option('--with-ti-dsplink', type='string', dest='ti-dsplink-dir', help = 'Specify alternate dsplink folder', default="")
-	opt.add_option('--with-ti-xdctools', type='string', dest='ti-xdctools-dir', help = 'Specify alternate xdctools folder', default="")
+	opt.add_option('--with-ti-cgt', type=str, dest='ti-cgt-dir', help = 'Specify alternate cgt root folder', default="")
+	opt.add_option('--with-ti-biosutils', type=str, dest='ti-biosutils-dir', help = 'Specify alternate biosutils folder', default="")
+	opt.add_option('--with-ti-dspbios', type=str, dest='ti-dspbios-dir', help = 'Specify alternate dspbios folder', default="")
+	opt.add_option('--with-ti-dsplink', type=str, dest='ti-dsplink-dir', help = 'Specify alternate dsplink folder', default="")
+	opt.add_option('--with-ti-xdctools', type=str, dest='ti-xdctools-dir', help = 'Specify alternate xdctools folder', default="")
 
 class ti_cprogram(cprogram):
 	"""
 	Link object files into a c program
-	
+
 	Changes:
 
 	- the linked executable to have a relative path (because we can)

waflib/extras/unity.py

@@ -38,7 +38,7 @@ EXTS_CXX = ('.cpp','.cc','.cxx','.C','.c++')
 
 def options(opt):
 	global MAX_BATCH
-	opt.add_option('--batchsize', action='store', dest='batchsize', type='int', default=MAX_BATCH,
+	opt.add_option('--batchsize', action='store', dest='batchsize', type=int, default=MAX_BATCH,
 		help='default unity batch size (0 disables unity builds)')
 
 @TaskGen.taskgen_method

waflib/fixpy2.py

@@ -2,66 +2,29 @@
 # encoding: utf-8
 # Thomas Nagy, 2010-2018 (ita)
 
-from __future__ import with_statement
-
 import os
 
 all_modifs = {}
 
 def fixdir(dir):
 	"""Call all substitution functions on Waf folders"""
-	for k in all_modifs:
-		for v in all_modifs[k]:
-			modif(os.path.join(dir, 'waflib'), k, v)
+	for y in '. Tools extras'.split():
+		for x in os.listdir(os.path.join(dir, 'waflib', y)):
+			if x.endswith('.py'):
+				filename = os.path.join(dir, 'waflib', y, x)
+				update(filename)
 
-def modif(dir, name, fun):
-	"""Call a substitution function"""
-	if name == '*':
-		lst = []
-		for y in '. Tools extras'.split():
-			for x in os.listdir(os.path.join(dir, y)):
-				if x.endswith('.py'):
-					lst.append(y + os.sep + x)
-		for x in lst:
-			modif(dir, x, fun)
-		return
-
-	filename = os.path.join(dir, name)
+def update(filename):
 	with open(filename, 'r') as f:
 		txt = f.read()
 
-	txt = fun(txt)
+	txt = txt.replace(".decode(sys.stdout.encoding or'latin-1',errors='replace')", '')
+	txt = txt.replace('.encode()', '')
+	txt = txt.replace('class Task(metaclass=store_task_type):', "class Task(object):%s\t__metaclass__=store_task_type" % os.linesep)
 
 	with open(filename, 'w') as f:
 		f.write(txt)
 
-def subst(*k):
-	"""register a substitution function"""
-	def do_subst(fun):
-		for x in k:
-			try:
-				all_modifs[x].append(fun)
-			except KeyError:
-				all_modifs[x] = [fun]
-		return fun
-	return do_subst
-
-@subst('*')
-def r1(code):
-	"utf-8 fixes for python < 2.6"
-	code = code.replace('as e:', ',e:')
-	code = code.replace(".decode(sys.stdout.encoding or'latin-1',errors='replace')", '')
-	return code.replace('.encode()', '')
-
-@subst('Runner.py')
-def r4(code):
-	"generator syntax"
-	return code.replace('next(self.biter)', 'self.biter.next()').replace('self.daemon = True', 'self.setDaemon(1)')
-
-@subst('Context.py')
-def r5(code):
-	return code.replace("('Execution failure: %s'%str(e),ex=e)", "('Execution failure: %s'%str(e),ex=e),None,sys.exc_info()[2]")
-
-@subst('Task.py')
-def r6(code):
-	return code.replace('class Task(metaclass=store_task_type):', "class Task(object):%s\t__metaclass__=store_task_type" % os.linesep)
+	for k in all_modifs:
+		for v in all_modifs[k]:
+			modif(os.path.join(dir, 'waflib'), k, v)

wscript

@@ -11,7 +11,7 @@ To add a tool that does not exist in the folder compat15, pass an absolute path:
 
 from __future__ import with_statement
 
-VERSION="2.1.0"
+VERSION="2.1.1"
 APPNAME='waf'
 REVISION=''