2020-01-01 07:20:01 +01:00
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# Copyright 2014-2020 Free Software Foundation, Inc.
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x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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# Test alternating between watchpoint types, watching a sliding window
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# of addresses (thus alternating between aligned and unaligned
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# addresses). Only a single watchpoint exists at any given time. On
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# targets that only update the debug registers on resume, this
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# stresses the debug register setup code, both in GDB and in the
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# target/kernel as one watchpoint replaces the other in a single
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# operation. (Note that we don't have any of these watchpoints
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# trigger.)
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standard_testfile
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if {[prepare_for_testing "failed to prepare" $testfile $srcfile debug]} {
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return -1
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}
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if ![runto_main] then {
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2016-12-01 21:40:05 +01:00
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fail "can't run to main"
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x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
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return 0
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}
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# The line we'll be stepping.
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set srcline [gdb_get_line_number "stepi line"]
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# The address the program is stopped at currently.
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set cur_addr ""
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# Get the current PC.
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proc get_pc {} {
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global hex gdb_prompt
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set addr ""
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set test "get PC"
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gdb_test_multiple "p /x \$pc" "$test" {
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-re " = ($hex).*$gdb_prompt $" {
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set addr $expect_out(1,string)
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pass "$test"
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}
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}
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return $addr
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}
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# Issue a stepi, and make sure the program advanced past the current
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# instruction (stored in the CUR_ADDR global).
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proc stepi {} {
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global hex gdb_prompt cur_addr
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set srcline " for (i = 0; i < 100000; i++); /* stepi line */"
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set test "stepi advanced"
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gdb_test_multiple "stepi" $test {
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2020-05-06 14:27:36 +02:00
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-re -wrap "[string_to_regexp $srcline]" {
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set addr [get_valueof "/x" "\$pc" "0"]
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x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
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if {$addr != $cur_addr} {
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pass $test
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} else {
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fail $test
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}
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2020-05-06 14:13:02 +02:00
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set cur_addr $addr
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x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
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}
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}
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}
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gdb_breakpoint $srcline
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gdb_continue_to_breakpoint "stepi line"
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2018-04-10 21:21:58 +02:00
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set cur_addr [get_pc]
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x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
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# The test tries various sequences of different types of watchpoints.
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# Probe for support first.
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2018-04-10 21:21:58 +02:00
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proc build_cmds_list {} {
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global gdb_prompt
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# So we get an immediate warning/error if the target doesn't support a
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# given watchpoint type.
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gdb_test_no_output "set breakpoint always-inserted on" \
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"Set breakpoints always inserted while building cmds list"
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# The list of supported commands. Below we'll probe for support and
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# add elements to this list.
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set cmds {}
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foreach cmd {"watch" "awatch" "rwatch"} {
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set test $cmd
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gdb_test_multiple "$cmd buf.byte\[0\]" $test {
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-re "You may have requested too many.*$gdb_prompt $" {
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unsupported $test
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}
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-re "Target does not support.*$gdb_prompt $" {
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unsupported $test
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}
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-re "Can't set read/access watchpoint when hardware watchpoints are disabled.*$gdb_prompt $" {
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unsupported $test
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}
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-re "$gdb_prompt $" {
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pass $test
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lappend cmds $cmd
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}
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}
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x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
|
2018-04-10 21:21:58 +02:00
|
|
|
delete_breakpoints
|
|
|
|
}
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
|
2018-04-10 21:21:58 +02:00
|
|
|
set test "hbreak"
|
|
|
|
gdb_test_multiple "hbreak main" $test {
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
-re "You may have requested too many.*$gdb_prompt $" {
|
|
|
|
unsupported $test
|
|
|
|
}
|
2018-04-10 21:21:58 +02:00
|
|
|
-re "No hardware breakpoint support.*$gdb_prompt $" {
|
2014-06-26 17:21:08 +02:00
|
|
|
unsupported $test
|
|
|
|
}
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
-re "$gdb_prompt $" {
|
|
|
|
pass $test
|
2018-04-10 21:21:58 +02:00
|
|
|
lappend cmds "hbreak"
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-04-10 21:21:58 +02:00
|
|
|
delete_breakpoints
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
|
2018-04-10 21:21:58 +02:00
|
|
|
return $cmds
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
}
|
|
|
|
|
2015-03-13 11:56:01 +01:00
|
|
|
# Return true if the memory range [buf.byte + OFFSET, +WIDTH] can be
|
|
|
|
# monitored by CMD, otherwise return false.
|
|
|
|
|
|
|
|
proc valid_addr_p {cmd offset width} {
|
|
|
|
|
|
|
|
if { [istarget "aarch64*-*-linux*"] } {
|
|
|
|
# The aarch64 Linux kernel port only accepts 4-byte aligned addresses
|
|
|
|
# for hardware breakpoints and 8-byte aligned addresses for hardware
|
|
|
|
# watchpoints. However, both GDB and GDBserver support unaligned
|
|
|
|
# watchpoints by using more than one properly aligned watchpoint
|
|
|
|
# registers to represent the whole unaligned region. Breakpoint
|
|
|
|
# addresses must still be aligned though.
|
|
|
|
if {$cmd == "hbreak" } {
|
|
|
|
if { [expr ($offset) % 4] != 0 } {
|
|
|
|
return 0
|
|
|
|
}
|
|
|
|
}
|
2015-04-10 17:23:13 +02:00
|
|
|
} elseif { [istarget "arm*-*-linux*"] } {
|
|
|
|
if { $cmd == "hbreak" } {
|
|
|
|
# Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
|
|
|
|
if { $width != 2 && $width != 4 } {
|
|
|
|
return 0
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
# Watchpoints can be of length 1, 2, 4 or 8 bytes.
|
|
|
|
if { [expr $width % 2] != 0 } {
|
|
|
|
return 0
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if { [expr ($offset) % 8] == 0 && $width == 8 } {
|
|
|
|
# If WIDTH is 8 byte, the address should be 8-byte aligned.
|
|
|
|
return 1
|
|
|
|
} elseif { [expr ($offset) % 4] == 0 } {
|
|
|
|
return 1
|
|
|
|
} elseif { [expr ($offset) % 4] == 2 && $width == 2 } {
|
|
|
|
# Halfword watchpoints and breakpoints.
|
|
|
|
return 1
|
|
|
|
} elseif { [expr ($offset) % 4] == 1 && $width == 1 && $cmd != "hbreak" } {
|
|
|
|
# Single byte watchpoints.
|
|
|
|
return 1
|
|
|
|
} else {
|
|
|
|
return 0
|
|
|
|
}
|
2015-03-13 11:56:01 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
return 1
|
|
|
|
}
|
|
|
|
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
# Watch WIDTH bytes at BASE + OFFSET. CMD specifices the specific
|
|
|
|
# type of watchpoint to use. If CMD is "hbreak", WIDTH is ignored.
|
2018-04-10 21:21:58 +02:00
|
|
|
# The HW_WP_P flag tells us if hardware watchpoints are enabled or
|
|
|
|
# not.
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
|
2018-04-10 21:21:58 +02:00
|
|
|
proc watch_command {cmd base offset width hw_wp_p} {
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
global srcfile srcline hex
|
|
|
|
|
|
|
|
if {$cmd == "hbreak"} {
|
|
|
|
set expr "*(buf.byte + $base + $offset)"
|
|
|
|
gdb_test "hbreak $expr" "Hardware assisted breakpoint \[0-9\]+ at $hex"
|
|
|
|
} elseif {$cmd == "watch"} {
|
|
|
|
set expr "*(buf.byte + $base + $offset)@$width"
|
2018-04-10 21:21:58 +02:00
|
|
|
|
|
|
|
if { ! $hw_wp_p } {
|
|
|
|
set wp_prefix "Watchpoint"
|
|
|
|
} else {
|
|
|
|
set wp_prefix "Hardware watchpoint"
|
|
|
|
}
|
|
|
|
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
gdb_test "$cmd $expr" \
|
2018-04-10 21:21:58 +02:00
|
|
|
"${wp_prefix} \[0-9\]+: [string_to_regexp $expr]"
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
} elseif {$cmd == "awatch"} {
|
|
|
|
set expr "*(buf.byte + $base + $offset)@$width"
|
|
|
|
gdb_test "$cmd $expr" \
|
|
|
|
"Hardware access \\(read/write\\) watchpoint \[0-9\]+: [string_to_regexp $expr]"
|
|
|
|
} elseif {$cmd == "rwatch"} {
|
|
|
|
set expr "*(buf.byte + $base + $offset)@$width"
|
|
|
|
gdb_test "$cmd $expr" \
|
|
|
|
"Hardware read watchpoint \[0-9\]+: [string_to_regexp $expr]"
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-04-10 21:21:58 +02:00
|
|
|
# Run the watchpoint tests (see the description at the top for details), the
|
|
|
|
# HW_WP_P flag tells us if hardware watchpoints are enabled or not.
|
|
|
|
proc run_watchpoints_tests {hw_wp_p} {
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
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2018-04-10 21:21:58 +02:00
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set cmds [build_cmds_list]
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x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
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2018-04-10 21:21:58 +02:00
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foreach always_inserted {"off" "on" } {
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gdb_test_no_output "set breakpoint always-inserted $always_inserted"
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foreach cmd1 $cmds {
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foreach cmd2 $cmds {
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for {set width 1} {$width < 4} {incr width} {
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x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
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2018-04-10 21:21:58 +02:00
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if {$cmd1 == "hbreak" && $cmd2 == "hbreak" \
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&& $width > 1} {
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# hbreak ignores WIDTH, no use testing more than
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# once.
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2015-03-13 11:56:01 +01:00
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continue
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}
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2018-04-10 21:21:58 +02:00
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for {set x 0} {$x < 4} {incr x} {
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if { ![valid_addr_p $cmd1 $x $width]
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|| ![valid_addr_p $cmd2 $x+1 $width] } {
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# Skip tests if requested address or length
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# of breakpoint or watchpoint don't meet
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# target or kernel requirements.
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continue
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x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
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}
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2018-04-10 21:21:58 +02:00
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set prefix "always-inserted $always_inserted: "
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append prefix "$cmd1 x $cmd2: "
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with_test_prefix "$prefix: width $width, iter $x" {
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with_test_prefix "base + 0" {
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watch_command $cmd1 $x 0 $width $hw_wp_p
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stepi
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gdb_test_no_output "delete \$bpnum"
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}
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with_test_prefix "base + 1" {
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watch_command $cmd2 $x 1 $width $hw_wp_p
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stepi
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gdb_test_no_output "delete \$bpnum"
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|
}
|
x86 Linux watchpoints: Couldn't write debug register: Invalid argument.
This patch fixes this on x86 Linux:
(gdb) watch *buf@2
Hardware watchpoint 8: *buf@2
(gdb) si
0x00000000004005a7 34 for (i = 0; i < 100000; i++); /* stepi line */
(gdb) del
Delete all breakpoints? (y or n) y
(gdb) watch *(buf+1)@1
Hardware watchpoint 9: *(buf+1)@1
(gdb) si
0x00000000004005a7 in main () at ../../../src/gdb/testsuite/gdb.base/watchpoint-reuse-slot.c:34
34 for (i = 0; i < 100000; i++); /* stepi line */
Couldn't write debug register: Invalid argument.
(gdb)
In the example above the debug registers are being switched from this
state:
CONTROL (DR7): 0000000000050101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601040, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
to this:
CONTROL (DR7): 0000000000010101 STATUS (DR6): 0000000000000000
DR0: addr=0x0000000000601041, ref.count=1 DR1: addr=0x0000000000000000, ref.count=0
DR2: addr=0x0000000000000000, ref.count=0 DR3: addr=0x0000000000000000, ref.count=0
That is, before, DR7 was setup for watching a 2 byte region starting
at what's in DR0 (0x601040).
And after, DR7 is setup for watching a 1 byte region starting at
what's in DR0 (0x601041).
We always write DR0..DR3 before DR7, because if we enable a slot's
bits in DR7, you need to have already written the corresponding
DR0..DR3 registers -- the kernel rejects the DR7 write with EINVAL
otherwise.
The error shown above is the opposite scenario. When we try to write
0x601041 to DR0, DR7's bits still indicate intent of watching a 2-byte
region. That DR0/DR7 combination is invalid, because 0x601041 is
unaligned. To watch two bytes, we'd have to use two slots. So the
kernel errors out with EINVAL.
Fix this by always first clearing DR7, then writing DR0..DR3, and then
setting DR7's bits.
A little optimization -- if we're disabling the last watchpoint, then
we can clear DR7 just once. The changes to nat/i386-dregs.c make that
easier to detect, and as bonus, they make it a little easier to make
sense of DR7 in the debug logs, as we no longer need to remember we're
seeing stale bits.
Tested on x86_64 Fedora 20, native and GDBserver.
This adds an exhaustive test that switches between many different
combinations of watchpoint types and addresses and widths.
gdb/
2014-06-23 Pedro Alves <palves@redhat.com>
* amd64-linux-nat.c (amd64_linux_prepare_to_resume): Clear
DR_CONTROL before setting DR0..DR3.
* i386-linux-nat.c (i386_linux_prepare_to_resume): Likewise.
* nat/i386-dregs.c (i386_remove_aligned_watchpoint): Clear all
bits of DR_CONTROL related to the debug register slot being
disabled. If all slots are vacant, clear local slowdown as well,
and assert DR_CONTROL is 0.
gdb/gdbserver/
2014-06-23 Pedro Alves <palves@redhat.com>
* linux-x86-low.c (x86_linux_prepare_to_resume): Clear DR_CONTROL
before setting DR0..DR3.
gdb/testsuite/
2014-06-23 Pedro Alves <palves@redhat.com>
* gdb.base/watchpoint-reuse-slot.c: New file.
* gdb.base/watchpoint-reuse-slot.exp: New file.
2014-06-23 17:44:04 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2018-04-10 21:21:58 +02:00
|
|
|
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# Based on HW_WP_P set whether hardware watchpoints can be used or
|
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# not, then call RUN_WATCHPOINTS_TESTS.
|
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proc setup_and_run_watchpoints_tests { hw_wp_p } {
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if {$hw_wp_p} {
|
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set prefix "hw-watch"
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} else {
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set prefix "sw-watch"
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}
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with_test_prefix $prefix {
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gdb_test_no_output "set can-use-hw-watchpoints ${hw_wp_p}"
|
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run_watchpoints_tests $hw_wp_p
|
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|
}
|
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}
|
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# Run tests with hardware watchpoints disabled, then again with them
|
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# enabled (if this target supports hardware watchpoints).
|
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if { ![target_info exists gdb,no_hardware_watchpoints]} {
|
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|
# Run test with H/W enabled.
|
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|
|
setup_and_run_watchpoints_tests 1
|
|
|
|
}
|
|
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# Run test with H/W disabled
|
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|
setup_and_run_watchpoints_tests 0
|