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binutils-gdb/opcodes/ChangeLog

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ubsan: m32r: left shift of negative value cpu/ * m32r.cpu (f-disp8): Avoid left shift of negative values. (f-disp16, f-disp24): Likewise. opcodes/ * m32r-ibld.c: Regenerate.
2020-01-03 22:41:43 +01:00
2020-01-04 Alan Modra <amodra@gmail.com>
* m32r-ibld.c: Regenerate.
ubsan: cr16: left shift cannot be represented in type 'int' * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2020-01-02 22:42:00 +01:00
2020-01-04 Alan Modra <amodra@gmail.com>
* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
ubsan: crx: left shift cannot be represented in type 'int' * crx-dis.c (match_opcode): Avoid shift left of signed value.
2020-01-02 21:37:17 +01:00
2020-01-04 Alan Modra <amodra@gmail.com>
* crx-dis.c (match_opcode): Avoid shift left of signed value.
ubsan: d30v: left shift cannot be represented in type 'int' * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2020-01-01 09:16:43 +01:00
2020-01-04 Alan Modra <amodra@gmail.com>
* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
Arm64: correct {su,us}dot SIMD encodings According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
2020-01-03 10:14:16 +01:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
Arm64: correct address index operands for LD1RO{H,W,D} Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03 10:16:44 +01:00
* aarch64-tbl.h (aarch64_opcode_table): Use
SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2020-01-03 Jan Beulich <jbeulich@suse.com>
* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
Arm64: correct {su,us}dot SIMD encodings According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
2020-01-03 10:14:16 +01:00
forms of SUDOT and USDOT.
Arm64: correct uzp{1,2} mnemonics According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
2020-01-03 10:13:31 +01:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
Arm64: correct address index operands for LD1RO{H,W,D} Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03 10:16:44 +01:00
* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
Arm64: correct uzp{1,2} mnemonics According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
2020-01-03 10:13:31 +01:00
uzip{1,2}.
* opcodes/aarch64-dis-2.c: Re-generate.
Arm64: correct 64-bit element fmmla encoding There's just one bit of difference to the 32-bit element form, as per the documentation.
2020-01-03 10:12:49 +01:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
Arm64: correct address index operands for LD1RO{H,W,D} Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03 10:16:44 +01:00
* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
Arm64: correct 64-bit element fmmla encoding There's just one bit of difference to the 32-bit element form, as per the documentation.
2020-01-03 10:12:49 +01:00
FMMLA encoding.
* opcodes/aarch64-dis-2.c: Re-generate.
Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02 15:10:40 +01:00
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
* z80-dis.c: Add support for eZ80 and Z80 instructions.
Re: Update year range in copyright notice of binutils files Add the ChangeLog entry.
2020-01-01 09:22:19 +01:00
2020-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2020-01-01 08:37:11 +01:00
For older changes see ChangeLog-2019
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
ChangeLog rotation
2020-01-01 08:37:11 +01:00
Copyright (C) 2020 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
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