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[ARM] Enable conditional Armv8-M instructions Newly introduced instructions common to ARMv8-M Baseline and Mainline are currently all marked as unconditional. However, all instructions but sg (ie. blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm) do actually support conditional execution. This patch fixes the definition of these instructions accordingly. 2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm conditionally executable and reindent parameters. * testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of aforementionned instructions.
2018-01-15 15:11:02 +01:00
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm
and vlstm conditionally executable and reindent parameters.
* testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of
aforementionned instructions.
[ARM] No IT usage deprecation for ARMv8-M Deprecations related to the use of the IT instruction introduced in Armv8-A do not apply to Armv8-M Baseline and mainline. However the warning logic do not distinguish between the various profiles and warn whenever the architecture version is 8. This patch adds a check to exclude M profile architectures from this warning. This works as expected when -march is specified on the command-line or a .arch/.cpu directive exist. However, in autodetection mode the CPU/architecture targeted is only known once the instructions have been all processed but this code is run when IT instruction is processed. It is therefore not possible to distinguish between Armv8-M and Armv8-A in that mode. The approach chosen here is not to warn in autodetection mode. The udf.d testcase that relied on that behavior to test deprecation warning for Armv8-A is therefore updated to explicitely pass -march=armv8-a. 2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M profile architecture or if in autodetection mode. Clarify that deprecation is for performance reason and concerns Armv8-A and Armv8-R. * testsuite/gas/arm/armv8-ar-bad.l: Adapt to new IT deprecation warning message. * testsuite/gas/arm/armv8-ar-it-bad.l: Likewise. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: Likewise. * testsuite/gas/arm/udf.l: Likewise. * testsuite/gas/arm/udf.d: Assemble for Armv8-A explicitely.
2018-01-15 15:09:28 +01:00
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M
profile architecture or if in autodetection mode. Clarify that
deprecation is for performance reason and concerns Armv8-A and Armv8-R.
* testsuite/gas/arm/armv8-ar-bad.l: Adapt to new IT deprecation warning
message.
* testsuite/gas/arm/armv8-ar-it-bad.l: Likewise.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: Likewise.
* testsuite/gas/arm/udf.l: Likewise.
* testsuite/gas/arm/udf.d: Assemble for Armv8-A explicitely.
Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodes
2018-01-15 13:09:11 +01:00
2018-01-15 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
Update pot files
2018-01-13 14:56:48 +01:00
2018-01-13 Nick Clifton <nickc@redhat.com>
* po/gas.pot: Regenerated.
Bump version number to 2.30.51 bfd/ * version.m4: Bump version to 2.30.51 * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2018-01-13 14:31:12 +01:00
2018-01-13 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
Add 2.30 markers to NEWS files. binutils/ * NEWS: Add marker for 2.30. gas/ * NEWS: Add marker for 2.30. ld/ * NEWS: Add marker for 2.30.
2018-01-13 14:20:55 +01:00
2018-01-13 Nick Clifton <nickc@redhat.com>
Add note about 2.30 branch creation to changelogs
2018-01-13 14:26:38 +01:00
2.30 branch created.
Add 2.30 markers to NEWS files. binutils/ * NEWS: Add marker for 2.30. gas/ * NEWS: Add marker for 2.30. ld/ * NEWS: Add marker for 2.30.
2018-01-13 14:20:55 +01:00
* NEWS: Add marker for 2.30.
Fix compile time warning building aout targeted architectures. Occasionally I build an out-of-tree a.out target (m68k-amigaos). After a system upgrade which included a newer compiler (clang 4) the build produces warnings like this: warning: macro expansion producing 'defined' has undefined behavior [-Wexpansion-to-defined] This is caused by the macro gas/config/aout_gnu.h:USE_EXTENDED_RELOC. Since it is in a header file, the warning triggers for several files. I am unsure what solution is preferable, thus I am suggesting two patches: a) keep the offending macro but define it explicitly to 0 and 1 b) replace the macro usage with its value where it is used. Either patch removes the warning for clang. I did not check with a recent GCC. * gas/config/aout_gnu.h (USE_EXTENDED_RELOC): Explicitly define to 0 and 1. Remove a dangling reference to "AMD 29000" in a comment.
2018-01-12 14:12:17 +01:00
2018-01-12 Gunther Nikl <gnikl@users.sourceforge.net>
* gas/config/aout_gnu.h (USE_EXTENDED_RELOC): Explicitly
define to 0 and 1. Remove a dangling reference to "AMD 29000"
in a comment.
Remove VL variants for 4FMAPS and 4VNNIW insns. AVX512_4FMAPS and AVX512_4VNNIW insns are marked as having AVX512VL variants. That is wrong as SDM doesn't define such instructions. The patch removes these VL variants. gas/ * testsuite/gas/i386/avx512_4fmaps-warn.l: Change xmm to zmm. * testsuite/gas/i386/avx512_4fmaps-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Delete _vl tests for 4fmaps an 4vnniw tests. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s: Likewise. opcodes/ * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. * i386-tbl.h: Regenerate.
2018-01-11 00:56:45 +01:00
2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* testsuite/i386/avx512_4fmaps_vl-warn.l: Likewise.
* testsuite/i386/avx512_4fmaps_vl-warn.s: Likewise.
* testsuite/i386/avx512_4fmaps_vl.d: Likewise.
* testsuite/i386/avx512_4fmaps_vl.s: Likewise.
* testsuite/i386/avx512_4vnniw_vl-intel.d: Likewise.
* testsuite/i386/avx512_4vnniw_vl.d: Likewise.
* testsuite/i386/avx512_4vnniw_vl.s: Likewise.
* testsuite/i386/i386.exp: Removed _vl tests for 4fmaps an 4vnniw
tests.
* testsuite/i386/x86-64-avx512_4fmaps_vl-intel.d: Removed.
* testsuite/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise.
* testsuite/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise.
* testsuite/i386/x86-64-avx512_4fmaps_vl.d: Likewise.
* testsuite/i386/x86-64-avx512_4fmaps_vl.s: Likewise.
* testsuite/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise.
* testsuite/i386/x86-64-avx512_4vnniw_vl.d: Likewise.
* testsuite/i386/x86-64-avx512_4vnniw_vl.s: Likewise.
gas tc-arm.c warning fix * config/tc-arm.c (aeabi_set_public_attributes): Avoid false positive "‘profile’ may be used uninitialized".
2018-01-11 00:04:58 +01:00
2018-01-11 Alan Modra <amodra@gmail.com>
* config/tc-arm.c (aeabi_set_public_attributes): Avoid false
positive "‘profile’ may be used uninitialized".
x86: fix Disp8 handling for scalar AVX512_4FMAPS insns Just like their packed counterparts the memory operand is always 16 bytes wide, and the Disp8 scaling is the same for all of them. (As a side note: I'm also surprised by there being AVX512VL variants of these as well as the AVX512_4VNNIW ones - the SDM doesn't define any such.) Adjust the test cases also for the packed forms to actually live up to their promise of testing correct Disp8 encoding.
2018-01-10 14:53:43 +01:00
2018-01-10 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512_4fmaps.s,
testsuite/gas/i386/avx512_4fmaps_vl.s,
testsuite/gas/i386/x86-64-avx512_4fmaps.s,
testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Actually test
Disp8 forms (and the transition happening at the right
boundary).
* testsuite/gas/i386/avx512_4fmaps.d,
testsuite/gas/i386/avx512_4fmaps-intel.d,
testsuite/gas/i386/avx512_4fmaps_vl.d,
testsuite/gas/i386/avx512_4fmaps_vl-intel.d,
testsuite/gas/i386/x86-64-avx512_4fmaps.d,
testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d,
testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d,
testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Adjust
expectations.
x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants In commit 2645e1d079 ("x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops") I screwed up the Disp8MemShift values of the AVX512VL variants.
2018-01-10 14:53:05 +01:00
2018-01-10 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512bw.s,
testsuite/gas/i386/avx512bw_vl.s: Add VPCMP* tests with memory
operands.
* testsuite/gas/i386/avx512bw-intel.d,
testsuite/gas/i386/avx512bw.d,
testsuite/gas/i386/avx512bw_vl-intel.d.
testsuite/gas/i386/avx512bw_vl.d: Adjust expectations.
RISC-V: Disassemble x0 based addresses as 0. gas/ * testsuite/gas/riscv/auipc-x0.d: New. * testsuite/gas/riscv/auipc-x0.s: New. opcodes/ * riscv-dis.c (maybe_print_address): If base_reg is zero, then the hi_addr value is zero.
2018-01-10 01:40:06 +01:00
2018-01-09 Jim Wilson <jimw@sifive.com>
* testsuite/gas/riscv/auipc-x0.d: New.
* testsuite/gas/riscv/auipc-x0.s: New.
[Arm] Add CSDB instruction CSDB is a new instruction which Arm has defined. As it shares the encoding space with NOP instructions, it is available from Armv3 in Arm mode, and Armv6T2 in Thumb mode. OK? If so, please commit on my behalf as I don't have commit rights over here. Thanks, James --- opcodes/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * arm-dis.c (arm_opcodes): Add csdb. (thumb32_opcodes): Add csdb. gas/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above in Arm execution state, and Armv6T2 and above in Thumb execution state. * testsuite/gas/arm/csdb.s: New. * testsuite/gas/arm/csdb.d: New. * testsuite/gas/arm/thumb2_it_bad.l: Add csdb. * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
2018-01-09 15:15:00 +01:00
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
in Arm execution state, and Armv6T2 and above in Thumb execution
state.
* testsuite/gas/arm/csdb.s: New.
* testsuite/gas/arm/csdb.d: New.
* testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
* testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
Add support for the AArch64's CSDB instruction. CSDB is a new instruction which Arm has defined. It has the same encoding as HINT #0x14 and is available at all architecture levels. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.d: Update expected results to expect CSDB.
2018-01-09 12:28:04 +01:00
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* testsuite/gas/aarch64/system.d: Update expected results to expect
CSDB for hint 0x14.
x86: Properly encode vmovd with 64-bit memeory For historical reason, we allow movd/vmovd with 64-bit register and memeory operands. But for vmovd, we failed to handle 64-bit memeory operand. This has been gone unnoticed since AT&T syntax always treats memory operand as 32-bit memory. This patch properly encodes vmovd with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit operands since GCC has case TYPE_SSEMOV: switch (get_attr_mode (insn)) { case MODE_DI: /* Handle broken assemblers that require movd instead of movq. */ if (!HAVE_AS_IX86_INTERUNIT_MOVQ && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) return "%vmovd\t{%1, %0|%0, %1}"; return "%vmovq\t{%1, %0|%0, %1}"; and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't generate AVX512 vmovd with 64-bit operand. gas/ PR gas/22681 * testsuite/gas/i386/i386.exp: Run x86-64-movd and x86-64-movd-intel. * testsuite/gas/i386/x86-64-movd-intel.d: New file. * testsuite/gas/i386/x86-64-movd.d: Likewise. * testsuite/gas/i386/x86-64-movd.s: Likewise. opcodes/ PR gas/22681 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. Remove AVX512 vmovd with 64-bit operands. * i386-tbl.h: Regenerated.
2018-01-08 13:36:59 +01:00
2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
PR gas/22681
* testsuite/gas/i386/i386.exp: Run x86-64-movd and
x86-64-movd-intel.
* testsuite/gas/i386/x86-64-movd-intel.d: New file.
* testsuite/gas/i386/x86-64-movd.d: Likewise.
* testsuite/gas/i386/x86-64-movd.s: Likewise.
Add a description of the X86_64 assembler's .largcomm pseudo-op. PR 22553 * doc/c-i386.texi (i386-Directives): Document the .largecomm directive.
2018-01-08 10:29:17 +01:00
2018-01-08 Nick Clifton <nickc@redhat.com>
PR 22553
* doc/c-i386.texi (i386-Directives): Document the .largecomm
directive.
RISC-V: Add 2 missing privileged registers. gas/ * testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval. * testsuite/gas/riscv/priv-reg.d: Likewise. include/ * opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL. (CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry. Add alias to map mbadaddr to CSR_MTVAL.
2018-01-04 23:17:53 +01:00
2018-01-04 Jim Wilson <jimw@sifive.com>
* testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval.
* testsuite/gas/riscv/priv-reg.d: Likewise.
Update year range in copyright notice of binutils files
2018-01-03 06:17:27 +01:00
2018-01-03 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
Fix typo in do_mrs function in ARM assembler. PR 18119 * config/tc-arm.c (do_mrs): Fix test of bits 16-19 in non-banked version of ARM MRS instruction.
2018-01-02 13:13:17 +01:00
2018-01-02 Nick Clifton <nickc@redhat.com>
PR 18119
* config/tc-arm.c (do_mrs): Fix test of bits 16-19 in non-banked
version of ARM MRS instruction.
ChangeLog rotation
2018-01-03 06:15:17 +01:00
For older changes see ChangeLog-2017
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
ChangeLog rotation
2018-01-03 06:15:17 +01:00
Copyright (C) 2018 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
Copying and distribution of this file, with or without modification,
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