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RISC-V: Disassemble x0 based addresses as 0. gas/ * testsuite/gas/riscv/auipc-x0.d: New. * testsuite/gas/riscv/auipc-x0.s: New. opcodes/ * riscv-dis.c (maybe_print_address): If base_reg is zero, then the hi_addr value is zero.
2018-01-10 01:40:06 +01:00
2018-01-09 Jim Wilson <jimw@sifive.com>
* riscv-dis.c (maybe_print_address): If base_reg is zero,
then the hi_addr value is zero.
[Arm] Add CSDB instruction CSDB is a new instruction which Arm has defined. As it shares the encoding space with NOP instructions, it is available from Armv3 in Arm mode, and Armv6T2 in Thumb mode. OK? If so, please commit on my behalf as I don't have commit rights over here. Thanks, James --- opcodes/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * arm-dis.c (arm_opcodes): Add csdb. (thumb32_opcodes): Add csdb. gas/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above in Arm execution state, and Armv6T2 and above in Thumb execution state. * testsuite/gas/arm/csdb.s: New. * testsuite/gas/arm/csdb.d: New. * testsuite/gas/arm/thumb2_it_bad.l: Add csdb. * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
2018-01-09 15:15:00 +01:00
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* arm-dis.c (arm_opcodes): Add csdb.
(thumb32_opcodes): Add csdb.
Add support for the AArch64's CSDB instruction. CSDB is a new instruction which Arm has defined. It has the same encoding as HINT #0x14 and is available at all architecture levels. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.d: Update expected results to expect CSDB.
2018-01-09 12:28:04 +01:00
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
x86: Properly encode vmovd with 64-bit memeory For historical reason, we allow movd/vmovd with 64-bit register and memeory operands. But for vmovd, we failed to handle 64-bit memeory operand. This has been gone unnoticed since AT&T syntax always treats memory operand as 32-bit memory. This patch properly encodes vmovd with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit operands since GCC has case TYPE_SSEMOV: switch (get_attr_mode (insn)) { case MODE_DI: /* Handle broken assemblers that require movd instead of movq. */ if (!HAVE_AS_IX86_INTERUNIT_MOVQ && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) return "%vmovd\t{%1, %0|%0, %1}"; return "%vmovq\t{%1, %0|%0, %1}"; and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't generate AVX512 vmovd with 64-bit operand. gas/ PR gas/22681 * testsuite/gas/i386/i386.exp: Run x86-64-movd and x86-64-movd-intel. * testsuite/gas/i386/x86-64-movd-intel.d: New file. * testsuite/gas/i386/x86-64-movd.d: Likewise. * testsuite/gas/i386/x86-64-movd.s: Likewise. opcodes/ PR gas/22681 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. Remove AVX512 vmovd with 64-bit operands. * i386-tbl.h: Regenerated.
2018-01-08 13:36:59 +01:00
2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
PR gas/22681
* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
Remove AVX512 vmovd with 64-bit operands.
* i386-tbl.h: Regenerated.
RISC-V: Print symbol address for jalr w/ zero offset. ld/ * testsuite/ld-riscv-elf/disas-jalr.d: New. * testsuite/ld-riscv-elf/disas-jalr.s: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run new testcase. opcodes/ * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a jalr.
2018-01-06 02:51:23 +01:00
2018-01-05 Jim Wilson <jimw@sifive.com>
* riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
jalr.
Update year range in copyright notice of binutils files
2018-01-03 06:17:27 +01:00
2018-01-03 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
x86: partial revert of 10c17abdd0 Other than the variables in tc-i386.c using them, OPERAND_TYPE_REGYMM and OPERAND_TYPE_REGZMM they aren't entirely unused. No need to update i386-init.h though, as it mistakenly wasn't updated by the original commit.
2018-01-02 11:44:04 +01:00
2018-01-02 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
and OPERAND_TYPE_REGZMM entries.
ChangeLog rotation
2018-01-03 06:15:17 +01:00
For older changes see ChangeLog-2017
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
ChangeLog rotation
2018-01-03 06:15:17 +01:00
Copyright (C) 2018 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
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