[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
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// Simulator definition for the micromips DSP ASE.
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2019-01-01 07:01:51 +01:00
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// Copyright (C) 2005-2019 Free Software Foundation, Inc.
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[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
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// Contributed by Imagination Technologies, Ltd.
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// Written by Andrew Bennett <andrew.bennett@imgtec.com>
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//
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// This file is part of the MIPS sim.
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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000000,5.RT,5.RS,0001000100,111100:POOL32A:32::ABSQ_S.PH
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"absq_s.ph r<RT>, r<RS>"
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*micromipsdsp:
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{
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do_ph_s_absq (SD_, RT, RS);
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}
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000000,5.RT,5.RS,0000000100,111100:POOL32A:32::ABSQ_S.QB
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"absq_s.qb r<RT>, r<RS>"
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*micromipsdsp:
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{
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do_qb_s_absq (SD_, RT, RS);
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}
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000000,5.RT,5.RS,0010000100,111100:POOL32A:32::ABSQ_S.W
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"absq_s.w r<RT>, r<RS>"
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*micromipsdsp:
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{
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do_w_s_absq (SD_, RT, RS);
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}
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000000,5.RT,5.RS,5.RD,00000,001101:POOL32A:32::ADDQ.PH
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"addq.ph r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_ph_op (SD_, RD, RS, RT, 0, 0);
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}
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000000,5.RT,5.RS,5.RD,10000,001101:POOL32A:32::ADDQ_S.PH
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"addq_s.ph r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_ph_op (SD_, RD, RS, RT, 0, 1);
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}
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000000,5.RT,5.RS,5.RD,01100,000101:POOL32A:32::ADDQ_S.W
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"addq_s.w r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_w_op (SD_, RD, RS, RT, 0);
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}
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000000,5.RT,5.RS,5.RD,00001,001101:POOL32A:32::ADDQH.PH
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"addqh.ph r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_qh_ph_op (SD_, RD, RS, RT, 0, 0);
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}
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000000,5.RT,5.RS,5.RD,10001,001101:POOL32A:32::ADDQH_R.PH
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"addqh_r.ph r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_qh_ph_op (SD_, RD, RS, RT, 0, 1);
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}
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000000,5.RT,5.RS,5.RD,00010,001101:POOL32A:32::ADDQH.W
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"addqh.w r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_qh_w_op (SD_, RD, RS, RT, 0, 0);
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}
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000000,5.RT,5.RS,5.RD,10010,001101:POOL32A:32::ADDQH_R.W
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"addqh_r.w r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_qh_w_op (SD_, RD, RS, RT, 0, 1);
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}
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000000,5.RT,5.RS,5.RD,01110,000101:POOL32A:32::ADDSC
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"addsc r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_addsc (SD_, RD, RS, RT);
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}
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000000,5.RT,5.RS,5.RD,00100,001101:POOL32A:32::ADDU.PH
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"addu.ph r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_u_ph_op (SD_, RD, RS, RT, 0, 0);
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}
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000000,5.RT,5.RS,5.RD,10100,001101:POOL32A:32::ADDU_S.PH
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"addu_s.ph r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_u_ph_op (SD_, RD, RS, RT, 0, 1);
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}
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000000,5.RT,5.RS,5.RD,00011,001101:POOL32A:32::ADDU.QB
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"addu.qb r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_qb_op (SD_, RD, RS, RT, 0, 0);
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}
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000000,5.RT,5.RS,5.RD,10011,001101:POOL32A:32::ADDU_S.QB
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"addu_s.qb r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_qb_op (SD_, RD, RS, RT, 0, 1);
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}
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000000,5.RT,5.RS,5.RD,01111,000101:POOL32A:32::ADDWC
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"addwc r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_addwc (SD_, RD, RS, RT);
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}
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000000,5.RT,5.RS,5.RD,00101,001101:POOL32A:32::ADDUH.QB
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"adduh.qb r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_uh_qb_op (SD_, RD, RS, RT, 0, 0);
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}
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000000,5.RT,5.RS,5.RD,10101,001101:POOL32A:32::ADDUH_R.QB
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"adduh_r.qb r<RD>, r<RS>, r<RT>"
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*micromipsdsp:
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{
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do_uh_qb_op (SD_, RD, RS, RT, 0, 1);
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}
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000000,5.RT,5.RS,5.SA,01000,010101:POOL32A:32::APPEND
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"append r<RT>, r<RS>, <SA>"
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*micromipsdsp:
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{
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do_append (SD_, RT, RS, SA);
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}
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000000,5.RT,5.RS,2.BP,00100010,111100:POOL32A:32::BALIGN
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"balign r<RT>, r<RS>, <BP>"
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*micromipsdsp:
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{
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do_balign (SD_, RT, RS, BP);
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}
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000000,5.RT,5.RS,0011000100,111100:POOL32A:32::BITREV
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"bitrev r<RT>, r<RS>"
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*micromipsdsp:
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{
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do_bitrev (SD_, RT, RS);
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}
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|
|
|
|
|
010000,1101100000,16.IMMEDIATE:POOL32I:32::BPOSGE32
|
|
|
|
"bposge32 <IMMEDIATE>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
|
|
|
|
if (pos >= 32)
|
|
|
|
NIA = delayslot_micromips (SD_, NIA + (EXTEND12 (IMMEDIATE) << 1), NIA,
|
|
|
|
MICROMIPS_DELAYSLOT_SIZE_ANY);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0000000000,000101:POOL32A:32::CMP.EQ.PH
|
|
|
|
"cmp.eq.ph r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_cmpu (SD_, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0000000001,000101:POOL32A:32::CMP.LT.PH
|
|
|
|
"cmp.lt.ph r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_cmpu (SD_, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0000000010,000101:POOL32A:32::CMP.LE.PH
|
|
|
|
"cmp.le.ph r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_cmpu (SD_, RS, RT, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00110,000101:POOL32A:32::CMPGDU.EQ.QB
|
|
|
|
"cmpgdu.eq.qb r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_cmpgdu (SD_, RD, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00111,000101:POOL32A:32::CMPGDU.LT.QB
|
|
|
|
"cmpgdu.lt.qb r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_cmpgdu (SD_, RD, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01000,000101:POOL32A:32::CMPGDU.LE.QB
|
|
|
|
"cmpgdu.le.qb r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_cmpgdu (SD_, RD, RS, RT, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00011,000101:POOL32A:32::CMPGU.EQ.QB
|
|
|
|
"cmpgu.eq.qb r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_cmpgu (SD_, RD, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00100,000101:POOL32A:32::CMPGU.LT.QB
|
|
|
|
"cmpgu.lt.qb r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_cmpgu (SD_, RD, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00101,000101:POOL32A:32::CMPGU.LE.QB
|
|
|
|
"cmpgu.le.qb r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_cmpgu (SD_, RD, RS, RT, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0000001001,000101:POOL32A:32::CMPU.EQ.QB
|
|
|
|
"cmpu.eq.qb r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_cmpu (SD_, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0000001010,000101:POOL32A:32::CMPU.LT.QB
|
|
|
|
"cmpu.lt.qb r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_cmpu (SD_, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0000001011,000101:POOL32A:32::CMPU.LE.QB
|
|
|
|
"cmpu.le.qb r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_cmpu (SD_, RS, RT, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,00000010,111100:POOL32A:32::DPA.W.PH
|
|
|
|
"dpa.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_ph_dot_product (SD_, AC, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,00001010,111100:POOL32A:32::DPAQ_S.W.PH
|
|
|
|
"dpaq_s.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_dot_product (SD_, AC, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,01001010,111100:POOL32A:32::DPAQ_SA.L.W
|
|
|
|
"dpaq_sa.l.w ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_dot_product (SD_, AC, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,10001010,111100:POOL32A:32::DPAQX_S.W.PH
|
|
|
|
"dpaqx_s.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,11001010,111100:POOL32A:32::DPAQX_SA.W.PH
|
|
|
|
"dpaqx_sa.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,10000010,111100:POOL32A:32::DPAU.H.QBL
|
|
|
|
"dpau.h.qbl ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_dot_product (SD_, AC, RS, RT, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,11000010,111100:POOL32A:32::DPAU.H.QBR
|
|
|
|
"dpau.h.qbr ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_dot_product (SD_, AC, RS, RT, 0, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,01000010,111100:POOL32A:32::DPAX.W.PH
|
|
|
|
"dpax.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_x_w_ph_dot_product (SD_, AC, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,00010010,111100:POOL32A:32::DPS.W.PH
|
|
|
|
"dps.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_ph_dot_product (SD_, AC, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,00011010,111100:POOL32A:32::DPSQ_S.W.PH
|
|
|
|
"dpsq_s.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_dot_product (SD_, AC, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,01011010,111100:POOL32A:32::DPSQ_SA.L.W
|
|
|
|
"dpsq_sa.l.w ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_dot_product (SD_, AC, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,10011010,111100:POOL32A:32::DPSQX_S.W.PH
|
|
|
|
"dpsqx_s.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,11011010,111100:POOL32A:32::DPSQX_SA.W.PH
|
|
|
|
"dpsqx_sa.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,10010010,111100:POOL32A:32::DPSU.H.QBL
|
|
|
|
"dpsu.h.qbl ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_dot_product (SD_, AC, RS, RT, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,11010010,111100:POOL32A:32::DPSU.H.QBR
|
|
|
|
"dpsu.h.qbr ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_dot_product (SD_, AC, RS, RT, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,01010010,111100:POOL32A:32::DPSX.W.PH
|
|
|
|
"dpsx.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_x_w_ph_dot_product (SD_, AC, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.SIZE,2.AC,10011001,111100:POOL32A:32::EXTP
|
|
|
|
"extp r<RT>, ac<AC>, <SIZE>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_extp (SD_, RT, AC, SIZE, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.SIZE,2.AC,11011001,111100:POOL32A:32::EXTPDP
|
|
|
|
"extpdp r<RT>, ac<AC>, <SIZE>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_extp (SD_, RT, AC, SIZE, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,11100010,111100:POOL32A:32::EXTPDPV
|
|
|
|
"extpdpv r<RT>, ac<AC>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_extpv (SD_, RT, AC, RS, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,10100010,111100:POOL32A:32::EXTPV
|
|
|
|
"extpv r<RT>, ac<AC>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_extpv (SD_, RT, AC, RS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.SHIFT,2.AC,00111001,111100:POOL32A:32::EXTR.W
|
|
|
|
"extr.w r<RT>, ac<AC>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_extr (SD_, RT, AC, SHIFT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.SHIFT,2.AC,01111001,111100:POOL32A:32::EXTR_R.W
|
|
|
|
"extr_r.w r<RT>, ac<AC>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_extr (SD_, RT, AC, SHIFT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.SHIFT,2.AC,10111001,111100:POOL32A:32::EXTR_RS.W
|
|
|
|
"extr_rs.w r<RT>, ac<AC>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_extr (SD_, RT, AC, SHIFT, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.SHIFT,2.AC,11111001,111100:POOL32A:32::EXTR_S.H
|
|
|
|
"extr_s.h r<RT>, ac<AC>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_h_extr (SD_, RT, AC, SHIFT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,00111010,111100:POOL32A:32::EXTRV.W
|
|
|
|
"extrv.w r<RT>, ac<AC>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_extrv (SD_, RT, AC, RS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,01111010,111100:POOL32A:32::EXTRV_R.W
|
|
|
|
"extrv_r.w r<RT>, ac<AC>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_extrv (SD_, RT, AC, RS, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,10111010,111100:POOL32A:32::EXTRV_RS.W
|
|
|
|
"extrv_rs.w r<RT>, ac<AC>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_extrv (SD_, RT, AC, RS, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,11111010,111100:POOL32A:32::EXTRV_S.H
|
|
|
|
"extrv_s.h r<RT>, ac<AC>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_extrv_s_h (SD_, RT, AC, RS);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0100000100,111100:POOL32A:32::INSV
|
|
|
|
"insv r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_insv (SD_, RT, RS);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.INDEX,5.BASE,5.RD,01000,100101:POOL32A:32::LBUX
|
|
|
|
"lbux r<RD>, r<INDEX>(r<BASE>)"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_lxx (SD_, RD, BASE, INDEX, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.INDEX,5.BASE,5.RD,00101,100101:POOL32A:32::LHX
|
|
|
|
"lhx r<RD>, r<INDEX>(r<BASE>)"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_lxx (SD_, RD, BASE, INDEX, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.INDEX,5.BASE,5.RD,00110,100101:POOL32A:32::LWX
|
|
|
|
"lwx r<RD>, r<INDEX>(r<BASE>)"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_lxx (SD_, RD, BASE, INDEX, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,00101010,111100:POOL32A:32::MADD_DSP
|
|
|
|
"madd ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_dsp_madd (SD_, AC, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,01101010,111100:POOL32A:32::MADDU_DSP
|
|
|
|
"maddu ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_dsp_maddu (SD_, AC, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,01101001,111100:POOL32A:32::MAQ_S.W.PHL
|
|
|
|
"maq_s.w.phl ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_maq (SD_, AC, RS, RT, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,11101001,111100:POOL32A:32::MAQ_SA.W.PHL
|
|
|
|
"maq_sa.w.phl ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_maq (SD_, AC, RS, RT, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,00101001,111100:POOL32A:32::MAQ_S.W.PHR
|
|
|
|
"maq_s.w.phr ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_maq (SD_, AC, RS, RT, 0, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,10101001,111100:POOL32A:32::MAQ_SA.W.PHR
|
|
|
|
"maq_sa.w.phr ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_maq (SD_, AC, RS, RT, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,00000,5.RS,2.AC,00000001,111100:POOL32A:32::MFHI_DSP
|
|
|
|
"mfhi r<RS>, ac<AC>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_dsp_mfhi (SD_, AC, RS);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,00000,5.RS,2.AC,01000001,111100:POOL32A:32::MFLO_DSP
|
|
|
|
"mflo r<RS>, ac<AC>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_dsp_mflo (SD_, AC, RS);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01010,010101:POOL32A:32::MODSUB
|
|
|
|
"modsub r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_modsub (SD_, RD, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,10101010,111100:POOL32A:32::MSUB_DSP
|
|
|
|
"msub ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_dsp_msub (SD_, AC, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,11101010,111100:POOL32A:32::MSUBU_DSP
|
|
|
|
"msubu ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_dsp_msubu (SD_, AC, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,00000,5.RS,2.AC,10000001,111100:POOL32A:32::MTHI_DSP
|
|
|
|
"mthi r<RS>, ac<AC>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_dsp_mthi (SD_, AC, RS);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,00000,5.RS,2.AC,00001001,111100:POOL32A:32::MTHLIP
|
|
|
|
"mthlip r<RS>, ac<AC>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_mthlip (SD_, RS, AC);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,00000,5.RS,2.AC,11000001,111100:POOL32A:32::MTLO_DSP
|
|
|
|
"mtlo r<RS>, ac<AC>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_dsp_mtlo (SD_, AC, RS);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00000,101101:POOL32A:32::MUL.PH
|
|
|
|
"mul.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_op (SD_, RD, RS, RT, 2, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,10000,101101:POOL32A:32::MUL_S.PH
|
|
|
|
"mul_s.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_op (SD_, RD, RS, RT, 2, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00000,100101:POOL32A:32::MULEQ_S.W.PHL
|
|
|
|
"muleq_s.w.phl r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_muleq (SD_, RD, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00001,100101:POOL32A:32::MULEQ_S.W.PHR
|
|
|
|
"muleq_s.w.phr r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_muleq (SD_, RD, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00010,010101:POOL32A:32::MULEU_S.PH.QBL
|
|
|
|
"muleu_s.ph.qbl r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_muleu (SD_, RD, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00011,010101:POOL32A:32::MULEU_S.PH.QBR
|
|
|
|
"muleu_s.ph.qbr r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_muleu (SD_, RD, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00100,010101:POOL32A:32::MULQ_RS.PH
|
|
|
|
"mulq_rs.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_mulq (SD_, RD, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00110,010101:POOL32A:32::MULQ_RS.W
|
|
|
|
"mulq_rs.w r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_mulq (SD_, RD, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00101,010101:POOL32A:32::MULQ_S.PH
|
|
|
|
"mulq_s.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_mulq (SD_, RD, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00111,010101:POOL32A:32::MULQ_S.W
|
|
|
|
"mulq_s.w r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_mulq (SD_, RD, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,10110010,111100:POOL32A:32::MULSA.W.PH
|
|
|
|
"mulsa.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_w_mulsa (SD_, AC, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,11110010,111100:POOL32A:32::MULSAQ_S.W.PH
|
|
|
|
"mulsaq_s.w.ph ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_mulsaq_s_w_ph (SD_, AC, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,00110010,111100:POOL32A:32::MULT_DSP
|
|
|
|
"mult ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_dsp_mult (SD_, AC, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,2.AC,01110010,111100:POOL32A:32::MULTU_DSP
|
|
|
|
"multu ac<AC>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_dsp_multu (SD_, AC, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00110,101101:POOL32A:32::PACKRL.PH
|
|
|
|
"packrl.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_packrl (SD_, RD, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01000,101101:POOL32A:32::PICK.PH
|
|
|
|
"pick.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_pick (SD_, RD, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00111,101101:POOL32A:32::PICK.QB
|
|
|
|
"pick.qb r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_pick (SD_, RD, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0101000100,111100:POOL32A:32::PRECEQ.W.PHL
|
|
|
|
"preceq.w.phl r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_preceq (SD_, RT, RS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0110000100,111100:POOL32A:32::PRECEQ.W.PHR
|
|
|
|
"preceq.w.phr r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_preceq (SD_, RT, RS, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0111000100,111100:POOL32A:32::PRECEQU.PH.QBL
|
|
|
|
"precequ.ph.qbl r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_ph_precequ (SD_, RT, RS, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0111001100,111100:POOL32A:32::PRECEQU.PH.QBLA
|
|
|
|
"precequ.ph.qbla r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_ph_precequ (SD_, RT, RS, 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,1001000100,111100:POOL32A:32::PRECEQU.PH.QBR
|
|
|
|
"precequ.ph.qbr r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_ph_precequ (SD_, RT, RS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,1001001100,111100:POOL32A:32::PRECEQU.PH.QBRA
|
|
|
|
"precequ.ph.qbra r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_ph_precequ (SD_, RT, RS, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,1011000100,111100:POOL32A:32::PRECEU.PH.QBL
|
|
|
|
"preceu.ph.qbl r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_ph_preceu (SD_, RT, RS, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,1011001100,111100:POOL32A:32::PRECEU.PH.QBLA
|
|
|
|
"preceu.ph.qbla r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_ph_preceu (SD_, RT, RS, 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,1101000100,111100:POOL32A:32::PRECEU.PH.QBR
|
|
|
|
"preceu.ph.qbr r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_ph_preceu (SD_, RT, RS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,1101001100,111100:POOL32A:32::PRECEU.PH.QBRA
|
|
|
|
"preceu.ph.qbra r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_ph_preceu (SD_, RT, RS, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00001,101101:POOL32A:32::PRECR.QB.PH
|
|
|
|
"precr.qb.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_qb_precr (SD_, RD, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.SA,01111,001101:POOL32A:32::PRECR_SRA.PH.W
|
|
|
|
"precr_sra.ph.w r<RT>, r<RS>, <SA>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_precr_sra (SD_, RT, RS, SA, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.SA,11111,001101:POOL32A:32::PRECR_SRA_R.PH.W
|
|
|
|
"precr_sra_r.ph.w r<RT>, r<RS>, <SA>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_precr_sra (SD_, RT, RS, SA, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00011,101101:POOL32A:32::PRECRQ.PH.W
|
|
|
|
"precrq.ph.w r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_ph_precrq (SD_, RD, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00010,101101:POOL32A:32::PRECRQ.QB.PH
|
|
|
|
"precrq.qb.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_qb_precrq (SD_, RD, RS, RT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00101,101101:POOL32A:32::PRECRQU_S.QB.PH
|
|
|
|
"precrqu_s.qb.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_qb_precrq (SD_, RD, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00100,101101:POOL32A:32::PRECRQ_RS.PH.W
|
|
|
|
"precrq_rs.ph.w r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_ph_rs_precrq (SD_, RD, RS, RT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.SA,01001,010101:POOL32A:32::PREPEND
|
|
|
|
"prepend r<RT>, r<RS>, <SA>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_prepend (SD_, RT, RS, SA);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,1111000100,111100:POOL32A:32::RADDU.W.QB
|
|
|
|
"raddu.w.qb r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_w_raddu (SD_, RT, RS);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,7.CONTROL_MASK,00011001,111100:POOL32A:32::RDDSP
|
|
|
|
"rddsp r<RT>":CONTROL_MASK == 1111111111
|
|
|
|
"rddsp r<RT>, <CONTROL_MASK>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_rddsp (SD_, RT, CONTROL_MASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,10.IMMEDIATE,5.RD,00000,111101:POOL32A:32::REPL.PH
|
|
|
|
"repl.ph r<RD>, <IMMEDIATE>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_repl (SD_, RD, IMMEDIATE, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,8.IMMEDIATE,0010111,111100:POOL32A:32::REPL.QB
|
|
|
|
"repl.qb r<RT>, <IMMEDIATE>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_repl (SD_, RT, IMMEDIATE, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0000001100,111100:POOL32A:32::REPLV.PH
|
|
|
|
"replv.ph r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_repl (SD_, RT, RS, 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,0001001100,111100:POOL32A:32::REPLV.QB
|
|
|
|
"replv.qb r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_repl (SD_, RT, RS, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,0000,6.IMMEDIATE,2.AC,00000000,011101:POOL32A:32::SHILO
|
|
|
|
"shilo ac<AC>, <IMMEDIATE>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_shilo (SD_, AC, IMMEDIATE);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,00000,5.RS,2.AC,01001001,111100:POOL32A:32::SHILOV
|
|
|
|
"shilov ac<AC>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_shilov (SD_, AC, RS);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,4.SHIFT,001110,110101:POOL32A:32::SHLL.PH
|
|
|
|
"shll.ph r<RT>, r<RS>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_shift (SD_, RT, RS, SHIFT, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,4.SHIFT,101110,110101:POOL32A:32::SHLL_S.PH
|
|
|
|
"shll_s.ph r<RT>, r<RS>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_shift (SD_, RT, RS, SHIFT, 0, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,3.SHIFT,0100001,111100:POOL32A:32::SHLL.QB
|
|
|
|
"shll.qb r<RT>, r<RS>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_shift (SD_, RT, RS, SHIFT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01110,001101:POOL32A:32::SHLLV.PH
|
|
|
|
"shllv.ph r<RD>, r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_shl (SD_, RD, RT, RS, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,11110,001101:POOL32A:32::SHLLV_S.PH
|
|
|
|
"shllv_s.ph r<RD>, r<RD>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_shl (SD_, RD, RT, RS, 0, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01110,010101:POOL32A:32::SHLLV.QB
|
|
|
|
"shllv.qb r<RD>, r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_shl (SD_, RD, RT, RS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01111,010101:POOL32A:32::SHLLV_S.W
|
|
|
|
"shllv_s.w r<RD>, r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_s_shllv (SD_, RD, RT, RS);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.SHIFT,01111,110101:POOL32A:32::SHLL_S.W
|
|
|
|
"shll_s.w r<RT>, r<RS>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_shll (SD_, RT, RS, SHIFT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,3.SHIFT,0000111,111100:POOL32A:32::SHRA.QB
|
|
|
|
"shra.qb r<RT>, r<RS>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_shra (SD_, RT, RS, SHIFT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,3.SHIFT,1000111,111100:POOL32A:32::SHRA_R.QB
|
|
|
|
"shra_r.qb r<RT>, r<RS>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_shra (SD_, RT, RS, SHIFT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,4.SHIFT,001100,110101:POOL32A:32::SHRA.PH
|
|
|
|
"shra.ph r<RT>, r<RS>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_shift (SD_, RT, RS, SHIFT, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,4.SHIFT,011100,110101:POOL32A:32::SHRA_R.PH
|
|
|
|
"shra_r.ph r<RT>, r<RS>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_shift (SD_, RT, RS, SHIFT, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00110,001101:POOL32A:32::SHRAV.PH
|
|
|
|
"shrav.ph r<RD>, r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_shl (SD_, RD, RT, RS, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,10110,001101:POOL32A:32::SHRAV_R.PH
|
|
|
|
"shrav_r.ph r<RD>, r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_shl (SD_, RD, RT, RS, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,00111,001101:POOL32A:32::SHRAV.QB
|
|
|
|
"shrav.qb r<RD>, r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_shrav (SD_, RD, RT, RS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,10111,001101:POOL32A:32::SHRAV_R.QB
|
|
|
|
"shrav_r.qb r<RD>, r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_shrav (SD_, RD, RT, RS, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01011,010101:POOL32A:32::SHRAV_R.W
|
|
|
|
"shrav_r.w r<RD>, r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_r_shrav (SD_, RD, RT, RS);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.SHIFT,01011,110101:POOL32A:32::SHRA_R.W
|
|
|
|
"shra_r.w r<RT>, r<RS>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_shra (SD_, RT, RS, SHIFT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,4.SHIFT,001111,111100:POOL32A:32::SHRL.PH
|
|
|
|
"shrl.ph r<RT>, r<RS>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_shrl (SD_, RT, RS, SHIFT);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,3.SHIFT,1100001,111100:POOL32A:32::SHRL.QB
|
|
|
|
"shrl.qb r<RT>, r<RS>, <SHIFT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_shift (SD_, RT, RS, SHIFT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01100,010101:POOL32A:32::SHRLV.PH
|
|
|
|
"shrlv.ph r<RD>, r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_shrlv (SD_, RD, RT, RS);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01101,010101:POOL32A:32::SHRLV.QB
|
|
|
|
"shrlv.qb r<RD>, r<RT>, r<RS>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_shl (SD_, RD, RT, RS, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01000,001101:POOL32A:32::SUBQ.PH
|
|
|
|
"subq.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_op (SD_, RD, RS, RT, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,11000,001101:POOL32A:32::SUBQ_S.PH
|
|
|
|
"subq_s.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_ph_op (SD_, RD, RS, RT, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01101,000101:POOL32A:32::SUBQ_S.W
|
|
|
|
"subq_s.w r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_w_op (SD_, RD, RS, RT, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01001,001101:POOL32A:32::SUBQH.PH
|
|
|
|
"subqh.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qh_ph_op (SD_, RD, RS, RT, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,11001,001101:POOL32A:32::SUBQH_R.PH
|
|
|
|
"subqh_r.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qh_ph_op (SD_, RD, RS, RT, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01010,001101:POOL32A:32::SUBQH.W
|
|
|
|
"subqh.w r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qh_w_op (SD_, RD, RS, RT, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,11010,001101:POOL32A:32::SUBQH_R.W
|
|
|
|
"subqh_r.w r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qh_w_op (SD_, RD, RS, RT, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01100,001101:POOL32A:32::SUBU.PH
|
|
|
|
"subu.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_u_ph_op (SD_, RD, RS, RT, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,11100,001101:POOL32A:32::SUBU_S.PH
|
|
|
|
"subu_s.ph r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_u_ph_op (SD_, RD, RS, RT, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01011,001101:POOL32A:32::SUBU.QB
|
|
|
|
"subu.qb r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_op (SD_, RD, RS, RT, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,11011,001101:POOL32A:32::SUBU_S.QB
|
|
|
|
"subu_s.qb r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_qb_op (SD_, RD, RS, RT, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,01101,001101:POOL32A:32::SUBUH.QB
|
|
|
|
"subuh.qb r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_uh_qb_op (SD_, RD, RS, RT, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,5.RS,5.RD,11101,001101:POOL32A:32::SUBUH_R.QB
|
|
|
|
"subuh_r.qb r<RD>, r<RS>, r<RT>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_uh_qb_op (SD_, RD, RS, RT, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
000000,5.RT,7.CONTROL_MASK,01011001,111100:POOL32A:32::WRDSP
|
|
|
|
"wrdsp r<RT>":CONTROL_MASK == 1111111111
|
|
|
|
"wrdsp r<RT>, <CONTROL_MASK>"
|
|
|
|
*micromipsdsp:
|
|
|
|
{
|
|
|
|
do_wrdsp (SD_, RT, CONTROL_MASK);
|
|
|
|
}
|