1999-04-16 03:35:26 +02:00
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/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include <stdlib.h>
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#define FALSE 0
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#define TRUE 1
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#define LOW 0
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#define HIGH 1
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#define LOWHIGH 1
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#define HIGHLOW 2
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#ifndef __STDC__
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2000-02-05 08:30:26 +01:00
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typedef char *VoidStar;
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1999-04-16 03:35:26 +02:00
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#endif
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2000-02-05 08:30:26 +01:00
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typedef unsigned long ARMword; /* must be 32 bits wide */
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typedef unsigned long long ARMdword; /* Must be at least 64 bits wide. */
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typedef struct ARMul_State ARMul_State;
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typedef unsigned ARMul_CPInits (ARMul_State * state);
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typedef unsigned ARMul_CPExits (ARMul_State * state);
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typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
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ARMword instr, ARMword value);
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typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
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ARMword instr, ARMword * value);
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typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
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ARMword instr, ARMword * value);
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typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
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ARMword instr, ARMword value);
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typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
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ARMword instr);
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typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
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ARMword * value);
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typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
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ARMword value);
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struct ARMul_State
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{
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ARMword Emulate; /* to start and stop emulation */
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unsigned EndCondition; /* reason for stopping */
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unsigned ErrorCode; /* type of illegal instruction */
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ARMword Reg[16]; /* the current register file */
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ARMword RegBank[7][16]; /* all the registers */
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/* 40 bit accumulator. We always keep this 64 bits wide,
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and move only 40 bits out of it in an MRA insn. */
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ARMdword Accumulator;
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ARMword Cpsr; /* the current psr */
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ARMword Spsr[7]; /* the exception psr's */
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ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
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ARMword SFlag;
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#ifdef MODET
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ARMword TFlag; /* Thumb state */
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#endif
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ARMword Bank; /* the current register bank */
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ARMword Mode; /* the current mode */
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ARMword instr, pc, temp; /* saved register state */
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ARMword loaded, decoded; /* saved pipeline state */
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unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
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unsigned long NumInstrs; /* the number of instructions executed */
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unsigned NextInstr;
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unsigned VectorCatch; /* caught exception mask */
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unsigned CallDebug; /* set to call the debugger */
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unsigned CanWatch; /* set by memory interface if its willing to suffer the
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overhead of checking for watchpoints on each memory
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access */
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unsigned MemReadDebug, MemWriteDebug;
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unsigned long StopHandle;
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unsigned char *MemDataPtr; /* admin data */
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unsigned char *MemInPtr; /* the Data In bus */
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unsigned char *MemOutPtr; /* the Data Out bus (which you may not need */
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unsigned char *MemSparePtr; /* extra space */
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ARMword MemSize;
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unsigned char *OSptr; /* OS Handle */
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char *CommandLine; /* Command Line from ARMsd */
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ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
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ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
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ARMul_LDCs *LDC[16]; /* LDC instruction */
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ARMul_STCs *STC[16]; /* STC instruction */
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ARMul_MRCs *MRC[16]; /* MRC instruction */
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ARMul_MCRs *MCR[16]; /* MCR instruction */
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ARMul_CDPs *CDP[16]; /* CDP instruction */
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ARMul_CPReads *CPRead[16]; /* Read CP register */
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ARMul_CPWrites *CPWrite[16]; /* Write CP register */
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unsigned char *CPData[16]; /* Coprocessor data */
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unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
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* XScale coprocessor support.
2001-04-18 matthew green <mrg@redhat.com>
* armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
(read_cp15_reg): Make non-static.
(XScale_cp15_LDC): Update for write_cp15_reg() change.
(XScale_cp15_MCR): Likewise.
(XScale_cp15_write_reg): Likewise.
(XScale_check_memacc): New function. Check for breakpoints being
activated by memory accesses. Does not support the Branch Target
Buffer.
(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
(XScale_debug_moe): New function. Set the debug Method Of Entry,
if configured.
(write_cp14_reg): Reset count counter if requested.
* armdefs.h (struct ARMul_State): New members `LastTime' and
`CP14R0_CCD' used for the timer/counters.
(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
defines for XScale registers.
(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
(ARMul_Emulate32): Handle the clock counter and hardware instruction
breakpoints. Call XScale_set_fsr_far() for software breakpoints and
software interrupts.
(LoadMult): Call XScale_set_fsr_far() for data aborts.
(LoadSMult): Likewise.
(StoreMult): Likewise.
(StoreSMult): Likewise.
* armemu.h (write_cp15_reg): Update prototype.
* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
register 0.
* armvirt.c (GetWord): Call XScale_check_memacc().
(PutWord): Likewise.
2001-04-18 18:39:37 +02:00
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unsigned long LastTime; /* Value of last call to ARMul_Time() */
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ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit
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3 set */
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unsigned EventSet; /* the number of events in the queue */
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unsigned long Now; /* time to the nearest cycle */
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struct EventNode **EventPtr; /* the event list */
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unsigned Exception; /* enable the next four values */
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unsigned Debug; /* show instructions as they are executed */
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unsigned NresetSig; /* reset the processor */
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unsigned NfiqSig;
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unsigned NirqSig;
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unsigned abortSig;
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unsigned NtransSig;
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unsigned bigendSig;
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unsigned prog32Sig;
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unsigned data32Sig;
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unsigned lateabtSig;
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ARMword Vector; /* synthesize aborts in cycle modes */
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ARMword Aborted; /* sticky flag for aborts */
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ARMword Reseted; /* sticky flag for Reset */
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ARMword Inted, LastInted; /* sticky flags for interrupts */
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ARMword Base; /* extra hand for base writeback */
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ARMword AbortAddr; /* to keep track of Prefetch aborts */
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const struct Dbg_HostosInterface *hostif;
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2000-09-16 01:55:50 +02:00
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unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
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unsigned is_v5; /* Are we emulating a v5 architecture ? */
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unsigned is_v5e; /* Are we emulating a v5e architecture ? */
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unsigned is_XScale; /* Are we emulating an XScale architecture ? */
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unsigned verbose; /* Print various messages like the banner */
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};
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#define ResetPin NresetSig
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#define FIQPin NfiqSig
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#define IRQPin NirqSig
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#define AbortPin abortSig
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#define TransPin NtransSig
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#define BigEndPin bigendSig
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#define Prog32Pin prog32Sig
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#define Data32Pin data32Sig
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#define LateAbortPin lateabtSig
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/***************************************************************************\
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* Properties of ARM we know about *
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\***************************************************************************/
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1999-04-16 03:35:26 +02:00
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/* The bitflags */
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#define ARM_Fix26_Prop 0x01
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#define ARM_Nexec_Prop 0x02
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#define ARM_Debug_Prop 0x10
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#define ARM_Isync_Prop ARM_Debug_Prop
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#define ARM_Lock_Prop 0x20
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#define ARM_v4_Prop 0x40
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#define ARM_v5_Prop 0x80
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#define ARM_v5e_Prop 0x100
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#define ARM_XScale_Prop 0x200
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1999-04-16 03:35:26 +02:00
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/***************************************************************************\
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* Macros to extract instruction fields *
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\***************************************************************************/
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2000-02-05 08:30:26 +01:00
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#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
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#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
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#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
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1999-04-16 03:35:26 +02:00
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/***************************************************************************\
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* The hardware vector addresses *
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\***************************************************************************/
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#define ARMResetV 0L
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#define ARMUndefinedInstrV 4L
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#define ARMSWIV 8L
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#define ARMPrefetchAbortV 12L
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#define ARMDataAbortV 16L
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#define ARMAddrExceptnV 20L
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#define ARMIRQV 24L
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#define ARMFIQV 28L
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#define ARMErrorV 32L /* This is an offset, not an address ! */
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#define ARMul_ResetV ARMResetV
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#define ARMul_UndefinedInstrV ARMUndefinedInstrV
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#define ARMul_SWIV ARMSWIV
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#define ARMul_PrefetchAbortV ARMPrefetchAbortV
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#define ARMul_DataAbortV ARMDataAbortV
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#define ARMul_AddrExceptnV ARMAddrExceptnV
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#define ARMul_IRQV ARMIRQV
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#define ARMul_FIQV ARMFIQV
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/***************************************************************************\
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* Mode and Bank Constants *
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\***************************************************************************/
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2000-05-30 19:13:37 +02:00
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#define USER26MODE 0L
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#define FIQ26MODE 1L
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#define IRQ26MODE 2L
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#define SVC26MODE 3L
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#define USER32MODE 16L
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#define FIQ32MODE 17L
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#define IRQ32MODE 18L
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#define SVC32MODE 19L
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#define ABORT32MODE 23L
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#define UNDEF32MODE 27L
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#define SYSTEMMODE 31L
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1999-04-16 03:35:26 +02:00
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#define ARM32BITMODE (state->Mode > 3)
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#define ARM26BITMODE (state->Mode <= 3)
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#define ARMMODE (state->Mode)
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#define ARMul_MODEBITS 0x1fL
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#define ARMul_MODE32BIT ARM32BITMODE
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#define ARMul_MODE26BIT ARM26BITMODE
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#define USERBANK 0
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#define FIQBANK 1
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#define IRQBANK 2
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#define SVCBANK 3
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#define ABORTBANK 4
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#define UNDEFBANK 5
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#define DUMMYBANK 6
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2000-07-04 07:16:20 +02:00
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#define SYSTEMBANK USERBANK
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2000-05-30 19:13:37 +02:00
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#define BANK_CAN_ACCESS_SPSR(bank) \
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((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
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1999-04-16 03:35:26 +02:00
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/***************************************************************************\
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* Definitons of things in the emulator *
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\***************************************************************************/
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2000-02-05 08:30:26 +01:00
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extern void ARMul_EmulateInit (void);
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extern ARMul_State *ARMul_NewState (void);
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extern void ARMul_Reset (ARMul_State * state);
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extern ARMword ARMul_DoProg (ARMul_State * state);
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extern ARMword ARMul_DoInstr (ARMul_State * state);
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1999-04-16 03:35:26 +02:00
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/***************************************************************************\
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* Definitons of things for event handling *
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\***************************************************************************/
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2000-02-05 08:30:26 +01:00
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extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
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unsigned (*func) ());
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extern void ARMul_EnvokeEvent (ARMul_State * state);
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extern unsigned long ARMul_Time (ARMul_State * state);
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1999-04-16 03:35:26 +02:00
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/***************************************************************************\
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* Useful support routines *
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\***************************************************************************/
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2000-02-05 08:30:26 +01:00
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extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
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unsigned reg);
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extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
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ARMword value);
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extern ARMword ARMul_GetPC (ARMul_State * state);
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extern ARMword ARMul_GetNextPC (ARMul_State * state);
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extern void ARMul_SetPC (ARMul_State * state, ARMword value);
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extern ARMword ARMul_GetR15 (ARMul_State * state);
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extern void ARMul_SetR15 (ARMul_State * state, ARMword value);
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extern ARMword ARMul_GetCPSR (ARMul_State * state);
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extern void ARMul_SetCPSR (ARMul_State * state, ARMword value);
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extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
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extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
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1999-04-16 03:35:26 +02:00
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/***************************************************************************\
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* Definitons of things to handle aborts *
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\***************************************************************************/
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2000-02-05 08:30:26 +01:00
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extern void ARMul_Abort (ARMul_State * state, ARMword address);
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#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
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1999-04-16 03:35:26 +02:00
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#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
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state->AbortAddr = (address & ~3L)
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#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
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state->Aborted = ARMul_DataAbortV ;
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#define ARMul_CLEARABORT state->abortSig = LOW
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/***************************************************************************\
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* Definitons of things in the memory interface *
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\***************************************************************************/
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2000-02-05 08:30:26 +01:00
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extern unsigned ARMul_MemoryInit (ARMul_State * state,
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unsigned long initmemsize);
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extern void ARMul_MemoryExit (ARMul_State * state);
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extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
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ARMword isize);
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extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
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ARMword isize);
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extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
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ARMword isize);
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extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
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extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
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extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
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extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
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extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
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ARMword data);
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extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
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ARMword data);
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extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
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ARMword data);
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extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
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ARMword data);
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extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
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ARMword data);
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extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
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ARMword data);
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extern void ARMul_Icycles (ARMul_State * state, unsigned number,
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ARMword address);
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extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
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ARMword address);
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extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
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extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
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2001-02-28 02:04:24 +01:00
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extern ARMword ARMul_SafeReadByte (ARMul_State * state, ARMword address);
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2000-02-05 08:30:26 +01:00
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extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
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ARMword data);
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extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
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ARMword data);
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2001-02-28 02:04:24 +01:00
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extern void ARMul_SafeWriteByte (ARMul_State * state, ARMword address,
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ARMword data);
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2000-02-05 08:30:26 +01:00
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extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
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ARMword, ARMword, ARMword, ARMword, ARMword,
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ARMword, ARMword, ARMword);
|
1999-04-16 03:35:26 +02:00
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/***************************************************************************\
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* Definitons of things in the co-processor interface *
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\***************************************************************************/
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#define ARMul_FIRST 0
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#define ARMul_TRANSFER 1
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#define ARMul_BUSY 2
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#define ARMul_DATA 3
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#define ARMul_INTERRUPT 4
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#define ARMul_DONE 0
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#define ARMul_CANT 1
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#define ARMul_INC 3
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|
* XScale coprocessor support.
2001-04-18 matthew green <mrg@redhat.com>
* armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
(read_cp15_reg): Make non-static.
(XScale_cp15_LDC): Update for write_cp15_reg() change.
(XScale_cp15_MCR): Likewise.
(XScale_cp15_write_reg): Likewise.
(XScale_check_memacc): New function. Check for breakpoints being
activated by memory accesses. Does not support the Branch Target
Buffer.
(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
(XScale_debug_moe): New function. Set the debug Method Of Entry,
if configured.
(write_cp14_reg): Reset count counter if requested.
* armdefs.h (struct ARMul_State): New members `LastTime' and
`CP14R0_CCD' used for the timer/counters.
(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
defines for XScale registers.
(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
(ARMul_Emulate32): Handle the clock counter and hardware instruction
breakpoints. Call XScale_set_fsr_far() for software breakpoints and
software interrupts.
(LoadMult): Call XScale_set_fsr_far() for data aborts.
(LoadSMult): Likewise.
(StoreMult): Likewise.
(StoreSMult): Likewise.
* armemu.h (write_cp15_reg): Update prototype.
* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
register 0.
* armvirt.c (GetWord): Call XScale_check_memacc().
(PutWord): Likewise.
2001-04-18 18:39:37 +02:00
|
|
|
#define ARMul_CP13_R0_FIQ 0x1
|
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|
|
#define ARMul_CP13_R0_IRQ 0x2
|
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|
|
#define ARMul_CP13_R8_PMUS 0x1
|
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|
|
#define ARMul_CP14_R0_ENABLE 0x0001
|
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|
#define ARMul_CP14_R0_CLKRST 0x0004
|
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|
#define ARMul_CP14_R0_CCD 0x0008
|
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|
|
#define ARMul_CP14_R0_INTEN0 0x0010
|
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|
|
|
#define ARMul_CP14_R0_INTEN1 0x0020
|
|
|
|
|
#define ARMul_CP14_R0_INTEN2 0x0040
|
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|
|
#define ARMul_CP14_R0_FLAG0 0x0100
|
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|
|
|
#define ARMul_CP14_R0_FLAG1 0x0200
|
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|
|
#define ARMul_CP14_R0_FLAG2 0x0400
|
|
|
|
|
#define ARMul_CP14_R10_MOE_IB 0x0004
|
|
|
|
|
#define ARMul_CP14_R10_MOE_DB 0x0008
|
|
|
|
|
#define ARMul_CP14_R10_MOE_BT 0x000c
|
|
|
|
|
#define ARMul_CP15_R1_ENDIAN 0x0080
|
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|
|
|
#define ARMul_CP15_R1_ALIGN 0x0002
|
|
|
|
|
#define ARMul_CP15_R5_X 0x0400
|
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|
|
|
#define ARMul_CP15_R5_ST_ALIGN 0x0001
|
|
|
|
|
#define ARMul_CP15_R5_IMPRE 0x0406
|
|
|
|
|
#define ARMul_CP15_R5_MMU_EXCPT 0x0400
|
|
|
|
|
#define ARMul_CP15_DBCON_M 0x0100
|
|
|
|
|
#define ARMul_CP15_DBCON_E1 0x000c
|
|
|
|
|
#define ARMul_CP15_DBCON_E0 0x0003
|
|
|
|
|
|
2000-02-05 08:30:26 +01:00
|
|
|
extern unsigned ARMul_CoProInit (ARMul_State * state);
|
|
|
|
|
extern void ARMul_CoProExit (ARMul_State * state);
|
|
|
|
|
extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
|
|
|
|
|
ARMul_CPInits * init, ARMul_CPExits * exit,
|
|
|
|
|
ARMul_LDCs * ldc, ARMul_STCs * stc,
|
|
|
|
|
ARMul_MRCs * mrc, ARMul_MCRs * mcr,
|
|
|
|
|
ARMul_CDPs * cdp,
|
|
|
|
|
ARMul_CPReads * read, ARMul_CPWrites * write);
|
|
|
|
|
extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
|
* XScale coprocessor support.
2001-04-18 matthew green <mrg@redhat.com>
* armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
(read_cp15_reg): Make non-static.
(XScale_cp15_LDC): Update for write_cp15_reg() change.
(XScale_cp15_MCR): Likewise.
(XScale_cp15_write_reg): Likewise.
(XScale_check_memacc): New function. Check for breakpoints being
activated by memory accesses. Does not support the Branch Target
Buffer.
(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
(XScale_debug_moe): New function. Set the debug Method Of Entry,
if configured.
(write_cp14_reg): Reset count counter if requested.
* armdefs.h (struct ARMul_State): New members `LastTime' and
`CP14R0_CCD' used for the timer/counters.
(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
defines for XScale registers.
(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
(ARMul_Emulate32): Handle the clock counter and hardware instruction
breakpoints. Call XScale_set_fsr_far() for software breakpoints and
software interrupts.
(LoadMult): Call XScale_set_fsr_far() for data aborts.
(LoadSMult): Likewise.
(StoreMult): Likewise.
(StoreSMult): Likewise.
* armemu.h (write_cp15_reg): Update prototype.
* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
register 0.
* armvirt.c (GetWord): Call XScale_check_memacc().
(PutWord): Likewise.
2001-04-18 18:39:37 +02:00
|
|
|
extern void XScale_check_memacc (ARMul_State * state, ARMword * address,
|
|
|
|
|
int store);
|
|
|
|
|
extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far);
|
|
|
|
|
extern int XScale_debug_moe (ARMul_State * state, int moe);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
|
* Definitons of things in the host environment *
|
|
|
|
|
\***************************************************************************/
|
|
|
|
|
|
2000-02-05 08:30:26 +01:00
|
|
|
extern unsigned ARMul_OSInit (ARMul_State * state);
|
|
|
|
|
extern void ARMul_OSExit (ARMul_State * state);
|
|
|
|
|
extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
|
|
|
|
|
extern ARMword ARMul_OSLastErrorP (ARMul_State * state);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
2000-02-05 08:30:26 +01:00
|
|
|
extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
|
|
|
|
|
extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
|
|
|
|
|
ARMword pc);
|
|
|
|
|
extern int rdi_log;
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
|
* Host-dependent stuff *
|
|
|
|
|
\***************************************************************************/
|
|
|
|
|
|
|
|
|
|
#ifdef macintosh
|
2000-02-05 08:30:26 +01:00
|
|
|
pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
|
1999-04-16 03:35:26 +02:00
|
|
|
# define HOURGLASS SpinCursor( 1 )
|
2000-02-05 08:30:26 +01:00
|
|
|
# define HOURGLASS_RATE 1023 /* 2^n - 1 */
|
1999-04-16 03:35:26 +02:00
|
|
|
#endif
|
2000-02-08 21:54:27 +01:00
|
|
|
|
|
|
|
|
extern void ARMul_UndefInstr (ARMul_State *, ARMword);
|
|
|
|
|
extern void ARMul_FixCPSR (ARMul_State *, ARMword, ARMword);
|
|
|
|
|
extern void ARMul_FixSPSR (ARMul_State *, ARMword, ARMword);
|
|
|
|
|
extern void ARMul_ConsolePrint (ARMul_State *, const char *, ...);
|
|
|
|
|
extern void ARMul_SelectProcessor (ARMul_State *, unsigned);
|