2007-06-28 16:29:56 +02:00
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/* This file is automatically generated by i386-gen. Do not edit! */
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2007-07-05 11:49:03 +02:00
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/* Copyright 2007 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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2007-06-28 16:29:56 +02:00
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/* i386 opcode table. */
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const template i386_optab[] =
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{
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{ "mov", 2, 0xa0, None, Cpu64,
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D|W|No_sSuf|No_xSuf,
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{ Disp64,
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Acc } },
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{ "mov", 2, 0xa0, None, CpuNo64,
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D|W|No_sSuf|No_qSuf|No_xSuf,
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{ Disp16|Disp32,
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Acc } },
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{ "mov", 2, 0x88, None, 0,
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D|W|Modrm|No_sSuf|No_xSuf,
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{ Reg8|Reg16|Reg32|Reg64,
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Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
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{ "mov", 2, 0xb0, None, 0,
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W|ShortForm|No_sSuf|No_qSuf|No_xSuf,
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{ Imm8|Imm16|Imm32|Imm32S,
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Reg8|Reg16|Reg32 } },
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{ "mov", 2, 0xc6, 0x0, 0,
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W|Modrm|No_sSuf|No_xSuf,
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{ Imm8|Imm16|Imm32|Imm32S,
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Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
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{ "mov", 2, 0xb0, None, Cpu64,
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W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
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{ Imm64,
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Reg64 } },
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{ "mov", 2, 0x8c, None, 0,
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Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ SReg2,
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Reg16|Reg32|Reg64|RegMem } },
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{ "mov", 2, 0x8c, None, 0,
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Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ SReg2,
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BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
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{ "mov", 2, 0x8c, None, Cpu386,
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Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ SReg3,
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Reg16|Reg32|Reg64|RegMem } },
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{ "mov", 2, 0x8c, None, Cpu386,
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Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ SReg3,
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BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
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{ "mov", 2, 0x8e, None, 0,
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Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg16|Reg32|Reg64,
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SReg2 } },
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{ "mov", 2, 0x8e, None, 0,
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Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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SReg2 } },
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{ "mov", 2, 0x8e, None, Cpu386,
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Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg16|Reg32|Reg64,
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SReg3 } },
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{ "mov", 2, 0x8e, None, Cpu386,
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Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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SReg3 } },
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{ "mov", 2, 0xf20, None, Cpu386|CpuNo64,
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D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Control,
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Reg32|RegMem } },
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{ "mov", 2, 0xf20, None, Cpu64,
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D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
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{ Control,
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Reg64|RegMem } },
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{ "mov", 2, 0xf21, None, Cpu386|CpuNo64,
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D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Debug,
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Reg32|RegMem } },
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{ "mov", 2, 0xf21, None, Cpu64,
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D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
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{ Debug,
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Reg64|RegMem } },
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{ "mov", 2, 0xf24, None, Cpu386|CpuNo64,
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D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Test,
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Reg32|RegMem } },
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{ "movabs", 2, 0xa0, None, Cpu64,
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D|W|No_sSuf|No_xSuf,
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{ Disp64,
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Acc } },
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{ "movabs", 2, 0xb0, None, Cpu64,
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W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
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{ Imm64,
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Reg64 } },
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{ "movsbl", 2, 0xfbe, None, Cpu386,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg32 } },
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{ "movsbw", 2, 0xfbe, None, Cpu386,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg16 } },
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{ "movswl", 2, 0xfbf, None, Cpu386,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg32 } },
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{ "movsbq", 2, 0xfbe, None, Cpu64,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
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{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg64 } },
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{ "movswq", 2, 0xfbf, None, Cpu64,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
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{ Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg64 } },
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{ "movslq", 2, 0x63, None, Cpu64,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
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{ Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg64 } },
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{ "movsx", 2, 0xfbe, None, Cpu386,
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Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg16|Reg32|Reg64 } },
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{ "movsx", 2, 0xfbf, None, Cpu386,
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Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg32|Reg64 } },
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{ "movsx", 2, 0x63, None, Cpu64,
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Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
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{ Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg64 } },
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{ "movzb", 2, 0xfb6, None, Cpu386,
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Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg16|Reg32|Reg64 } },
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{ "movzbl", 2, 0xfb6, None, Cpu386,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg32 } },
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{ "movzbw", 2, 0xfb6, None, Cpu386,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg16 } },
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{ "movzwl", 2, 0xfb7, None, Cpu386,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg32 } },
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{ "movzbq", 2, 0xfb6, None, Cpu64,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
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{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg64 } },
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{ "movzwq", 2, 0xfb7, None, Cpu64,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
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{ Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg64 } },
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{ "movzx", 2, 0xfb6, None, Cpu386,
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Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg16|Reg32|Reg64 } },
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{ "movzx", 2, 0xfb7, None, Cpu386,
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Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg32|Reg64 } },
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{ "push", 1, 0x50, None, CpuNo64,
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ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg16|Reg32|Reg64 } },
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{ "push", 1, 0xff, 0x6, CpuNo64,
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Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
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{ "push", 1, 0x6a, None, Cpu186|CpuNo64,
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DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Imm8S } },
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{ "push", 1, 0x68, None, Cpu186|CpuNo64,
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DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Imm16|Imm32 } },
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{ "push", 1, 0x6, None, CpuNo64,
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ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ SReg2 } },
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{ "push", 1, 0xfa0, None, Cpu386|CpuNo64,
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ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ SReg3 } },
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{ "push", 1, 0x50, None, Cpu64,
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ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
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{ Reg16|Reg64 } },
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{ "push", 1, 0xff, 0x6, Cpu64,
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Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
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{ Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
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{ "push", 1, 0x6a, None, Cpu64,
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DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
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{ Imm8S } },
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{ "push", 1, 0x68, None, Cpu64,
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DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
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{ Imm16|Imm32S } },
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{ "push", 1, 0xfa0, None, Cpu64,
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ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
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{ SReg3 } },
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{ "pusha", 0, 0x60, None, Cpu186|CpuNo64,
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DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ 0 } },
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{ "pop", 1, 0x58, None, CpuNo64,
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ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg16|Reg32|Reg64 } },
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{ "pop", 1, 0x8f, 0x0, CpuNo64,
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Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
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{ "pop", 1, 0x7, None, CpuNo64,
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ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ SReg2 } },
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{ "pop", 1, 0xfa1, None, Cpu386|CpuNo64,
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ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
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{ SReg3 } },
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{ "pop", 1, 0x58, None, Cpu64,
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ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
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{ Reg16|Reg64 } },
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{ "pop", 1, 0x8f, 0x0, Cpu64,
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Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
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{ Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
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{ "pop", 1, 0xfa1, None, Cpu64,
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ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
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{ SReg3 } },
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{ "popa", 0, 0x61, None, Cpu186|CpuNo64,
|
|
|
|
|
DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xchg", 2, 0x90, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "xchg", 2, 0x90, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Acc,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "xchg", 2, 0x86, None, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "xchg", 2, 0x86, None, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "in", 2, 0xe4, None, 0,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "in", 2, 0xec, None, 0,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ InOutPortReg,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "in", 1, 0xe4, None, 0,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8 } },
|
|
|
|
|
{ "in", 1, 0xec, None, 0,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ InOutPortReg } },
|
|
|
|
|
{ "out", 2, 0xe6, None, 0,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Acc,
|
|
|
|
|
Imm8 } },
|
|
|
|
|
{ "out", 2, 0xee, None, 0,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Acc,
|
|
|
|
|
InOutPortReg } },
|
|
|
|
|
{ "out", 1, 0xe6, None, 0,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8 } },
|
|
|
|
|
{ "out", 1, 0xee, None, 0,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ InOutPortReg } },
|
|
|
|
|
{ "lea", 2, 0x8d, None, 0,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "lds", 2, 0xc5, None, CpuNo64,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "les", 2, 0xc4, None, CpuNo64,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "lfs", 2, 0xfb4, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "lgs", 2, 0xfb5, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "lss", 2, 0xfb2, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "clc", 0, 0xf8, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cld", 0, 0xfc, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cli", 0, 0xfa, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "clts", 0, 0xf06, None, Cpu286,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cmc", 0, 0xf5, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "lahf", 0, 0x9f, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "sahf", 0, 0x9e, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "pushf", 0, 0x9c, None, CpuNo64,
|
|
|
|
|
DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "pushf", 0, 0x9c, None, Cpu64,
|
|
|
|
|
DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "popf", 0, 0x9d, None, CpuNo64,
|
|
|
|
|
DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "popf", 0, 0x9d, None, Cpu64,
|
|
|
|
|
DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "stc", 0, 0xf9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "std", 0, 0xfd, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "sti", 0, 0xfb, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "add", 2, 0x0, None, 0,
|
|
|
|
|
D|W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "add", 2, 0x83, 0x0, 0,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8S,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "add", 2, 0x4, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "add", 2, 0x80, 0x0, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "inc", 1, 0x40, None, CpuNo64,
|
|
|
|
|
ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "inc", 1, 0xfe, 0x0, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sub", 2, 0x28, None, 0,
|
|
|
|
|
D|W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sub", 2, 0x83, 0x5, 0,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8S,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sub", 2, 0x2c, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "sub", 2, 0x80, 0x5, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "dec", 1, 0x48, None, CpuNo64,
|
|
|
|
|
ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "dec", 1, 0xfe, 0x1, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sbb", 2, 0x18, None, 0,
|
|
|
|
|
D|W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sbb", 2, 0x83, 0x3, 0,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8S,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sbb", 2, 0x1c, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "sbb", 2, 0x80, 0x3, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "cmp", 2, 0x38, None, 0,
|
|
|
|
|
D|W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "cmp", 2, 0x83, 0x7, 0,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8S,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "cmp", 2, 0x3c, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "cmp", 2, 0x80, 0x7, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "test", 2, 0x84, None, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "test", 2, 0x84, None, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "test", 2, 0xa8, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "test", 2, 0xf6, 0x0, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "and", 2, 0x20, None, 0,
|
|
|
|
|
D|W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "and", 2, 0x83, 0x4, 0,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8S,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "and", 2, 0x24, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "and", 2, 0x80, 0x4, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "or", 2, 0x8, None, 0,
|
|
|
|
|
D|W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "or", 2, 0x83, 0x1, 0,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8S,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "or", 2, 0xc, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "or", 2, 0x80, 0x1, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "xor", 2, 0x30, None, 0,
|
|
|
|
|
D|W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "xor", 2, 0x83, 0x6, 0,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8S,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "xor", 2, 0x34, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "xor", 2, 0x80, 0x6, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "clr", 1, 0x30, None, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf|RegKludge,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "adc", 2, 0x10, None, 0,
|
|
|
|
|
D|W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "adc", 2, 0x83, 0x2, 0,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8S,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "adc", 2, 0x14, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "adc", 2, 0x80, 0x2, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8|Imm16|Imm32|Imm32S,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "neg", 1, 0xf6, 0x3, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "not", 1, 0xf6, 0x2, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "aaa", 0, 0x37, None, CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "aas", 0, 0x3f, None, CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "daa", 0, 0x27, None, CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "das", 0, 0x2f, None, CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "aad", 0, 0xd50a, None, CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "aad", 1, 0xd5, None, CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8 } },
|
|
|
|
|
{ "aam", 0, 0xd40a, None, CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "aam", 1, 0xd4, None, CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8 } },
|
|
|
|
|
{ "cbw", 0, 0x98, None, 0,
|
|
|
|
|
Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cdqe", 0, 0x98, None, Cpu64,
|
|
|
|
|
Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cwde", 0, 0x98, None, 0,
|
|
|
|
|
Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cwd", 0, 0x99, None, 0,
|
|
|
|
|
Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cdq", 0, 0x99, None, 0,
|
|
|
|
|
Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cqo", 0, 0x99, None, Cpu64,
|
|
|
|
|
Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cbtw", 0, 0x98, None, 0,
|
|
|
|
|
Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cltq", 0, 0x98, None, Cpu64,
|
|
|
|
|
Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cwtl", 0, 0x98, None, 0,
|
|
|
|
|
Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cwtd", 0, 0x99, None, 0,
|
|
|
|
|
Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cltd", 0, 0x99, None, 0,
|
|
|
|
|
Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cqto", 0, 0x99, None, Cpu64,
|
|
|
|
|
Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "mul", 1, 0xf6, 0x4, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "imul", 1, 0xf6, 0x5, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "imul", 2, 0xfaf, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "imul", 3, 0x6b, None, Cpu186,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8S,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "imul", 3, 0x69, None, Cpu186,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm16|Imm32|Imm32S,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "imul", 2, 0x6b, None, Cpu186,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge,
|
|
|
|
|
{ Imm8S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "imul", 2, 0x69, None, Cpu186,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge,
|
|
|
|
|
{ Imm16|Imm32|Imm32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "div", 1, 0xf6, 0x6, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "div", 2, 0xf6, 0x6, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "idiv", 1, 0xf6, 0x7, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "idiv", 2, 0xf6, 0x7, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "rol", 2, 0xd0, 0x0, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm1,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rol", 2, 0xc0, 0x0, Cpu186,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rol", 2, 0xd2, 0x0, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ ShiftCount,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rol", 1, 0xd0, 0x0, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "ror", 2, 0xd0, 0x1, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm1,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "ror", 2, 0xc0, 0x1, Cpu186,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "ror", 2, 0xd2, 0x1, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ ShiftCount,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "ror", 1, 0xd0, 0x1, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rcl", 2, 0xd0, 0x2, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm1,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rcl", 2, 0xc0, 0x2, Cpu186,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rcl", 2, 0xd2, 0x2, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ ShiftCount,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rcl", 1, 0xd0, 0x2, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rcr", 2, 0xd0, 0x3, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm1,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rcr", 2, 0xc0, 0x3, Cpu186,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rcr", 2, 0xd2, 0x3, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ ShiftCount,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rcr", 1, 0xd0, 0x3, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sal", 2, 0xd0, 0x4, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm1,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sal", 2, 0xc0, 0x4, Cpu186,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sal", 2, 0xd2, 0x4, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ ShiftCount,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sal", 1, 0xd0, 0x4, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shl", 2, 0xd0, 0x4, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm1,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shl", 2, 0xc0, 0x4, Cpu186,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shl", 2, 0xd2, 0x4, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ ShiftCount,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shl", 1, 0xd0, 0x4, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shr", 2, 0xd0, 0x5, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm1,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shr", 2, 0xc0, 0x5, Cpu186,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shr", 2, 0xd2, 0x5, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ ShiftCount,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shr", 1, 0xd0, 0x5, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sar", 2, 0xd0, 0x7, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm1,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sar", 2, 0xc0, 0x7, Cpu186,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sar", 2, 0xd2, 0x7, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ ShiftCount,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sar", 1, 0xd0, 0x7, 0,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shld", 3, 0xfa4, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg16|Reg32|Reg64,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shld", 3, 0xfa5, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ ShiftCount,
|
|
|
|
|
Reg16|Reg32|Reg64,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shld", 2, 0xfa5, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shrd", 3, 0xfac, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg16|Reg32|Reg64,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shrd", 3, 0xfad, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ ShiftCount,
|
|
|
|
|
Reg16|Reg32|Reg64,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "shrd", 2, 0xfad, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "call", 1, 0xe8, None, CpuNo64,
|
|
|
|
|
JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp16|Disp32 } },
|
|
|
|
|
{ "call", 1, 0xe8, None, Cpu64,
|
|
|
|
|
JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Disp16|Disp32 } },
|
|
|
|
|
{ "call", 1, 0xff, 0x2, CpuNo64,
|
|
|
|
|
Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
|
|
|
|
|
{ "call", 1, 0xff, 0x2, Cpu64,
|
|
|
|
|
Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
|
|
|
|
|
{ "call", 2, 0x9a, None, CpuNo64,
|
|
|
|
|
JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm16,
|
|
|
|
|
Imm16|Imm32 } },
|
|
|
|
|
{ "call", 1, 0xff, 0x3, 0,
|
|
|
|
|
Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
|
|
|
|
|
{ "lcall", 2, 0x9a, None, CpuNo64,
|
|
|
|
|
JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm16,
|
|
|
|
|
Imm16|Imm32 } },
|
|
|
|
|
{ "lcall", 1, 0xff, 0x3, 0,
|
|
|
|
|
Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
|
|
|
|
|
{ "jmp", 1, 0xeb, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jmp", 1, 0xff, 0x4, CpuNo64,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
|
|
|
|
|
{ "jmp", 1, 0xff, 0x4, Cpu64,
|
|
|
|
|
Modrm|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
|
|
|
|
|
{ "jmp", 2, 0xea, None, CpuNo64,
|
|
|
|
|
JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm16,
|
|
|
|
|
Imm16|Imm32 } },
|
|
|
|
|
{ "jmp", 1, 0xff, 0x5, 0,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
|
|
|
|
|
{ "ljmp", 2, 0xea, None, CpuNo64,
|
|
|
|
|
JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm16,
|
|
|
|
|
Imm16|Imm32 } },
|
|
|
|
|
{ "ljmp", 1, 0xff, 0x5, 0,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
|
|
|
|
|
{ "ret", 0, 0xc3, None, CpuNo64,
|
|
|
|
|
DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ret", 1, 0xc2, None, CpuNo64,
|
|
|
|
|
DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm16 } },
|
|
|
|
|
{ "ret", 0, 0xc3, None, Cpu64,
|
|
|
|
|
DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ret", 1, 0xc2, None, Cpu64,
|
|
|
|
|
DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Imm16 } },
|
|
|
|
|
{ "lret", 0, 0xcb, None, 0,
|
|
|
|
|
DefaultSize|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "lret", 1, 0xca, None, 0,
|
|
|
|
|
DefaultSize|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm16 } },
|
|
|
|
|
{ "enter", 2, 0xc8, None, Cpu186|CpuNo64,
|
|
|
|
|
DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm16,
|
|
|
|
|
Imm8 } },
|
|
|
|
|
{ "enter", 2, 0xc8, None, Cpu64,
|
|
|
|
|
DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Imm16,
|
|
|
|
|
Imm8 } },
|
|
|
|
|
{ "leave", 0, 0xc9, None, Cpu186|CpuNo64,
|
|
|
|
|
DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "leave", 0, 0xc9, None, Cpu64,
|
|
|
|
|
DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "jo", 1, 0x70, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jno", 1, 0x71, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jb", 1, 0x72, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jc", 1, 0x72, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jnae", 1, 0x72, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jnb", 1, 0x73, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jnc", 1, 0x73, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jae", 1, 0x73, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "je", 1, 0x74, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jz", 1, 0x74, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jne", 1, 0x75, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jnz", 1, 0x75, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jbe", 1, 0x76, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jna", 1, 0x76, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jnbe", 1, 0x77, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "ja", 1, 0x77, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "js", 1, 0x78, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jns", 1, 0x79, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jp", 1, 0x7a, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jpe", 1, 0x7a, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jnp", 1, 0x7b, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jpo", 1, 0x7b, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jl", 1, 0x7c, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jnge", 1, 0x7c, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jnl", 1, 0x7d, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jge", 1, 0x7d, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jle", 1, 0x7e, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jng", 1, 0x7e, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jnle", 1, 0x7f, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jg", 1, 0x7f, None, 0,
|
|
|
|
|
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jcxz", 1, 0xe3, None, CpuNo64,
|
|
|
|
|
JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jecxz", 1, 0xe3, None, CpuNo64,
|
|
|
|
|
JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jecxz", 1, 0x67e3, None, Cpu64,
|
|
|
|
|
JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "jrcxz", 1, 0xe3, None, Cpu64,
|
|
|
|
|
JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "loop", 1, 0xe2, None, CpuNo64,
|
|
|
|
|
JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "loop", 1, 0xe2, None, Cpu64,
|
|
|
|
|
JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "loopz", 1, 0xe1, None, CpuNo64,
|
|
|
|
|
JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "loopz", 1, 0xe1, None, Cpu64,
|
|
|
|
|
JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "loope", 1, 0xe1, None, CpuNo64,
|
|
|
|
|
JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "loope", 1, 0xe1, None, Cpu64,
|
|
|
|
|
JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "loopnz", 1, 0xe0, None, CpuNo64,
|
|
|
|
|
JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "loopnz", 1, 0xe0, None, Cpu64,
|
|
|
|
|
JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "loopne", 1, 0xe0, None, CpuNo64,
|
|
|
|
|
JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "loopne", 1, 0xe0, None, Cpu64,
|
|
|
|
|
JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Disp8|Disp16|Disp32|Disp32S|Disp64 } },
|
|
|
|
|
{ "seto", 1, 0xf90, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setno", 1, 0xf91, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setb", 1, 0xf92, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setc", 1, 0xf92, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setnae", 1, 0xf92, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setnb", 1, 0xf93, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setnc", 1, 0xf93, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setae", 1, 0xf93, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sete", 1, 0xf94, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setz", 1, 0xf94, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setne", 1, 0xf95, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setnz", 1, 0xf95, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setbe", 1, 0xf96, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setna", 1, 0xf96, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setnbe", 1, 0xf97, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "seta", 1, 0xf97, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sets", 1, 0xf98, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setns", 1, 0xf99, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setp", 1, 0xf9a, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setpe", 1, 0xf9a, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setnp", 1, 0xf9b, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setpo", 1, 0xf9b, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setl", 1, 0xf9c, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setnge", 1, 0xf9c, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setnl", 1, 0xf9d, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setge", 1, 0xf9d, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setle", 1, 0xf9e, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setng", 1, 0xf9e, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setnle", 1, 0xf9f, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "setg", 1, 0xf9f, 0x0, Cpu386,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "cmps", 0, 0xa6, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cmps", 2, 0xa6, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "scmp", 0, 0xa6, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "scmp", 2, 0xa6, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "ins", 0, 0x6c, None, Cpu186,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ins", 2, 0x6c, None, Cpu186,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf|IsString,
|
|
|
|
|
{ InOutPortReg,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
|
|
|
|
|
{ "outs", 0, 0x6e, None, Cpu186,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "outs", 2, 0x6e, None, Cpu186,
|
|
|
|
|
W|No_sSuf|No_qSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
InOutPortReg } },
|
|
|
|
|
{ "lods", 0, 0xac, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "lods", 1, 0xac, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "lods", 2, 0xac, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "slod", 0, 0xac, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "slod", 1, 0xac, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "slod", 2, 0xac, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "movs", 0, 0xa4, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "movs", 2, 0xa4, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
|
|
|
|
|
{ "smov", 0, 0xa4, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "smov", 2, 0xa4, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
|
|
|
|
|
{ "scas", 0, 0xae, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "scas", 1, 0xae, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
|
|
|
|
|
{ "scas", 2, 0xae, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "ssca", 0, 0xae, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ssca", 1, 0xae, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
|
|
|
|
|
{ "ssca", 2, 0xae, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "stos", 0, 0xaa, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "stos", 1, 0xaa, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
|
|
|
|
|
{ "stos", 2, 0xaa, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ Acc,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
|
|
|
|
|
{ "ssto", 0, 0xaa, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ssto", 1, 0xaa, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
|
|
|
|
|
{ "ssto", 2, 0xaa, None, 0,
|
|
|
|
|
W|No_sSuf|No_xSuf|IsString,
|
|
|
|
|
{ Acc,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
|
|
|
|
|
{ "xlat", 0, 0xd7, None, 0,
|
|
|
|
|
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xlat", 1, 0xd7, None, 0,
|
|
|
|
|
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "bsf", 2, 0xfbc, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "bsr", 2, 0xfbd, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "bt", 2, 0xfa3, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "bt", 2, 0xfba, 0x4, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "btc", 2, 0xfbb, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "btc", 2, 0xfba, 0x7, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "btr", 2, 0xfb3, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "btr", 2, 0xfba, 0x6, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "bts", 2, 0xfab, None, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "bts", 2, 0xfba, 0x5, Cpu386,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "int", 1, 0xcd, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8 } },
|
|
|
|
|
{ "int3", 0, 0xcc, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "into", 0, 0xce, None, CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "iret", 0, 0xcf, None, 0,
|
|
|
|
|
DefaultSize|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rsm", 0, 0xfaa, None, Cpu386,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "bound", 2, 0x62, None, Cpu186|CpuNo64,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "hlt", 0, 0xf4, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "nop", 1, 0xf1f, 0x0, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "nop", 0, 0x90, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "arpl", 2, 0x63, None, Cpu286|CpuNo64,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16,
|
|
|
|
|
Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "lar", 2, 0xf02, None, Cpu286,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "lgdt", 1, 0xf01, 0x2, Cpu286|CpuNo64,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "lgdt", 1, 0xf01, 0x2, Cpu64,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "lidt", 1, 0xf01, 0x3, Cpu286|CpuNo64,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "lidt", 1, 0xf01, 0x3, Cpu64,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "lldt", 1, 0xf00, 0x2, Cpu286,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "lmsw", 1, 0xf01, 0x6, Cpu286,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "lsl", 2, 0xf03, None, Cpu286,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "ltr", 1, 0xf00, 0x3, Cpu286,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sgdt", 1, 0xf01, 0x0, Cpu286|CpuNo64,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sgdt", 1, 0xf01, 0x0, Cpu64,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sidt", 1, 0xf01, 0x1, Cpu286|CpuNo64,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sidt", 1, 0xf01, 0x1, Cpu64,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sldt", 1, 0xf00, 0x0, Cpu286,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "sldt", 1, 0xf00, 0x0, Cpu286,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "smsw", 1, 0xf01, 0x4, Cpu286,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "smsw", 1, 0xf01, 0x4, Cpu286,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "str", 1, 0xf00, 0x1, Cpu286,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "str", 1, 0xf00, 0x1, Cpu286,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "verr", 1, 0xf00, 0x4, Cpu286,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "verw", 1, 0xf00, 0x5, Cpu286,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fld", 1, 0xd9c0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fld", 1, 0xd9, 0x0, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fld", 1, 0xd9c0, None, 0,
|
|
|
|
|
ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fld", 1, 0xdb, 0x5, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fild", 1, 0xdf, 0x0, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fild", 1, 0xdf, 0x5, 0,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fildll", 1, 0xdf, 0x5, 0,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fldt", 1, 0xdb, 0x5, 0,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fbld", 1, 0xdf, 0x4, 0,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fst", 1, 0xddd0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fst", 1, 0xd9, 0x2, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fst", 1, 0xddd0, None, 0,
|
|
|
|
|
ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fist", 1, 0xdf, 0x2, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fstp", 1, 0xddd8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fstp", 1, 0xd9, 0x3, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fstp", 1, 0xddd8, None, 0,
|
|
|
|
|
ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fstp", 1, 0xdb, 0x7, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fistp", 1, 0xdf, 0x3, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fistp", 1, 0xdf, 0x7, 0,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fistpll", 1, 0xdf, 0x7, 0,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fstpt", 1, 0xdb, 0x7, 0,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fbstp", 1, 0xdf, 0x6, 0,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fxch", 1, 0xd9c8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fxch", 0, 0xd9c9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fcom", 1, 0xd8d0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fcom", 0, 0xd8d1, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fcom", 1, 0xd8, 0x2, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fcom", 1, 0xd8d0, None, 0,
|
|
|
|
|
ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "ficom", 1, 0xde, 0x2, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fcomp", 1, 0xd8d8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fcomp", 0, 0xd8d9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fcomp", 1, 0xd8, 0x3, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fcomp", 1, 0xd8d8, None, 0,
|
|
|
|
|
ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "ficomp", 1, 0xde, 0x3, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fcompp", 0, 0xded9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fucom", 1, 0xdde0, None, Cpu286,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fucom", 0, 0xdde1, None, Cpu286,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fucomp", 1, 0xdde8, None, Cpu286,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fucomp", 0, 0xdde9, None, Cpu286,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fucompp", 0, 0xdae9, None, Cpu286,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ftst", 0, 0xd9e4, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fxam", 0, 0xd9e5, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fld1", 0, 0xd9e8, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fldl2t", 0, 0xd9e9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fldl2e", 0, 0xd9ea, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fldpi", 0, 0xd9eb, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fldlg2", 0, 0xd9ec, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fldln2", 0, 0xd9ed, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fldz", 0, 0xd9ee, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fadd", 2, 0xd8c0, None, 0,
|
|
|
|
|
ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fadd", 1, 0xd8c0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
#if SYSV386_COMPAT
|
|
|
|
|
{ "fadd", 0, 0xdec1, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#endif
|
|
|
|
|
{ "fadd", 1, 0xd8, 0x0, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fiadd", 1, 0xde, 0x0, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "faddp", 2, 0xdec0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatAcc,
|
|
|
|
|
FloatReg } },
|
|
|
|
|
{ "faddp", 1, 0xdec0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "faddp", 0, 0xdec1, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "faddp", 2, 0xdec0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fsub", 1, 0xd8e0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
#if SYSV386_COMPAT
|
|
|
|
|
{ "fsub", 2, 0xd8e0, None, 0,
|
|
|
|
|
ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fsub", 0, 0xdee1, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#else
|
|
|
|
|
{ "fsub", 2, 0xd8e0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
#endif
|
|
|
|
|
{ "fsub", 1, 0xd8, 0x4, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fisub", 1, 0xde, 0x4, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
#if SYSV386_COMPAT
|
|
|
|
|
{ "fsubp", 2, 0xdee0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatAcc,
|
|
|
|
|
FloatReg } },
|
|
|
|
|
{ "fsubp", 1, 0xdee0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fsubp", 0, 0xdee1, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#if OLDGCC_COMPAT
|
|
|
|
|
{ "fsubp", 2, 0xdee0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
#endif
|
|
|
|
|
#else
|
|
|
|
|
{ "fsubp", 2, 0xdee8, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
|
|
|
|
|
{ FloatAcc,
|
|
|
|
|
FloatReg } },
|
|
|
|
|
{ "fsubp", 1, 0xdee8, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fsubp", 0, 0xdee9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#endif
|
|
|
|
|
{ "fsubr", 1, 0xd8e8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
#if SYSV386_COMPAT
|
|
|
|
|
{ "fsubr", 2, 0xd8e8, None, 0,
|
|
|
|
|
ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fsubr", 0, 0xdee9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#else
|
|
|
|
|
{ "fsubr", 2, 0xd8e8, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
#endif
|
|
|
|
|
{ "fsubr", 1, 0xd8, 0x5, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fisubr", 1, 0xde, 0x5, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
#if SYSV386_COMPAT
|
|
|
|
|
{ "fsubrp", 2, 0xdee8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatAcc,
|
|
|
|
|
FloatReg } },
|
|
|
|
|
{ "fsubrp", 1, 0xdee8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fsubrp", 0, 0xdee9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#if OLDGCC_COMPAT
|
|
|
|
|
{ "fsubrp", 2, 0xdee8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
#endif
|
|
|
|
|
#else
|
|
|
|
|
{ "fsubrp", 2, 0xdee0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
|
|
|
|
|
{ FloatAcc,
|
|
|
|
|
FloatReg } },
|
|
|
|
|
{ "fsubrp", 1, 0xdee0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fsubrp", 0, 0xdee1, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#endif
|
|
|
|
|
{ "fmul", 2, 0xd8c8, None, 0,
|
|
|
|
|
ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fmul", 1, 0xd8c8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
#if SYSV386_COMPAT
|
|
|
|
|
{ "fmul", 0, 0xdec9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#endif
|
|
|
|
|
{ "fmul", 1, 0xd8, 0x1, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fimul", 1, 0xde, 0x1, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fmulp", 2, 0xdec8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatAcc,
|
|
|
|
|
FloatReg } },
|
|
|
|
|
{ "fmulp", 1, 0xdec8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fmulp", 0, 0xdec9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fmulp", 2, 0xdec8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fdiv", 1, 0xd8f0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
#if SYSV386_COMPAT
|
|
|
|
|
{ "fdiv", 2, 0xd8f0, None, 0,
|
|
|
|
|
ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fdiv", 0, 0xdef1, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#else
|
|
|
|
|
{ "fdiv", 2, 0xd8f0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
#endif
|
|
|
|
|
{ "fdiv", 1, 0xd8, 0x6, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fidiv", 1, 0xde, 0x6, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
#if SYSV386_COMPAT
|
|
|
|
|
{ "fdivp", 2, 0xdef0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatAcc,
|
|
|
|
|
FloatReg } },
|
|
|
|
|
{ "fdivp", 1, 0xdef0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fdivp", 0, 0xdef1, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#if OLDGCC_COMPAT
|
|
|
|
|
{ "fdivp", 2, 0xdef0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
#endif
|
|
|
|
|
#else
|
|
|
|
|
{ "fdivp", 2, 0xdef8, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
|
|
|
|
|
{ FloatAcc,
|
|
|
|
|
FloatReg } },
|
|
|
|
|
{ "fdivp", 1, 0xdef8, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fdivp", 0, 0xdef9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#endif
|
|
|
|
|
{ "fdivr", 1, 0xd8f8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
#if SYSV386_COMPAT
|
|
|
|
|
{ "fdivr", 2, 0xd8f8, None, 0,
|
|
|
|
|
ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fdivr", 0, 0xdef9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#else
|
|
|
|
|
{ "fdivr", 2, 0xd8f8, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
#endif
|
|
|
|
|
{ "fdivr", 1, 0xd8, 0x7, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fidivr", 1, 0xde, 0x7, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
#if SYSV386_COMPAT
|
|
|
|
|
{ "fdivrp", 2, 0xdef8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatAcc,
|
|
|
|
|
FloatReg } },
|
|
|
|
|
{ "fdivrp", 1, 0xdef8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fdivrp", 0, 0xdef9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#if OLDGCC_COMPAT
|
|
|
|
|
{ "fdivrp", 2, 0xdef8, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
#endif
|
|
|
|
|
#else
|
|
|
|
|
{ "fdivrp", 2, 0xdef0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
|
|
|
|
|
{ FloatAcc,
|
|
|
|
|
FloatReg } },
|
|
|
|
|
{ "fdivrp", 1, 0xdef0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fdivrp", 0, 0xdef1, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
#endif
|
|
|
|
|
{ "f2xm1", 0, 0xd9f0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fyl2x", 0, 0xd9f1, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fptan", 0, 0xd9f2, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fpatan", 0, 0xd9f3, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fxtract", 0, 0xd9f4, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fprem1", 0, 0xd9f5, None, Cpu286,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fdecstp", 0, 0xd9f6, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fincstp", 0, 0xd9f7, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fprem", 0, 0xd9f8, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fyl2xp1", 0, 0xd9f9, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fsqrt", 0, 0xd9fa, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fsincos", 0, 0xd9fb, None, Cpu286,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "frndint", 0, 0xd9fc, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fscale", 0, 0xd9fd, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fsin", 0, 0xd9fe, None, Cpu286,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fcos", 0, 0xd9ff, None, Cpu286,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fchs", 0, 0xd9e0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fabs", 0, 0xd9e1, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fninit", 0, 0xdbe3, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "finit", 0, 0xdbe3, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fldcw", 1, 0xd9, 0x5, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fnstcw", 1, 0xd9, 0x7, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fstcw", 1, 0xd9, 0x7, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fnstsw", 1, 0xdfe0, None, 0,
|
|
|
|
|
IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Acc } },
|
|
|
|
|
{ "fnstsw", 1, 0xdd, 0x7, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fnstsw", 0, 0xdfe0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fstsw", 1, 0xdfe0, None, 0,
|
|
|
|
|
IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
|
|
|
|
|
{ Acc } },
|
|
|
|
|
{ "fstsw", 1, 0xdd, 0x7, 0,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fstsw", 0, 0xdfe0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fnclex", 0, 0xdbe2, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fclex", 0, 0xdbe2, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fnstenv", 1, 0xd9, 0x6, 0,
|
|
|
|
|
Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fstenv", 1, 0xd9, 0x6, 0,
|
|
|
|
|
Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fldenv", 1, 0xd9, 0x4, 0,
|
|
|
|
|
Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fnsave", 1, 0xdd, 0x6, 0,
|
|
|
|
|
Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fsave", 1, 0xdd, 0x6, 0,
|
|
|
|
|
Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "frstor", 1, 0xdd, 0x4, 0,
|
|
|
|
|
Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "ffree", 1, 0xddc0, None, 0,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "ffreep", 1, 0xdfc0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fnop", 0, 0xd9d0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fwait", 0, 0x9b, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "addr16", 0, 0x67, None, Cpu386|CpuNo64,
|
|
|
|
|
Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "addr32", 0, 0x67, None, Cpu386,
|
|
|
|
|
Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "aword", 0, 0x67, None, Cpu386|CpuNo64,
|
|
|
|
|
Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "adword", 0, 0x67, None, Cpu386,
|
|
|
|
|
Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "data16", 0, 0x66, None, Cpu386,
|
|
|
|
|
Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "data32", 0, 0x66, None, Cpu386|CpuNo64,
|
|
|
|
|
Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "word", 0, 0x66, None, Cpu386,
|
|
|
|
|
Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "dword", 0, 0x66, None, Cpu386|CpuNo64,
|
|
|
|
|
Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "lock", 0, 0xf0, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "wait", 0, 0x9b, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cs", 0, 0x2e, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ds", 0, 0x3e, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "es", 0, 0x26, None, CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fs", 0, 0x64, None, Cpu386,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "gs", 0, 0x65, None, Cpu386,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ss", 0, 0x36, None, CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rep", 0, 0xf3, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "repe", 0, 0xf3, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "repz", 0, 0xf3, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "repne", 0, 0xf2, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "repnz", 0, 0xf2, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ht", 0, 0x3e, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "hnt", 0, 0x2e, None, 0,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex", 0, 0x40, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rexz", 0, 0x41, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rexy", 0, 0x42, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rexyz", 0, 0x43, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rexx", 0, 0x44, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rexxz", 0, 0x45, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rexxy", 0, 0x46, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rexxyz", 0, 0x47, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex64", 0, 0x48, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex64z", 0, 0x49, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex64y", 0, 0x4a, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex64yz", 0, 0x4b, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex64x", 0, 0x4c, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex64xz", 0, 0x4d, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex64xy", 0, 0x4e, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex64xyz", 0, 0x4f, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.b", 0, 0x41, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.x", 0, 0x42, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.xb", 0, 0x43, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.r", 0, 0x44, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.rb", 0, 0x45, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.rx", 0, 0x46, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.rxb", 0, 0x47, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.w", 0, 0x48, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.wb", 0, 0x49, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.wx", 0, 0x4a, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.wxb", 0, 0x4b, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.wr", 0, 0x4c, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.wrb", 0, 0x4d, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.wrx", 0, 0x4e, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rex.wrxb", 0, 0x4f, None, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "bswap", 1, 0xfc8, None, Cpu486,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg32|Reg64 } },
|
|
|
|
|
{ "xadd", 2, 0xfc0, None, Cpu486,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "cmpxchg", 2, 0xfb0, None, Cpu486,
|
|
|
|
|
W|Modrm|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg8|Reg16|Reg32|Reg64,
|
|
|
|
|
Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "invd", 0, 0xf08, None, Cpu486,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "wbinvd", 0, 0xf09, None, Cpu486,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "invlpg", 1, 0xf01, 0x7, Cpu486,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "cpuid", 0, 0xfa2, None, Cpu486,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "wrmsr", 0, 0xf30, None, Cpu586,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rdtsc", 0, 0xf31, None, Cpu586,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rdmsr", 0, 0xf32, None, Cpu586,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cmpxchg8b", 1, 0xfc7, 0x1, Cpu586,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "sysenter", 0, 0xf34, None, Cpu686,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "sysexit", 0, 0xf35, None, Cpu686,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fxsave", 1, 0xfae, 0x0, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fxrstor", 1, 0xfae, 0x1, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "rdpmc", 0, 0xf33, None, Cpu686,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ud2", 0, 0xf0b, None, Cpu686,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ud2a", 0, 0xf0b, None, Cpu686,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "ud2b", 0, 0xfb9, None, Cpu686,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cmovo", 2, 0xf40, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovno", 2, 0xf41, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovb", 2, 0xf42, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovc", 2, 0xf42, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovnae", 2, 0xf42, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovae", 2, 0xf43, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovnc", 2, 0xf43, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovnb", 2, 0xf43, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmove", 2, 0xf44, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovz", 2, 0xf44, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovne", 2, 0xf45, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovnz", 2, 0xf45, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovbe", 2, 0xf46, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovna", 2, 0xf46, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmova", 2, 0xf47, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovnbe", 2, 0xf47, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovs", 2, 0xf48, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovns", 2, 0xf49, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovp", 2, 0xf4a, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovnp", 2, 0xf4b, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovl", 2, 0xf4c, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovnge", 2, 0xf4c, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovge", 2, 0xf4d, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovnl", 2, 0xf4d, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovle", 2, 0xf4e, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovng", 2, 0xf4e, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovg", 2, 0xf4f, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "cmovnle", 2, 0xf4f, None, Cpu686,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "fcmovb", 2, 0xdac0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcmovnae", 2, 0xdac0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcmove", 2, 0xdac8, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcmovbe", 2, 0xdad0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcmovna", 2, 0xdad0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcmovu", 2, 0xdad8, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcmovae", 2, 0xdbc0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcmovnb", 2, 0xdbc0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcmovne", 2, 0xdbc8, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcmova", 2, 0xdbd0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcmovnbe", 2, 0xdbd0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcmovnu", 2, 0xdbd8, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcomi", 2, 0xdbf0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcomi", 0, 0xdbf1, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fcomi", 1, 0xdbf0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fucomi", 2, 0xdbe8, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fucomi", 0, 0xdbe9, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fucomi", 1, 0xdbe8, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fcomip", 2, 0xdff0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcompi", 2, 0xdff0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fcompi", 0, 0xdff1, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fcompi", 1, 0xdff0, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "fucomip", 2, 0xdfe8, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fucompi", 2, 0xdfe8, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg,
|
|
|
|
|
FloatAcc } },
|
|
|
|
|
{ "fucompi", 0, 0xdfe9, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "fucompi", 1, 0xdfe8, None, Cpu686,
|
|
|
|
|
ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ FloatReg } },
|
|
|
|
|
{ "movnti", 2, 0xfc3, None, CpuP4,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "clflush", 1, 0xfae, 0x7, CpuP4,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "lfence", 0, 0xfae, 0xe8, CpuP4,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "mfence", 0, 0xfae, 0xf0, CpuP4,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "pause", 0, 0xf390, None, CpuP4,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "emms", 0, 0xf77, None, CpuMMX,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "movd", 2, 0xf6e, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "movd", 2, 0xf7e, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegMMX,
|
|
|
|
|
Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movd", 2, 0x660f6e, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movd", 2, 0x660f7e, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movq", 2, 0xf6f, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "movq", 2, 0xf7f, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ RegMMX,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } },
|
|
|
|
|
{ "movq", 2, 0xf30f7e, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movq", 2, 0x660fd6, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
|
|
|
|
|
{ "movq", 2, 0xf6e, None, Cpu64,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "movq", 2, 0xf7e, None, Cpu64,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegMMX,
|
|
|
|
|
Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movq", 2, 0x660f6e, None, Cpu64,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movq", 2, 0x660f7e, None, Cpu64,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movq", 2, 0xa0, None, Cpu64,
|
|
|
|
|
D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Disp64,
|
|
|
|
|
Acc } },
|
|
|
|
|
{ "movq", 2, 0x88, None, Cpu64,
|
|
|
|
|
D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg64,
|
|
|
|
|
Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movq", 2, 0xc6, 0x0, Cpu64,
|
|
|
|
|
W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm32S,
|
|
|
|
|
Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movq", 2, 0xb0, None, Cpu64,
|
|
|
|
|
W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm64,
|
|
|
|
|
Reg64 } },
|
|
|
|
|
{ "movq", 2, 0x8c, None, Cpu64,
|
|
|
|
|
Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ SReg2|SReg3,
|
|
|
|
|
Reg64|RegMem } },
|
|
|
|
|
{ "movq", 2, 0x8e, None, Cpu64,
|
|
|
|
|
Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg64,
|
|
|
|
|
SReg2|SReg3 } },
|
|
|
|
|
{ "movq", 2, 0xf20, None, Cpu64,
|
|
|
|
|
D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Control,
|
|
|
|
|
Reg64|RegMem } },
|
|
|
|
|
{ "movq", 2, 0xf21, None, Cpu64,
|
|
|
|
|
D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Debug,
|
|
|
|
|
Reg64|RegMem } },
|
|
|
|
|
{ "packssdw", 2, 0xf6b, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "packssdw", 2, 0x660f6b, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "packsswb", 2, 0xf63, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "packsswb", 2, 0x660f63, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "packuswb", 2, 0xf67, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "packuswb", 2, 0x660f67, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "paddb", 2, 0xffc, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "paddb", 2, 0x660ffc, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "paddw", 2, 0xffd, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "paddw", 2, 0x660ffd, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "paddd", 2, 0xffe, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "paddd", 2, 0x660ffe, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "paddq", 2, 0xfd4, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "paddq", 2, 0x660fd4, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "paddsb", 2, 0xfec, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "paddsb", 2, 0x660fec, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "paddsw", 2, 0xfed, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "paddsw", 2, 0x660fed, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "paddusb", 2, 0xfdc, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "paddusb", 2, 0x660fdc, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "paddusw", 2, 0xfdd, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "paddusw", 2, 0x660fdd, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pand", 2, 0xfdb, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pand", 2, 0x660fdb, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pandn", 2, 0xfdf, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pandn", 2, 0x660fdf, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpeqb", 2, 0xf74, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pcmpeqb", 2, 0x660f74, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpeqw", 2, 0xf75, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pcmpeqw", 2, 0x660f75, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpeqd", 2, 0xf76, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pcmpeqd", 2, 0x660f76, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpgtb", 2, 0xf64, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pcmpgtb", 2, 0x660f64, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpgtw", 2, 0xf65, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pcmpgtw", 2, 0x660f65, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpgtd", 2, 0xf66, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pcmpgtd", 2, 0x660f66, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmaddwd", 2, 0xff5, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pmaddwd", 2, 0x660ff5, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmulhw", 2, 0xfe5, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pmulhw", 2, 0x660fe5, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmullw", 2, 0xfd5, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pmullw", 2, 0x660fd5, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "por", 2, 0xfeb, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "por", 2, 0x660feb, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psllw", 2, 0xff1, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psllw", 2, 0x660ff1, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psllw", 2, 0xf71, 0x6, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psllw", 2, 0x660f71, 0x6, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pslld", 2, 0xff2, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pslld", 2, 0x660ff2, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pslld", 2, 0xf72, 0x6, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pslld", 2, 0x660f72, 0x6, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psllq", 2, 0xff3, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psllq", 2, 0x660ff3, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psllq", 2, 0xf73, 0x6, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psllq", 2, 0x660f73, 0x6, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psraw", 2, 0xfe1, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psraw", 2, 0x660fe1, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psraw", 2, 0xf71, 0x4, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psraw", 2, 0x660f71, 0x4, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psrad", 2, 0xfe2, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psrad", 2, 0x660fe2, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psrad", 2, 0xf72, 0x4, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psrad", 2, 0x660f72, 0x4, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psrlw", 2, 0xfd1, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psrlw", 2, 0x660fd1, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psrlw", 2, 0xf71, 0x2, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psrlw", 2, 0x660f71, 0x2, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psrld", 2, 0xfd2, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psrld", 2, 0x660fd2, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psrld", 2, 0xf72, 0x2, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psrld", 2, 0x660f72, 0x2, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psrlq", 2, 0xfd3, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psrlq", 2, 0x660fd3, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psrlq", 2, 0xf73, 0x2, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psrlq", 2, 0x660f73, 0x2, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psubb", 2, 0xff8, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psubb", 2, 0x660ff8, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psubw", 2, 0xff9, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psubw", 2, 0x660ff9, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psubd", 2, 0xffa, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psubd", 2, 0x660ffa, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psubq", 2, 0xffb, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psubq", 2, 0x660ffb, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psubsb", 2, 0xfe8, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psubsb", 2, 0x660fe8, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psubsw", 2, 0xfe9, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psubsw", 2, 0x660fe9, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psubusb", 2, 0xfd8, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psubusb", 2, 0x660fd8, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psubusw", 2, 0xfd9, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psubusw", 2, 0x660fd9, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "punpckhbw", 2, 0xf68, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "punpckhbw", 2, 0x660f68, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "punpckhwd", 2, 0xf69, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "punpckhwd", 2, 0x660f69, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "punpckhdq", 2, 0xf6a, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "punpckhdq", 2, 0x660f6a, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "punpcklbw", 2, 0xf60, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "punpcklbw", 2, 0x660f60, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "punpcklwd", 2, 0xf61, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "punpcklwd", 2, 0x660f61, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "punpckldq", 2, 0xf62, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "punpckldq", 2, 0x660f62, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pxor", 2, 0xfef, None, CpuMMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pxor", 2, 0x660fef, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "addps", 2, 0xf58, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "addss", 2, 0xf30f58, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "andnps", 2, 0xf55, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "andps", 2, 0xf54, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpeqps", 2, 0xfc2, 0x0, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpeqss", 2, 0xf30fc2, 0x0, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpleps", 2, 0xfc2, 0x2, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpless", 2, 0xf30fc2, 0x2, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpltps", 2, 0xfc2, 0x1, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpltss", 2, 0xf30fc2, 0x1, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpneqps", 2, 0xfc2, 0x4, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpneqss", 2, 0xf30fc2, 0x4, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpnleps", 2, 0xfc2, 0x6, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpnless", 2, 0xf30fc2, 0x6, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpnltps", 2, 0xfc2, 0x5, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpnltss", 2, 0xf30fc2, 0x5, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpordps", 2, 0xfc2, 0x7, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpordss", 2, 0xf30fc2, 0x7, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpunordps", 2, 0xfc2, 0x3, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpunordss", 2, 0xf30fc2, 0x3, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpps", 3, 0xfc2, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpss", 3, 0xf30fc2, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "comiss", 2, 0xf2f, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtpi2ps", 2, 0xf2a, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtps2pi", 2, 0xf2d, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "cvtsi2ss", 2, 0xf30f2a, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtss2si", 2, 0xf30f2d, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
Reg32|Reg64 } },
|
|
|
|
|
{ "cvttps2pi", 2, 0xf2c, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "cvttss2si", 2, 0xf30f2c, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
Reg32|Reg64 } },
|
|
|
|
|
{ "divps", 2, 0xf5e, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "divss", 2, 0xf30f5e, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "ldmxcsr", 1, 0xfae, 0x2, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "maskmovq", 2, 0xff7, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "maxps", 2, 0xf5f, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "maxss", 2, 0xf30f5f, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "minps", 2, 0xf5d, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "minss", 2, 0xf30f5d, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movaps", 2, 0xf28, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movaps", 2, 0xf29, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
|
|
|
|
|
{ "movhlps", 2, 0xf12, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movhps", 2, 0xf16, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movhps", 2, 0xf17, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movlhps", 2, 0xf16, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movlps", 2, 0xf12, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movlps", 2, 0xf13, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movmskps", 2, 0xf50, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
Reg32|Reg64 } },
|
|
|
|
|
{ "movntps", 2, 0xf2b, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movntq", 2, 0xfe7, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegMMX,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movntdq", 2, 0x660fe7, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movss", 2, 0xf30f10, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movss", 2, 0xf30f11, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
|
|
|
|
|
{ "movups", 2, 0xf10, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movups", 2, 0xf11, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
|
|
|
|
|
{ "mulps", 2, 0xf59, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "mulss", 2, 0xf30f59, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "orps", 2, 0xf56, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pavgb", 2, 0xfe0, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pavgb", 2, 0x660fe0, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pavgw", 2, 0xfe3, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pavgw", 2, 0x660fe3, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pextrw", 3, 0xfc5, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegMMX,
|
|
|
|
|
Reg32|Reg64 } },
|
|
|
|
|
{ "pextrw", 3, 0x660fc5, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM,
|
|
|
|
|
Reg32|Reg64 } },
|
|
|
|
|
{ "pextrw", 3, 0x660f3a15, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM,
|
|
|
|
|
Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "pinsrw", 3, 0xfc4, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pinsrw", 3, 0x660fc4, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmaxsw", 2, 0xfee, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pmaxsw", 2, 0x660fee, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmaxub", 2, 0xfde, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pmaxub", 2, 0x660fde, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pminsw", 2, 0xfea, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pminsw", 2, 0x660fea, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pminub", 2, 0xfda, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pminub", 2, 0x660fda, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovmskb", 2, 0xfd7, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ RegMMX,
|
|
|
|
|
Reg32|Reg64 } },
|
|
|
|
|
{ "pmovmskb", 2, 0x660fd7, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
Reg32|Reg64 } },
|
|
|
|
|
{ "pmulhuw", 2, 0xfe4, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pmulhuw", 2, 0x660fe4, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "prefetchnta", 1, 0xf18, 0x0, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "prefetcht0", 1, 0xf18, 0x1, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "prefetcht1", 1, 0xf18, 0x2, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "prefetcht2", 1, 0xf18, 0x3, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "psadbw", 2, 0xff6, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psadbw", 2, 0x660ff6, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pshufw", 3, 0xf70, None, CpuMMX2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "rcpps", 2, 0xf53, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "rcpss", 2, 0xf30f53, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "rsqrtps", 2, 0xf52, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "rsqrtss", 2, 0xf30f52, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "sfence", 0, 0xfae, 0xf8, CpuMMX2,
|
|
|
|
|
IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "shufps", 3, 0xfc6, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "sqrtps", 2, 0xf51, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "sqrtss", 2, 0xf30f51, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "stmxcsr", 1, 0xfae, 0x3, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "subps", 2, 0xf5c, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "subss", 2, 0xf30f5c, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "ucomiss", 2, 0xf2e, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "unpckhps", 2, 0xf15, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "unpcklps", 2, 0xf14, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "xorps", 2, 0xf57, None, CpuSSE,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "addpd", 2, 0x660f58, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "addsd", 2, 0xf20f58, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "andnpd", 2, 0x660f55, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "andpd", 2, 0x660f54, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpeqpd", 2, 0x660fc2, 0x0, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpeqsd", 2, 0xf20fc2, 0x0, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmplepd", 2, 0x660fc2, 0x2, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmplesd", 2, 0xf20fc2, 0x2, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpltpd", 2, 0x660fc2, 0x1, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpltsd", 2, 0xf20fc2, 0x1, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpneqpd", 2, 0x660fc2, 0x4, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpneqsd", 2, 0xf20fc2, 0x4, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpnlepd", 2, 0x660fc2, 0x6, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpnlesd", 2, 0xf20fc2, 0x6, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpnltpd", 2, 0x660fc2, 0x5, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpnltsd", 2, 0xf20fc2, 0x5, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpordpd", 2, 0x660fc2, 0x7, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpordsd", 2, 0xf20fc2, 0x7, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpunordpd", 2, 0x660fc2, 0x3, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpunordsd", 2, 0xf20fc2, 0x3, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmppd", 3, 0x660fc2, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpsd", 0, 0xa7, None, 0,
|
|
|
|
|
Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "cmpsd", 2, 0xa7, None, 0,
|
|
|
|
|
Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
|
|
|
|
|
{ "cmpsd", 3, 0xf20fc2, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "comisd", 2, 0x660f2f, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtpi2pd", 2, 0x660f2a, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtsi2sd", 2, 0xf20f2a, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "divpd", 2, 0x660f5e, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "divsd", 2, 0xf20f5e, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "maxpd", 2, 0x660f5f, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "maxsd", 2, 0xf20f5f, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "minpd", 2, 0x660f5d, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "minsd", 2, 0xf20f5d, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movapd", 2, 0x660f28, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movapd", 2, 0x660f29, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
|
|
|
|
|
{ "movhpd", 2, 0x660f16, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movhpd", 2, 0x660f17, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movlpd", 2, 0x660f12, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movlpd", 2, 0x660f13, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movmskpd", 2, 0x660f50, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
Reg32|Reg64 } },
|
|
|
|
|
{ "movntpd", 2, 0x660f2b, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movsd", 0, 0xa5, None, 0,
|
|
|
|
|
Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "movsd", 2, 0xa5, None, 0,
|
|
|
|
|
Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
|
|
|
|
|
{ "movsd", 2, 0xf20f10, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movsd", 2, 0xf20f11, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
|
|
|
|
|
{ "movupd", 2, 0x660f10, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movupd", 2, 0x660f11, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
|
|
|
|
|
{ "mulpd", 2, 0x660f59, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "mulsd", 2, 0xf20f59, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "orpd", 2, 0x660f56, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "shufpd", 3, 0x660fc6, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "sqrtpd", 2, 0x660f51, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "sqrtsd", 2, 0xf20f51, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "subpd", 2, 0x660f5c, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "subsd", 2, 0xf20f5c, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "ucomisd", 2, 0x660f2e, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "unpckhpd", 2, 0x660f15, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "unpcklpd", 2, 0x660f14, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "xorpd", 2, 0x660f57, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtdq2pd", 2, 0xf30fe6, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtpd2dq", 2, 0xf20fe6, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtdq2ps", 2, 0xf5b, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtpd2pi", 2, 0x660f2d, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "cvtpd2ps", 2, 0x660f5a, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtps2pd", 2, 0xf5a, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtps2dq", 2, 0x660f5b, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtsd2si", 2, 0xf20f2d, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
Reg32|Reg64 } },
|
|
|
|
|
{ "cvtsd2ss", 2, 0xf20f5a, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvtss2sd", 2, 0xf30f5a, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvttpd2pi", 2, 0x660f2c, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "cvttsd2si", 2, 0xf20f2c, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
Reg32|Reg64 } },
|
|
|
|
|
{ "cvttpd2dq", 2, 0x660fe6, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cvttps2dq", 2, 0xf30f5b, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "maskmovdqu", 2, 0x660ff7, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movdqa", 2, 0x660f6f, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movdqa", 2, 0x660f7f, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
|
|
|
|
|
{ "movdqu", 2, 0xf30f6f, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movdqu", 2, 0xf30f7f, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
|
|
|
|
|
{ "movdq2q", 2, 0xf20fd6, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "movq2dq", 2, 0xf30fd6, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegMMX,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmuludq", 2, 0xff4, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pmuludq", 2, 0x660ff4, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pshufd", 3, 0x660f70, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pshufhw", 3, 0xf30f70, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pshuflw", 3, 0xf20f70, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pslldq", 2, 0x660f73, 0x7, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psrldq", 2, 0x660f73, 0x3, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "punpckhqdq", 2, 0x660f6d, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "punpcklqdq", 2, 0x660f6c, None, CpuSSE2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "addsubpd", 2, 0x660fd0, None, CpuSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "addsubps", 2, 0xf20fd0, None, CpuSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "cmpxchg16b", 1, 0xfc7, 0x1, CpuSSE3|Cpu64,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fisttp", 1, 0xdf, 0x1, CpuSSE3,
|
|
|
|
|
Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fisttp", 1, 0xdd, 0x1, CpuSSE3,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "fisttpll", 1, 0xdd, 0x1, CpuSSE3,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "haddpd", 2, 0x660f7c, None, CpuSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "haddps", 2, 0xf20f7c, None, CpuSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "hsubpd", 2, 0x660f7d, None, CpuSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "hsubps", 2, 0xf20f7d, None, CpuSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "lddqu", 2, 0xf20ff0, None, CpuSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "monitor", 0, 0xf01, 0xc8, CpuSSE3,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "monitor", 3, 0xf01, 0xc8, CpuSSE3|CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ Reg16|Reg32,
|
|
|
|
|
Reg32,
|
|
|
|
|
Reg32 } },
|
|
|
|
|
{ "monitor", 3, 0xf01, 0xc8, CpuSSE3|Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
|
|
|
|
|
{ Reg32|Reg64,
|
|
|
|
|
Reg64,
|
|
|
|
|
Reg64 } },
|
|
|
|
|
{ "movddup", 2, 0xf20f12, None, CpuSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movshdup", 2, 0xf30f16, None, CpuSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movsldup", 2, 0xf30f12, None, CpuSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "mwait", 0, 0xf01, 0xc9, CpuSSE3,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "mwait", 2, 0xf01, 0xc9, CpuSSE3|CpuNo64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ Reg32,
|
|
|
|
|
Reg32 } },
|
|
|
|
|
{ "mwait", 2, 0xf01, 0xc9, CpuSSE3|Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
|
|
|
|
|
{ Reg64,
|
|
|
|
|
Reg64 } },
|
|
|
|
|
{ "vmcall", 0, 0xf01, 0xc1, CpuVMX,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "vmclear", 1, 0x660fc7, 0x6, CpuVMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "vmlaunch", 0, 0xf01, 0xc2, CpuVMX,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "vmresume", 0, 0xf01, 0xc3, CpuVMX,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "vmptrld", 1, 0xfc7, 0x6, CpuVMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "vmptrst", 1, 0xfc7, 0x7, CpuVMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "vmread", 2, 0xf78, None, CpuVMX|CpuNo64,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg32,
|
|
|
|
|
Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "vmread", 2, 0xf78, None, CpuVMX|Cpu64,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Reg64,
|
|
|
|
|
Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "vmwrite", 2, 0xf79, None, CpuVMX|CpuNo64,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg32 } },
|
|
|
|
|
{ "vmwrite", 2, 0xf79, None, CpuVMX|Cpu64,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg64 } },
|
|
|
|
|
{ "vmxoff", 0, 0xf01, 0xc4, CpuVMX,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "vmxon", 1, 0xf30fc7, 0x6, CpuVMX,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "phaddw", 2, 0xf3801, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "phaddw", 2, 0x660f3801, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "phaddd", 2, 0xf3802, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "phaddd", 2, 0x660f3802, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "phaddsw", 2, 0xf3803, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "phaddsw", 2, 0x660f3803, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "phsubw", 2, 0xf3805, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "phsubw", 2, 0x660f3805, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "phsubd", 2, 0xf3806, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "phsubd", 2, 0x660f3806, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "phsubsw", 2, 0xf3807, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "phsubsw", 2, 0x660f3807, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmaddubsw", 2, 0xf3804, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pmaddubsw", 2, 0x660f3804, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmulhrsw", 2, 0xf380b, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pmulhrsw", 2, 0x660f380b, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pshufb", 2, 0xf3800, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pshufb", 2, 0x660f3800, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psignb", 2, 0xf3808, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psignb", 2, 0x660f3808, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psignw", 2, 0xf3809, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psignw", 2, 0x660f3809, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "psignd", 2, 0xf380a, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "psignd", 2, 0x660f380a, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "palignr", 3, 0xf3a0f, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "palignr", 3, 0x660f3a0f, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pabsb", 2, 0xf381c, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pabsb", 2, 0x660f381c, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pabsw", 2, 0xf381d, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pabsw", 2, 0x660f381d, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pabsd", 2, 0xf381e, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pabsd", 2, 0x660f381e, None, CpuSSSE3,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "blendpd", 3, 0x660f3a0d, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "blendps", 3, 0x660f3a0c, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "blendvpd", 3, 0x660f3815, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "blendvps", 3, 0x660f3814, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "dppd", 3, 0x660f3a41, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "dpps", 3, 0x660f3a40, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "extractps", 3, 0x660f3a17, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM,
|
|
|
|
|
Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "insertps", 3, 0x660f3a21, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "movntdqa", 2, 0x660f382a, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "mpsadbw", 3, 0x660f3a42, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "packusdw", 2, 0x660f382b, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pblendvb", 3, 0x660f3810, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pblendw", 3, 0x660f3a0e, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpeqq", 2, 0x660f3829, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pextrb", 3, 0x660f3a14, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM,
|
|
|
|
|
Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "pextrd", 3, 0x660f3a16, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM,
|
|
|
|
|
Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "pextrq", 3, 0x660f3a16, None, CpuSSE4_1|Cpu64,
|
|
|
|
|
Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
RegXMM,
|
|
|
|
|
Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "phminposuw", 2, 0x660f3841, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pinsrb", 3, 0x660f3a20, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pinsrd", 3, 0x660f3a22, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pinsrq", 3, 0x660f3a22, None, CpuSSE4_1|Cpu64,
|
|
|
|
|
Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmaxsb", 2, 0x660f383c, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmaxsd", 2, 0x660f383d, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmaxud", 2, 0x660f383f, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmaxuw", 2, 0x660f383e, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pminsb", 2, 0x660f3838, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pminsd", 2, 0x660f3839, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pminud", 2, 0x660f383b, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pminuw", 2, 0x660f383a, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovsxbw", 2, 0x660f3820, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovsxbd", 2, 0x660f3821, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovsxbq", 2, 0x660f3822, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovsxwd", 2, 0x660f3823, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovsxwq", 2, 0x660f3824, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovsxdq", 2, 0x660f3825, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovzxbw", 2, 0x660f3830, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovzxbd", 2, 0x660f3831, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovzxbq", 2, 0x660f3832, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovzxwd", 2, 0x660f3833, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovzxwq", 2, 0x660f3834, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmovzxdq", 2, 0x660f3835, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmuldq", 2, 0x660f3828, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pmulld", 2, 0x660f3840, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "ptest", 2, 0x660f3817, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "roundpd", 3, 0x660f3a09, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "roundps", 3, 0x660f3a08, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "roundsd", 3, 0x660f3a0b, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "roundss", 3, 0x660f3a0a, None, CpuSSE4_1,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpgtq", 2, 0x660f3837, None, CpuSSE4_2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpestri", 3, 0x660f3a61, None, CpuSSE4_2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpestrm", 3, 0x660f3a60, None, CpuSSE4_2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpistri", 3, 0x660f3a63, None, CpuSSE4_2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "pcmpistrm", 3, 0x660f3a62, None, CpuSSE4_2,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "crc32", 2, 0xf20f38f1, None, CpuSSE4_2,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg32 } },
|
|
|
|
|
{ "crc32", 2, 0xf20f38f1, None, CpuSSE4_2|Cpu64,
|
|
|
|
|
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|Rex64,
|
|
|
|
|
{ Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg64 } },
|
|
|
|
|
{ "crc32", 2, 0xf20f38f0, None, CpuSSE4_2,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg32 } },
|
|
|
|
|
{ "crc32", 2, 0xf20f38f0, None, CpuSSE4_2|Cpu64,
|
|
|
|
|
Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
|
|
|
|
|
{ Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg64 } },
|
|
|
|
|
{ "prefetch", 1, 0xf0d, 0x0, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "prefetchw", 1, 0xf0d, 0x1, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "femms", 0, 0xf0e, None, Cpu3dnow,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "pavgusb", 2, 0xf0f, 0xbf, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pf2id", 2, 0xf0f, 0x1d, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pf2iw", 2, 0xf0f, 0x1c, Cpu3dnowA,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfacc", 2, 0xf0f, 0xae, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfadd", 2, 0xf0f, 0x9e, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfcmpeq", 2, 0xf0f, 0xb0, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfcmpge", 2, 0xf0f, 0x90, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfcmpgt", 2, 0xf0f, 0xa0, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfmax", 2, 0xf0f, 0xa4, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfmin", 2, 0xf0f, 0x94, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfmul", 2, 0xf0f, 0xb4, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfnacc", 2, 0xf0f, 0x8a, Cpu3dnowA,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfpnacc", 2, 0xf0f, 0x8e, Cpu3dnowA,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfrcp", 2, 0xf0f, 0x96, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfrcpit1", 2, 0xf0f, 0xa6, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfrcpit2", 2, 0xf0f, 0xb6, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfrsqit1", 2, 0xf0f, 0xa7, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfrsqrt", 2, 0xf0f, 0x97, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfsub", 2, 0xf0f, 0x9a, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pfsubr", 2, 0xf0f, 0xaa, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pi2fd", 2, 0xf0f, 0xd, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pi2fw", 2, 0xf0f, 0xc, Cpu3dnowA,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pmulhrw", 2, 0xf0f, 0xb7, Cpu3dnow,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "pswapd", 2, 0xf0f, 0xbb, Cpu3dnowA,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
|
|
|
|
|
RegMMX } },
|
|
|
|
|
{ "syscall", 0, 0xf05, None, CpuK6,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "sysret", 0, 0xf07, None, CpuK6,
|
|
|
|
|
DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "swapgs", 0, 0xf01, 0xf8, Cpu64,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "rdtscp", 0, 0xf01, 0xf9, CpuSledgehammer,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "clgi", 0, 0xf01, 0xdd, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "invlpga", 0, 0xf01, 0xdf, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "invlpga", 2, 0xf01, 0xdf, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg32 } },
|
|
|
|
|
{ "skinit", 0, 0xf01, 0xde, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "skinit", 1, 0xf01, 0xde, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "stgi", 0, 0xf01, 0xdc, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "vmload", 0, 0xf01, 0xda, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "vmload", 1, 0xf01, 0xda, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "vmmcall", 0, 0xf01, 0xd9, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "vmrun", 0, 0xf01, 0xd8, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "vmrun", 1, 0xf01, 0xd8, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "vmsave", 0, 0xf01, 0xdb, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "vmsave", 1, 0xf01, 0xdb, CpuSVME,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
|
|
|
|
|
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movntsd", 2, 0xf20f2b, None, CpuSSE4a,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "movntss", 2, 0xf30f2b, None, CpuSSE4a,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
|
|
|
|
|
{ "extrq", 3, 0x660f78, 0x0, CpuSSE4a,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Imm8,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "extrq", 2, 0x660f79, None, CpuSSE4a,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "insertq", 2, 0xf20f79, None, CpuSSE4a,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "insertq", 4, 0xf20f78, None, CpuSSE4a,
|
|
|
|
|
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
|
|
|
|
|
{ Imm8,
|
|
|
|
|
Imm8,
|
|
|
|
|
RegXMM,
|
|
|
|
|
RegXMM } },
|
|
|
|
|
{ "popcnt", 2, 0xf30fb8, None, CpuABM|CpuSSE4_2,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "lzcnt", 2, 0xf30fbd, None, CpuABM,
|
|
|
|
|
Modrm|No_bSuf|No_sSuf|No_xSuf,
|
|
|
|
|
{ Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
|
|
|
|
|
Reg16|Reg32|Reg64 } },
|
|
|
|
|
{ "xstore-rng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xcrypt-ecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xcrypt-cbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xcrypt-ctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xcrypt-cfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xcrypt-ofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xstorerng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock,
|
|
|
|
|
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
|
|
|
|
|
{ 0 } },
|
|
|
|
|
{ "xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock,
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No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
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{ 0 } },
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{ "xstore", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
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No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
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{ 0 } },
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{ NULL, 0, 0, 0, 0, 0, { 0 } }
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};
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/* i386 register table. */
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const reg_entry i386_regtab[] =
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{
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{ "st", FloatReg|FloatAcc, 0, 0 },
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{ "al", Reg8|Acc, 0, 0 },
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{ "cl", Reg8|ShiftCount, 0, 1 },
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{ "dl", Reg8, 0, 2 },
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{ "bl", Reg8, 0, 3 },
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{ "ah", Reg8, 0, 4 },
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{ "ch", Reg8, 0, 5 },
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{ "dh", Reg8, 0, 6 },
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{ "bh", Reg8, 0, 7 },
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{ "axl", Reg8|Acc, RegRex64, 0 },
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{ "cxl", Reg8, RegRex64, 1 },
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{ "dxl", Reg8, RegRex64, 2 },
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{ "bxl", Reg8, RegRex64, 3 },
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{ "spl", Reg8, RegRex64, 4 },
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{ "bpl", Reg8, RegRex64, 5 },
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{ "sil", Reg8, RegRex64, 6 },
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{ "dil", Reg8, RegRex64, 7 },
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{ "r8b", Reg8, RegRex|RegRex64, 0 },
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{ "r9b", Reg8, RegRex|RegRex64, 1 },
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{ "r10b", Reg8, RegRex|RegRex64, 2 },
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{ "r11b", Reg8, RegRex|RegRex64, 3 },
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{ "r12b", Reg8, RegRex|RegRex64, 4 },
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{ "r13b", Reg8, RegRex|RegRex64, 5 },
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{ "r14b", Reg8, RegRex|RegRex64, 6 },
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{ "r15b", Reg8, RegRex|RegRex64, 7 },
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{ "ax", Reg16|Acc, 0, 0 },
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{ "cx", Reg16, 0, 1 },
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{ "dx", Reg16|InOutPortReg, 0, 2 },
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{ "bx", Reg16|BaseIndex, 0, 3 },
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{ "sp", Reg16, 0, 4 },
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{ "bp", Reg16|BaseIndex, 0, 5 },
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{ "si", Reg16|BaseIndex, 0, 6 },
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{ "di", Reg16|BaseIndex, 0, 7 },
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{ "r8w", Reg16, RegRex, 0 },
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{ "r9w", Reg16, RegRex, 1 },
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{ "r10w", Reg16, RegRex, 2 },
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{ "r11w", Reg16, RegRex, 3 },
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{ "r12w", Reg16, RegRex, 4 },
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{ "r13w", Reg16, RegRex, 5 },
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{ "r14w", Reg16, RegRex, 6 },
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{ "r15w", Reg16, RegRex, 7 },
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{ "eax", Reg32|BaseIndex|Acc, 0, 0 },
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{ "ecx", Reg32|BaseIndex, 0, 1 },
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{ "edx", Reg32|BaseIndex, 0, 2 },
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{ "ebx", Reg32|BaseIndex, 0, 3 },
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{ "esp", Reg32, 0, 4 },
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{ "ebp", Reg32|BaseIndex, 0, 5 },
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{ "esi", Reg32|BaseIndex, 0, 6 },
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{ "edi", Reg32|BaseIndex, 0, 7 },
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{ "r8d", Reg32|BaseIndex, RegRex, 0 },
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{ "r9d", Reg32|BaseIndex, RegRex, 1 },
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{ "r10d", Reg32|BaseIndex, RegRex, 2 },
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{ "r11d", Reg32|BaseIndex, RegRex, 3 },
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{ "r12d", Reg32|BaseIndex, RegRex, 4 },
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{ "r13d", Reg32|BaseIndex, RegRex, 5 },
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{ "r14d", Reg32|BaseIndex, RegRex, 6 },
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{ "r15d", Reg32|BaseIndex, RegRex, 7 },
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{ "rax", Reg64|BaseIndex|Acc, 0, 0 },
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{ "rcx", Reg64|BaseIndex, 0, 1 },
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{ "rdx", Reg64|BaseIndex, 0, 2 },
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{ "rbx", Reg64|BaseIndex, 0, 3 },
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{ "rsp", Reg64, 0, 4 },
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{ "rbp", Reg64|BaseIndex, 0, 5 },
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{ "rsi", Reg64|BaseIndex, 0, 6 },
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{ "rdi", Reg64|BaseIndex, 0, 7 },
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{ "r8", Reg64|BaseIndex, RegRex, 0 },
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{ "r9", Reg64|BaseIndex, RegRex, 1 },
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{ "r10", Reg64|BaseIndex, RegRex, 2 },
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{ "r11", Reg64|BaseIndex, RegRex, 3 },
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{ "r12", Reg64|BaseIndex, RegRex, 4 },
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{ "r13", Reg64|BaseIndex, RegRex, 5 },
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{ "r14", Reg64|BaseIndex, RegRex, 6 },
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{ "r15", Reg64|BaseIndex, RegRex, 7 },
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{ "es", SReg2, 0, 0 },
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{ "cs", SReg2, 0, 1 },
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{ "ss", SReg2, 0, 2 },
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{ "ds", SReg2, 0, 3 },
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{ "fs", SReg3, 0, 4 },
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{ "gs", SReg3, 0, 5 },
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{ "cr0", Control, 0, 0 },
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{ "cr1", Control, 0, 1 },
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{ "cr2", Control, 0, 2 },
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{ "cr3", Control, 0, 3 },
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{ "cr4", Control, 0, 4 },
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{ "cr5", Control, 0, 5 },
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{ "cr6", Control, 0, 6 },
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{ "cr7", Control, 0, 7 },
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{ "cr8", Control, RegRex, 0 },
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{ "cr9", Control, RegRex, 1 },
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{ "cr10", Control, RegRex, 2 },
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{ "cr11", Control, RegRex, 3 },
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{ "cr12", Control, RegRex, 4 },
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{ "cr13", Control, RegRex, 5 },
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{ "cr14", Control, RegRex, 6 },
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{ "cr15", Control, RegRex, 7 },
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{ "db0", Debug, 0, 0 },
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{ "db1", Debug, 0, 1 },
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{ "db2", Debug, 0, 2 },
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{ "db3", Debug, 0, 3 },
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{ "db4", Debug, 0, 4 },
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{ "db5", Debug, 0, 5 },
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{ "db6", Debug, 0, 6 },
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{ "db7", Debug, 0, 7 },
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{ "db8", Debug, RegRex, 0 },
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{ "db9", Debug, RegRex, 1 },
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{ "db10", Debug, RegRex, 2 },
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{ "db11", Debug, RegRex, 3 },
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{ "db12", Debug, RegRex, 4 },
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{ "db13", Debug, RegRex, 5 },
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{ "db14", Debug, RegRex, 6 },
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{ "db15", Debug, RegRex, 7 },
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{ "dr0", Debug, 0, 0 },
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{ "dr1", Debug, 0, 1 },
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{ "dr2", Debug, 0, 2 },
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{ "dr3", Debug, 0, 3 },
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{ "dr4", Debug, 0, 4 },
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{ "dr5", Debug, 0, 5 },
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{ "dr6", Debug, 0, 6 },
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{ "dr7", Debug, 0, 7 },
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{ "dr8", Debug, RegRex, 0 },
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{ "dr9", Debug, RegRex, 1 },
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{ "dr10", Debug, RegRex, 2 },
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{ "dr11", Debug, RegRex, 3 },
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{ "dr12", Debug, RegRex, 4 },
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{ "dr13", Debug, RegRex, 5 },
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{ "dr14", Debug, RegRex, 6 },
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{ "dr15", Debug, RegRex, 7 },
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{ "tr0", Test, 0, 0 },
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{ "tr1", Test, 0, 1 },
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{ "tr2", Test, 0, 2 },
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{ "tr3", Test, 0, 3 },
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{ "tr4", Test, 0, 4 },
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{ "tr5", Test, 0, 5 },
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{ "tr6", Test, 0, 6 },
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{ "tr7", Test, 0, 7 },
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{ "mm0", RegMMX, 0, 0 },
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{ "mm1", RegMMX, 0, 1 },
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{ "mm2", RegMMX, 0, 2 },
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{ "mm3", RegMMX, 0, 3 },
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{ "mm4", RegMMX, 0, 4 },
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{ "mm5", RegMMX, 0, 5 },
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{ "mm6", RegMMX, 0, 6 },
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{ "mm7", RegMMX, 0, 7 },
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{ "xmm0", RegXMM, 0, 0 },
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{ "xmm1", RegXMM, 0, 1 },
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{ "xmm2", RegXMM, 0, 2 },
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{ "xmm3", RegXMM, 0, 3 },
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{ "xmm4", RegXMM, 0, 4 },
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{ "xmm5", RegXMM, 0, 5 },
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{ "xmm6", RegXMM, 0, 6 },
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{ "xmm7", RegXMM, 0, 7 },
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{ "xmm8", RegXMM, RegRex, 0 },
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{ "xmm9", RegXMM, RegRex, 1 },
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{ "xmm10", RegXMM, RegRex, 2 },
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{ "xmm11", RegXMM, RegRex, 3 },
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{ "xmm12", RegXMM, RegRex, 4 },
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{ "xmm13", RegXMM, RegRex, 5 },
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{ "xmm14", RegXMM, RegRex, 6 },
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{ "xmm15", RegXMM, RegRex, 7 },
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{ "rip", BaseIndex, 0, 0 },
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{ "st(0)", FloatReg|FloatAcc, 0, 0 },
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{ "st(1)", FloatReg, 0, 1 },
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{ "st(2)", FloatReg, 0, 2 },
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{ "st(3)", FloatReg, 0, 3 },
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{ "st(4)", FloatReg, 0, 4 },
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{ "st(5)", FloatReg, 0, 5 },
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{ "st(6)", FloatReg, 0, 6 },
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{ "st(7)", FloatReg, 0, 7 },
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};
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const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);
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