636 lines
18 KiB
C
636 lines
18 KiB
C
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/* This file is generated by the genmloop script. DO NOT EDIT! */
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/* Enable switch() support in cgen headers. */
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#define SEM_IN_SWITCH
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#define WANT_CPU sh64
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#define WANT_CPU_SH64
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#include "sim-main.h"
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#include "bfd.h"
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#include "cgen-mem.h"
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#include "cgen-ops.h"
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#include "sim-assert.h"
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/* Fill in the administrative ARGBUF fields required by all insns,
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virtual and real. */
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static INLINE void
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sh64_compact_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
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PCADDR pc, int fast_p)
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{
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#if WITH_SCACHE
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SEM_SET_CODE (abuf, idesc, fast_p);
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ARGBUF_ADDR (abuf) = pc;
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#endif
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ARGBUF_IDESC (abuf) = idesc;
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}
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/* Fill in tracing/profiling fields of an ARGBUF. */
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static INLINE void
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sh64_compact_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
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int trace_p, int profile_p)
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{
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ARGBUF_TRACE_P (abuf) = trace_p;
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ARGBUF_PROFILE_P (abuf) = profile_p;
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}
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#if WITH_SCACHE_PBB
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/* Emit the "x-before" handler.
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x-before is emitted before each insn (serial or parallel).
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This is as opposed to x-after which is only emitted at the end of a group
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of parallel insns. */
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static INLINE void
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sh64_compact_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
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{
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ARGBUF *abuf = &sc[0].argbuf;
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const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEFORE];
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abuf->fields.before.first_p = first_p;
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sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, 0);
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/* no need to set trace_p,profile_p */
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}
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/* Emit the "x-after" handler.
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x-after is emitted after a serial insn or at the end of a group of
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parallel insns. */
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static INLINE void
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sh64_compact_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
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{
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ARGBUF *abuf = &sc[0].argbuf;
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const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_AFTER];
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sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, 0);
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/* no need to set trace_p,profile_p */
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}
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#endif /* WITH_SCACHE_PBB */
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static INLINE const IDESC *
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extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
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int fast_p)
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{
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const IDESC *id = sh64_compact_decode (current_cpu, pc, insn, insn, abuf);
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sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
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if (! fast_p)
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{
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int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
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int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
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sh64_compact_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
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}
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return id;
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}
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static INLINE SEM_PC
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execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
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{
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SEM_PC vpc;
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if (fast_p)
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{
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#if ! WITH_SEM_SWITCH_FAST
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#if WITH_SCACHE
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vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
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#else
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vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
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#endif
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#else
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abort ();
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#endif /* WITH_SEM_SWITCH_FAST */
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}
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else
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{
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#if ! WITH_SEM_SWITCH_FULL
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ARGBUF *abuf = &sc->argbuf;
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const IDESC *idesc = abuf->idesc;
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#if WITH_SCACHE_PBB
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int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
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#else
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int virtual_p = 0;
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#endif
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if (! virtual_p)
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{
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/* FIXME: call x-before */
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if (ARGBUF_PROFILE_P (abuf))
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PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
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/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
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if (PROFILE_MODEL_P (current_cpu)
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&& ARGBUF_PROFILE_P (abuf))
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sh64_compact_model_insn_before (current_cpu, 1 /*first_p*/);
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TRACE_INSN_INIT (current_cpu, abuf, 1);
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TRACE_INSN (current_cpu, idesc->idata,
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(const struct argbuf *) abuf, abuf->addr);
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}
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#if WITH_SCACHE
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vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
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#else
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vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
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#endif
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if (! virtual_p)
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{
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/* FIXME: call x-after */
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if (PROFILE_MODEL_P (current_cpu)
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&& ARGBUF_PROFILE_P (abuf))
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{
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int cycles;
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cycles = (*idesc->timing->model_fn) (current_cpu, sc);
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sh64_compact_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
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}
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TRACE_INSN_FINI (current_cpu, abuf, 1);
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}
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#else
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abort ();
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#endif /* WITH_SEM_SWITCH_FULL */
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}
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return vpc;
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}
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/* Record address of cti terminating a pbb. */
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#define SET_CTI_VPC(sc) do { _cti_sc = (sc); } while (0)
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/* Record number of [real] insns in pbb. */
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#define SET_INSN_COUNT(n) do { _insn_count = (n); } while (0)
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/* Fetch and extract a pseudo-basic-block.
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FAST_P is non-zero if no tracing/profiling/etc. is wanted. */
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INLINE SEM_PC
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sh64_compact_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
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{
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SEM_PC new_vpc;
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PCADDR pc;
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SCACHE *sc;
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int max_insns = CPU_SCACHE_MAX_CHAIN_LENGTH (current_cpu);
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pc = GET_H_PC ();
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new_vpc = scache_lookup_or_alloc (current_cpu, pc, max_insns, &sc);
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if (! new_vpc)
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{
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/* Leading '_' to avoid collision with mainloop.in. */
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int _insn_count = 0;
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SCACHE *orig_sc = sc;
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SCACHE *_cti_sc = NULL;
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int slice_insns = CPU_MAX_SLICE_INSNS (current_cpu);
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/* First figure out how many instructions to compile.
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MAX_INSNS is the size of the allocated buffer, which includes space
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for before/after handlers if they're being used.
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SLICE_INSNS is the maxinum number of real insns that can be
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executed. Zero means "as many as we want". */
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/* ??? max_insns is serving two incompatible roles.
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1) Number of slots available in scache buffer.
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2) Number of real insns to execute.
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They're incompatible because there are virtual insns emitted too
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(chain,cti-chain,before,after handlers). */
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if (slice_insns == 1)
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{
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/* No need to worry about extra slots required for virtual insns
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and parallel exec support because MAX_CHAIN_LENGTH is
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guaranteed to be big enough to execute at least 1 insn! */
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max_insns = 1;
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}
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else
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{
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/* Allow enough slop so that while compiling insns, if max_insns > 0
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then there's guaranteed to be enough space to emit one real insn.
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MAX_CHAIN_LENGTH is typically much longer than
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the normal number of insns between cti's anyway. */
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max_insns -= (1 /* one for the trailing chain insn */
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+ (FAST_P
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? 0
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: (1 + MAX_PARALLEL_INSNS) /* before+after */)
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+ (MAX_PARALLEL_INSNS > 1
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? (MAX_PARALLEL_INSNS * 2)
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: 0));
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/* Account for before/after handlers. */
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if (! FAST_P)
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slice_insns *= 3;
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if (slice_insns > 0
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&& slice_insns < max_insns)
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max_insns = slice_insns;
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}
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new_vpc = sc;
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/* SC,PC must be updated to point passed the last entry used.
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SET_CTI_VPC must be called if pbb is terminated by a cti.
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SET_INSN_COUNT must be called to record number of real insns in
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pbb [could be computed by us of course, extra cpu but perhaps
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negligible enough]. */
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/* begin extract-pbb */
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{
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const IDESC *idesc;
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int icount = 0;
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while (max_insns > 0)
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{
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UHI insn = GETIMEMUHI (current_cpu, pc);
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idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
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SEM_SKIP_COMPILE (current_cpu, sc, 1);
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++sc;
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--max_insns;
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++icount;
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pc += idesc->length;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (sc - 1);
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if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
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{
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USI insn = GETIMEMUHI (current_cpu, pc);
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idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
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if (IDESC_CTI_P (idesc) ||
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CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_ILLSLOT))
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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sim_io_eprintf (CPU_STATE (current_cpu),
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"malformed program, `%s' insn in delay slot\n",
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CGEN_INSN_NAME (idesc->idata));
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sim_engine_halt (sd, current_cpu, NULL, pc,
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sim_stopped, SIM_SIGILL);
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}
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else
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{
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++sc;
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--max_insns;
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++icount;
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pc += idesc->length;
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}
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}
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break;
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}
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}
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Finish:
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SET_INSN_COUNT (icount);
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}
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/* end extract-pbb */
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/* The last one is a pseudo-insn to link to the next chain.
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It is also used to record the insn count for this chain. */
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{
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const IDESC *id;
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/* Was pbb terminated by a cti? */
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if (_cti_sc)
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{
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id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_CTI_CHAIN];
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}
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else
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{
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id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_CHAIN];
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}
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SEM_SET_CODE (&sc->argbuf, id, FAST_P);
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sc->argbuf.idesc = id;
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sc->argbuf.addr = pc;
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sc->argbuf.fields.chain.insn_count = _insn_count;
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sc->argbuf.fields.chain.next = 0;
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sc->argbuf.fields.chain.branch_target = 0;
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++sc;
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}
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/* Update the pointer to the next free entry, may not have used as
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many entries as was asked for. */
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CPU_SCACHE_NEXT_FREE (current_cpu) = sc;
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/* Record length of chain if profiling.
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This includes virtual insns since they count against
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max_insns too. */
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if (! FAST_P)
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PROFILE_COUNT_SCACHE_CHAIN_LENGTH (current_cpu, sc - orig_sc);
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}
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return new_vpc;
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}
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/* Chain to the next block from a non-cti terminated previous block. */
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INLINE SEM_PC
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sh64_compact_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
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{
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ARGBUF *abuf = SEM_ARGBUF (sem_arg);
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PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
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SET_H_PC (abuf->addr);
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/* If not running forever, exit back to main loop. */
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if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
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/* Also exit back to main loop if there's an event.
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Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
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at the "right" time, but then that was what was asked for.
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There is no silver bullet for simulator engines.
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??? Clearly this needs a cleaner interface.
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At present it's just so Ctrl-C works. */
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|| STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
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CPU_RUNNING_P (current_cpu) = 0;
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/* If chained to next block, go straight to it. */
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if (abuf->fields.chain.next)
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return abuf->fields.chain.next;
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/* See if next block has already been compiled. */
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abuf->fields.chain.next = scache_lookup (current_cpu, abuf->addr);
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if (abuf->fields.chain.next)
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return abuf->fields.chain.next;
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/* Nope, so next insn is a virtual insn to invoke the compiler
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(begin a pbb). */
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return CPU_SCACHE_PBB_BEGIN (current_cpu);
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}
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|
|
/* Chain to the next block from a cti terminated previous block.
|
||
|
|
BR_TYPE indicates whether the branch was taken and whether we can cache
|
||
|
|
the vpc of the branch target.
|
||
|
|
NEW_PC is the target's branch address, and is only valid if
|
||
|
|
BR_TYPE != SEM_BRANCH_UNTAKEN. */
|
||
|
|
|
||
|
|
INLINE SEM_PC
|
||
|
|
sh64_compact_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
|
||
|
|
SEM_BRANCH_TYPE br_type, PCADDR new_pc)
|
||
|
|
{
|
||
|
|
SEM_PC *new_vpc_ptr;
|
||
|
|
|
||
|
|
PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
|
||
|
|
|
||
|
|
/* If we have switched ISAs, exit back to main loop.
|
||
|
|
Set idesc to 0 to cause the engine to point to the right insn table. */
|
||
|
|
if (new_pc & 1)
|
||
|
|
{
|
||
|
|
/* Switch to SHmedia. */
|
||
|
|
CPU_IDESC_SEM_INIT_P (current_cpu) = 0;
|
||
|
|
CPU_RUNNING_P (current_cpu) = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If not running forever, exit back to main loop. */
|
||
|
|
if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
|
||
|
|
/* Also exit back to main loop if there's an event.
|
||
|
|
Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
|
||
|
|
at the "right" time, but then that was what was asked for.
|
||
|
|
There is no silver bullet for simulator engines.
|
||
|
|
??? Clearly this needs a cleaner interface.
|
||
|
|
At present it's just so Ctrl-C works. */
|
||
|
|
|| STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
|
||
|
|
CPU_RUNNING_P (current_cpu) = 0;
|
||
|
|
|
||
|
|
/* Restart compiler if we branched to an uncacheable address
|
||
|
|
(e.g. "j reg"). */
|
||
|
|
if (br_type == SEM_BRANCH_UNCACHEABLE)
|
||
|
|
{
|
||
|
|
SET_H_PC (new_pc);
|
||
|
|
return CPU_SCACHE_PBB_BEGIN (current_cpu);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If branch wasn't taken, update the pc and set BR_ADDR_PTR to our
|
||
|
|
next chain ptr. */
|
||
|
|
if (br_type == SEM_BRANCH_UNTAKEN)
|
||
|
|
{
|
||
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||
|
|
new_pc = abuf->addr;
|
||
|
|
SET_H_PC (new_pc);
|
||
|
|
new_vpc_ptr = &abuf->fields.chain.next;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||
|
|
SET_H_PC (new_pc);
|
||
|
|
new_vpc_ptr = &abuf->fields.chain.branch_target;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If chained to next block, go straight to it. */
|
||
|
|
if (*new_vpc_ptr)
|
||
|
|
return *new_vpc_ptr;
|
||
|
|
/* See if next block has already been compiled. */
|
||
|
|
*new_vpc_ptr = scache_lookup (current_cpu, new_pc);
|
||
|
|
if (*new_vpc_ptr)
|
||
|
|
return *new_vpc_ptr;
|
||
|
|
/* Nope, so next insn is a virtual insn to invoke the compiler
|
||
|
|
(begin a pbb). */
|
||
|
|
return CPU_SCACHE_PBB_BEGIN (current_cpu);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* x-before handler.
|
||
|
|
This is called before each insn. */
|
||
|
|
|
||
|
|
void
|
||
|
|
sh64_compact_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
|
||
|
|
{
|
||
|
|
SEM_ARG sem_arg = sc;
|
||
|
|
const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||
|
|
int first_p = abuf->fields.before.first_p;
|
||
|
|
const ARGBUF *cur_abuf = SEM_ARGBUF (sc + 1);
|
||
|
|
const IDESC *cur_idesc = cur_abuf->idesc;
|
||
|
|
PCADDR pc = cur_abuf->addr;
|
||
|
|
|
||
|
|
if (ARGBUF_PROFILE_P (cur_abuf))
|
||
|
|
PROFILE_COUNT_INSN (current_cpu, pc, cur_idesc->num);
|
||
|
|
|
||
|
|
/* If this isn't the first insn, finish up the previous one. */
|
||
|
|
|
||
|
|
if (! first_p)
|
||
|
|
{
|
||
|
|
if (PROFILE_MODEL_P (current_cpu))
|
||
|
|
{
|
||
|
|
const SEM_ARG prev_sem_arg = sc - 1;
|
||
|
|
const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
|
||
|
|
const IDESC *prev_idesc = prev_abuf->idesc;
|
||
|
|
int cycles;
|
||
|
|
|
||
|
|
/* ??? May want to measure all insns if doing insn tracing. */
|
||
|
|
if (ARGBUF_PROFILE_P (prev_abuf))
|
||
|
|
{
|
||
|
|
cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
|
||
|
|
sh64_compact_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
|
||
|
|
if (PROFILE_MODEL_P (current_cpu)
|
||
|
|
&& ARGBUF_PROFILE_P (cur_abuf))
|
||
|
|
sh64_compact_model_insn_before (current_cpu, first_p);
|
||
|
|
|
||
|
|
TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
|
||
|
|
TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* x-after handler.
|
||
|
|
This is called after a serial insn or at the end of a group of parallel
|
||
|
|
insns. */
|
||
|
|
|
||
|
|
void
|
||
|
|
sh64_compact_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
|
||
|
|
{
|
||
|
|
SEM_ARG sem_arg = sc;
|
||
|
|
const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||
|
|
const SEM_ARG prev_sem_arg = sc - 1;
|
||
|
|
const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
|
||
|
|
|
||
|
|
/* ??? May want to measure all insns if doing insn tracing. */
|
||
|
|
if (PROFILE_MODEL_P (current_cpu)
|
||
|
|
&& ARGBUF_PROFILE_P (prev_abuf))
|
||
|
|
{
|
||
|
|
const IDESC *prev_idesc = prev_abuf->idesc;
|
||
|
|
int cycles;
|
||
|
|
|
||
|
|
cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
|
||
|
|
sh64_compact_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
|
||
|
|
}
|
||
|
|
TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define FAST_P 0
|
||
|
|
|
||
|
|
void
|
||
|
|
sh64_compact_engine_run_full (SIM_CPU *current_cpu)
|
||
|
|
{
|
||
|
|
SIM_DESC current_state = CPU_STATE (current_cpu);
|
||
|
|
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
|
||
|
|
/* virtual program counter */
|
||
|
|
SEM_PC vpc;
|
||
|
|
#if WITH_SEM_SWITCH_FULL
|
||
|
|
/* For communication between cti's and cti-chain. */
|
||
|
|
SEM_BRANCH_TYPE pbb_br_type;
|
||
|
|
PCADDR pbb_br_npc;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
if (! CPU_IDESC_SEM_INIT_P (current_cpu))
|
||
|
|
{
|
||
|
|
/* ??? 'twould be nice to move this up a level and only call it once.
|
||
|
|
On the other hand, in the "let's go fast" case the test is only done
|
||
|
|
once per pbb (since we only return to the main loop at the end of
|
||
|
|
a pbb). And in the "let's run until we're done" case we don't return
|
||
|
|
until the program exits. */
|
||
|
|
|
||
|
|
#if WITH_SEM_SWITCH_FULL
|
||
|
|
#if defined (__GNUC__)
|
||
|
|
/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
|
||
|
|
#define DEFINE_LABELS
|
||
|
|
#include "sem-compact-switch.c"
|
||
|
|
#endif
|
||
|
|
#else
|
||
|
|
sh64_compact_sem_init_idesc_table (current_cpu);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Initialize the "begin (compile) a pbb" virtual insn. */
|
||
|
|
vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
|
||
|
|
SEM_SET_FULL_CODE (SEM_ARGBUF (vpc),
|
||
|
|
& CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN]);
|
||
|
|
vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN];
|
||
|
|
|
||
|
|
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
CPU_RUNNING_P (current_cpu) = 1;
|
||
|
|
/* ??? In the case where we're returning to the main loop after every
|
||
|
|
pbb we don't want to call pbb_begin each time (which hashes on the pc
|
||
|
|
and does a table lookup). A way to speed this up is to save vpc
|
||
|
|
between calls. */
|
||
|
|
vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
|
||
|
|
|
||
|
|
do
|
||
|
|
{
|
||
|
|
/* begin full-exec-pbb */
|
||
|
|
{
|
||
|
|
#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
|
||
|
|
#define DEFINE_SWITCH
|
||
|
|
#include "sem-compact-switch.c"
|
||
|
|
#else
|
||
|
|
vpc = execute (current_cpu, vpc, FAST_P);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
/* end full-exec-pbb */
|
||
|
|
}
|
||
|
|
while (CPU_RUNNING_P (current_cpu));
|
||
|
|
}
|
||
|
|
|
||
|
|
#undef FAST_P
|
||
|
|
|
||
|
|
|
||
|
|
#define FAST_P 1
|
||
|
|
|
||
|
|
void
|
||
|
|
sh64_compact_engine_run_fast (SIM_CPU *current_cpu)
|
||
|
|
{
|
||
|
|
SIM_DESC current_state = CPU_STATE (current_cpu);
|
||
|
|
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
|
||
|
|
/* virtual program counter */
|
||
|
|
SEM_PC vpc;
|
||
|
|
#if WITH_SEM_SWITCH_FAST
|
||
|
|
/* For communication between cti's and cti-chain. */
|
||
|
|
SEM_BRANCH_TYPE pbb_br_type;
|
||
|
|
PCADDR pbb_br_npc;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
if (! CPU_IDESC_SEM_INIT_P (current_cpu))
|
||
|
|
{
|
||
|
|
/* ??? 'twould be nice to move this up a level and only call it once.
|
||
|
|
On the other hand, in the "let's go fast" case the test is only done
|
||
|
|
once per pbb (since we only return to the main loop at the end of
|
||
|
|
a pbb). And in the "let's run until we're done" case we don't return
|
||
|
|
until the program exits. */
|
||
|
|
|
||
|
|
#if WITH_SEM_SWITCH_FAST
|
||
|
|
#if defined (__GNUC__)
|
||
|
|
/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
|
||
|
|
#define DEFINE_LABELS
|
||
|
|
#include "sem-compact-switch.c"
|
||
|
|
#endif
|
||
|
|
#else
|
||
|
|
sh64_compact_semf_init_idesc_table (current_cpu);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Initialize the "begin (compile) a pbb" virtual insn. */
|
||
|
|
vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
|
||
|
|
SEM_SET_FAST_CODE (SEM_ARGBUF (vpc),
|
||
|
|
& CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN]);
|
||
|
|
vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN];
|
||
|
|
|
||
|
|
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
CPU_RUNNING_P (current_cpu) = 1;
|
||
|
|
/* ??? In the case where we're returning to the main loop after every
|
||
|
|
pbb we don't want to call pbb_begin each time (which hashes on the pc
|
||
|
|
and does a table lookup). A way to speed this up is to save vpc
|
||
|
|
between calls. */
|
||
|
|
vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
|
||
|
|
|
||
|
|
do
|
||
|
|
{
|
||
|
|
/* begin fast-exec-pbb */
|
||
|
|
{
|
||
|
|
#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
|
||
|
|
#define DEFINE_SWITCH
|
||
|
|
#include "sem-compact-switch.c"
|
||
|
|
#else
|
||
|
|
vpc = execute (current_cpu, vpc, FAST_P);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
/* end fast-exec-pbb */
|
||
|
|
}
|
||
|
|
while (CPU_RUNNING_P (current_cpu));
|
||
|
|
}
|
||
|
|
|
||
|
|
#undef FAST_P
|
||
|
|
|