525 lines
9.0 KiB
ArmAsm
525 lines
9.0 KiB
ArmAsm
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.globl _main
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.globl call_tests
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.globl movm_tests
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.globl misc_tests
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.globl mov_tests
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.globl ext_tests
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.globl add_tests
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.globl sub_tests
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.globl cmp_tests
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.globl logical_tests
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.globl shift_tests
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.globl muldiv_tests
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.globl movbu_tests
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.globl movhu_tests
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.globl mac_tests
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.globl bit_tests
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.globl dsp_add_tests
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.globl dsp_cmp_tests
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.globl dsp_sub_tests
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.globl dsp_mov_tests
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.globl dsp_logical_tests
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.globl dsp_misc_tests
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.globl autoincrement_tests
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.globl dsp_autoincrement_tests
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.text
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.am33
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_main:
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call_tests:
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call 256,[a2,a3,exreg0],9
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call 256,[a2,a3,exreg1],9
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call 256,[a2,a3,exother],9
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call 256,[a2,a3,all],9
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call 131071,[a2,a3,exreg0],9
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call 131071,[a2,a3,exreg1],9
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call 131071,[a2,a3,exother],9
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call 131071,[a2,a3,all],9
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movm_tests:
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movm (sp),[a2,a3,exreg0]
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movm (sp),[a2,a3,exreg1]
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movm (sp),[a2,a3,exother]
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movm (sp),[a2,a3,all]
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movm [a2,a3,exreg0],(sp)
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movm [a2,a3,exreg1],(sp)
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movm [a2,a3,exother],(sp)
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movm [a2,a3,all],(sp)
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movm (usp),[a2,a3,exreg0]
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movm (usp),[a2,a3,exreg1]
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movm (usp),[a2,a3,exother]
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movm (usp),[a2,a3,all]
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movm [a2,a3,exreg0],(usp)
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movm [a2,a3,exreg1],(usp)
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movm [a2,a3,exother],(usp)
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movm [a2,a3,all],(usp)
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misc_tests:
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syscall 0x4
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mcst9 d0
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mcst48 d1
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getchx d0
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getclx d1
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clr r9
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sat16 r9,r8
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mcste r7,r6
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swap r5,r4
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swaph r3,r2
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swhw r1,r0
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mov_tests:
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mov r0,r1
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mov xr0, r1
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mov r1, xr2
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mov (r1),r2
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mov r3,(r4)
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mov (sp),r5
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mov r6,(sp)
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mov 16,r1
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mov 16,xr1
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mov (16,r1),r2
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mov r2,(16,r1)
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mov (16,sp),r2
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mov r2,(16,sp)
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mov 0x1ffeff,r2
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mov 0x1ffeff,xr2
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mov (0x1ffeff,r1),r2
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mov r2,(0x1ffeff,r1)
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mov (0x1ffeff,sp),r2
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mov r2,(0x1ffeff,sp)
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mov (0x1ffeff),r2
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mov r2,(0x1ffeff)
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mov 0x7ffefdfc,r2
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mov 0x7ffefdfc,xr2
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mov (0x7ffefdfc,r1),r2
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mov r2,(0x7ffefdfc,r1)
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mov (0x7ffefdfc,sp),r2
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mov r2,(0x7ffefdfc,sp)
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mov (0x7ffefdfc),r2
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mov r2,(0x7ffefdfc)
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movu 16,r1
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movu 0x1ffeff,r2
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movu 0x7ffefdfc,r2
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mov usp,a0
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mov ssp,a1
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mov msp,a2
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mov pc,a3
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mov a0,usp
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mov a1,ssp
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mov a2,msp
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mov epsw,d0
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mov d1,epsw
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mov a0,r1
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mov d2,r3
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mov r5,a1
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mov r7,d3
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ext_tests:
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ext r2
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extb r3,r4
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extbu r4,r5
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exth r6,r7
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exthu r7,r8
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add_tests:
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add r10,r11
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add 16,r1
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add 0x1ffeff,r2
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add 0x7ffefdfc,r2
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add r1,r2,r3
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addc r12,r13
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addc 16,r1
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addc 0x1ffeff,r2
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addc 0x7ffefdfc,r2
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inc r13
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inc4 r12
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sub_tests:
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sub r14,r15
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sub 16,r1
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sub 0x1ffeff,r2
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sub 0x7ffefdfc,r2
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subc r15,r14
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subc 16,r1
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subc 0x1ffeff,r2
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subc 0x7ffefdfc,r2
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cmp_tests:
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cmp r11,r10
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cmp 16,r1
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cmp 0x1ffeff,r2
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cmp 0x7ffefdfc,r2
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logical_tests:
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and r0,r1
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or r2,r3
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xor r4,r5
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not r6
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and 16,r1
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or 16,r1
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xor 16,r1
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and 0x1ffeff,r2
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or 0x1ffeff,r2
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xor 0x1ffeff,r2
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and 0x7ffefdfc,r2
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or 0x7ffefdfc,r2
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xor 0x7ffefdfc,r2
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and 131072,epsw
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or 65535,epsw
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shift_tests:
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asr r7,r8
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lsr r9,r10
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asl r11,r12
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asl2 r13
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ror r14
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rol r15
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asr 16,r1
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lsr 16,r1
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asl 16,r1
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asr 0x1ffeff,r2
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lsr 0x1ffeff,r2
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asl 0x1ffeff,r2
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asr 0x7ffefdfc,r2
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lsr 0x7ffefdfc,r2
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asl 0x7ffefdfc,r2
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muldiv_tests:
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mul r1,r2
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mulu r3,r4
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mul 16,r1
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mulu 16,r1
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mul 0x1ffeff,r2
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mulu 0x1ffeff,r2
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mul 0x7ffefdfc,r2
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mulu 0x7ffefdfc,r2
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div r5,r6
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divu r7,r8
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dmulh r13,r12
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dmulhu r11,r10
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dmulh 0x7ffefdfc,r2
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dmulhu 0x7ffefdfc,r2
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mul r1,r2,r3,r4
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mulu r1,r2,r3,r4
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movbu_tests:
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movbu (r5),r6
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movbu r7,(r8)
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movbu (sp),r7
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movbu r8,(sp)
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movbu (16,r1),r2
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movbu r2,(16,r1)
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movbu (16,sp),r2
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movbu r2,(16,sp)
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movbu (0x1ffeff,r1),r2
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movbu r2,(0x1ffeff,r1)
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movbu (0x1ffeff,sp),r2
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movbu r2,(0x1ffeff,sp)
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movbu (0x1ffeff),r2
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movbu r2,(0x1ffeff)
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movbu (0x7ffefdfc,r1),r2
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movbu r2,(0x7ffefdfc,r1)
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movbu (0x7ffefdfc,sp),r2
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movbu r2,(0x7ffefdfc,sp)
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movbu (0x7ffefdfc),r2
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movbu r2,(0x7ffefdfc)
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movhu_tests:
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movhu (r9),r10
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movhu r11,(r12)
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movhu (sp),r9
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movhu r10,(sp)
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movhu (16,r1),r2
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movhu r2,(16,r1)
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movhu (16,sp),r2
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movhu r2,(16,sp)
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movhu (0x1ffeff,r1),r2
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movhu r2,(0x1ffeff,r1)
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movhu (0x1ffeff,sp),r2
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movhu r2,(0x1ffeff,sp)
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movhu (0x1ffeff),r2
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movhu r2,(0x1ffeff)
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movhu (0x7ffefdfc,r1),r2
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movhu r2,(0x7ffefdfc,r1)
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movhu (0x7ffefdfc,sp),r2
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movhu r2,(0x7ffefdfc,sp)
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movhu (0x7ffefdfc),r2
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movhu r2,(0x7ffefdfc)
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mac_tests:
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mac r1,r2
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macu r3,r4
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macb r5,r6
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macbu r7,r8
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mach r9,r10
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machu r11,r12
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dmach r13,r14
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dmachu r15,r14
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mac 16,r1
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macu 16,r1
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macb 16,r1
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macbu 16,r1
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mach 16,r1
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machu 16,r1
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mac 0x1ffeff,r2
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macu 0x1ffeff,r2
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macb 0x1ffeff,r2
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macbu 0x1ffeff,r2
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mach 0x1ffeff,r2
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machu 0x1ffeff,r2
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mac 0x7ffefdfc,r2
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macu 0x7ffefdfc,r2
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macb 0x7ffefdfc,r2
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macbu 0x7ffefdfc,r2
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mach 0x7ffefdfc,r2
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machu 0x7ffefdfc,r2
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dmach 0x7ffefdfc,r2
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dmachu 0x7ffefdfc,r2
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bit_tests:
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bsch r1,r2
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btst 16,r1
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btst 0x1ffeff,r2
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btst 0x7ffefdfc,r2
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dsp_add_tests:
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add_add r4,r1,r2,r3
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add_add r4,r1,2,r3
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add_sub r4,r1,r2,r3
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add_sub r4,r1,2,r3
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add_cmp r4,r1,r2,r3
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add_cmp r4,r1,2,r3
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add_mov r4,r1,r2,r3
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add_mov r4,r1,2,r3
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add_asr r4,r1,r2,r3
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add_asr r4,r1,2,r3
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add_lsr r4,r1,r2,r3
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add_lsr r4,r1,2,r3
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add_asl r4,r1,r2,r3
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add_asl r4,r1,2,r3
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add_add 4,r1,r2,r3
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add_add 4,r1,2,r3
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add_sub 4,r1,r2,r3
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add_sub 4,r1,2,r3
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add_cmp 4,r1,r2,r3
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add_cmp 4,r1,2,r3
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add_mov 4,r1,r2,r3
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add_mov 4,r1,2,r3
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add_asr 4,r1,r2,r3
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add_asr 4,r1,2,r3
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add_lsr 4,r1,r2,r3
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add_lsr 4,r1,2,r3
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add_asl 4,r1,r2,r3
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add_asl 4,r1,2,r3
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dsp_cmp_tests:
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cmp_add r4,r1,r2,r3
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cmp_add r4,r1,2,r3
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cmp_sub r4,r1,r2,r3
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cmp_sub r4,r1,2,r3
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cmp_mov r4,r1,r2,r3
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cmp_mov r4,r1,2,r3
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cmp_asr r4,r1,r2,r3
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cmp_asr r4,r1,2,r3
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cmp_lsr r4,r1,r2,r3
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cmp_lsr r4,r1,2,r3
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cmp_asl r4,r1,r2,r3
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cmp_asl r4,r1,2,r3
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cmp_add 4,r1,r2,r3
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cmp_add 4,r1,2,r3
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cmp_sub 4,r1,r2,r3
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cmp_sub 4,r1,2,r3
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cmp_mov 4,r1,r2,r3
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cmp_mov 4,r1,2,r3
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cmp_asr 4,r1,r2,r3
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cmp_asr 4,r1,2,r3
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cmp_lsr 4,r1,r2,r3
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cmp_lsr 4,r1,2,r3
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cmp_asl 4,r1,r2,r3
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cmp_asl 4,r1,2,r3
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dsp_sub_tests:
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sub_add r4,r1,r2,r3
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sub_add r4,r1,2,r3
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sub_sub r4,r1,r2,r3
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sub_sub r4,r1,2,r3
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sub_cmp r4,r1,r2,r3
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sub_cmp r4,r1,2,r3
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sub_mov r4,r1,r2,r3
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sub_mov r4,r1,2,r3
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sub_asr r4,r1,r2,r3
|
||
|
|
sub_asr r4,r1,2,r3
|
||
|
|
sub_lsr r4,r1,r2,r3
|
||
|
|
sub_lsr r4,r1,2,r3
|
||
|
|
sub_asl r4,r1,r2,r3
|
||
|
|
sub_asl r4,r1,2,r3
|
||
|
|
sub_add 4,r1,r2,r3
|
||
|
|
sub_add 4,r1,2,r3
|
||
|
|
sub_sub 4,r1,r2,r3
|
||
|
|
sub_sub 4,r1,2,r3
|
||
|
|
sub_cmp 4,r1,r2,r3
|
||
|
|
sub_cmp 4,r1,2,r3
|
||
|
|
sub_mov 4,r1,r2,r3
|
||
|
|
sub_mov 4,r1,2,r3
|
||
|
|
sub_asr 4,r1,r2,r3
|
||
|
|
sub_asr 4,r1,2,r3
|
||
|
|
sub_lsr 4,r1,r2,r3
|
||
|
|
sub_lsr 4,r1,2,r3
|
||
|
|
sub_asl 4,r1,r2,r3
|
||
|
|
sub_asl 4,r1,2,r3
|
||
|
|
|
||
|
|
dsp_mov_tests:
|
||
|
|
mov_add r4,r1,r2,r3
|
||
|
|
mov_add r4,r1,2,r3
|
||
|
|
mov_sub r4,r1,r2,r3
|
||
|
|
mov_sub r4,r1,2,r3
|
||
|
|
mov_cmp r4,r1,r2,r3
|
||
|
|
mov_cmp r4,r1,2,r3
|
||
|
|
mov_mov r4,r1,r2,r3
|
||
|
|
mov_mov r4,r1,2,r3
|
||
|
|
mov_asr r4,r1,r2,r3
|
||
|
|
mov_asr r4,r1,2,r3
|
||
|
|
mov_lsr r4,r1,r2,r3
|
||
|
|
mov_lsr r4,r1,2,r3
|
||
|
|
mov_asl r4,r1,r2,r3
|
||
|
|
mov_asl r4,r1,2,r3
|
||
|
|
mov_add 4,r1,r2,r3
|
||
|
|
mov_add 4,r1,2,r3
|
||
|
|
mov_sub 4,r1,r2,r3
|
||
|
|
mov_sub 4,r1,2,r3
|
||
|
|
mov_cmp 4,r1,r2,r3
|
||
|
|
mov_cmp 4,r1,2,r3
|
||
|
|
mov_mov 4,r1,r2,r3
|
||
|
|
mov_mov 4,r1,2,r3
|
||
|
|
mov_asr 4,r1,r2,r3
|
||
|
|
mov_asr 4,r1,2,r3
|
||
|
|
mov_lsr 4,r1,r2,r3
|
||
|
|
mov_lsr 4,r1,2,r3
|
||
|
|
mov_asl 4,r1,r2,r3
|
||
|
|
mov_asl 4,r1,2,r3
|
||
|
|
|
||
|
|
dsp_logical_tests:
|
||
|
|
and_add r4,r1,r2,r3
|
||
|
|
and_add r4,r1,2,r3
|
||
|
|
and_sub r4,r1,r2,r3
|
||
|
|
and_sub r4,r1,2,r3
|
||
|
|
and_cmp r4,r1,r2,r3
|
||
|
|
and_cmp r4,r1,2,r3
|
||
|
|
and_mov r4,r1,r2,r3
|
||
|
|
and_mov r4,r1,2,r3
|
||
|
|
and_asr r4,r1,r2,r3
|
||
|
|
and_asr r4,r1,2,r3
|
||
|
|
and_lsr r4,r1,r2,r3
|
||
|
|
and_lsr r4,r1,2,r3
|
||
|
|
and_asl r4,r1,r2,r3
|
||
|
|
and_asl r4,r1,2,r3
|
||
|
|
xor_add r4,r1,r2,r3
|
||
|
|
xor_add r4,r1,2,r3
|
||
|
|
xor_sub r4,r1,r2,r3
|
||
|
|
xor_sub r4,r1,2,r3
|
||
|
|
xor_cmp r4,r1,r2,r3
|
||
|
|
xor_cmp r4,r1,2,r3
|
||
|
|
xor_mov r4,r1,r2,r3
|
||
|
|
xor_mov r4,r1,2,r3
|
||
|
|
xor_asr r4,r1,r2,r3
|
||
|
|
xor_asr r4,r1,2,r3
|
||
|
|
xor_lsr r4,r1,r2,r3
|
||
|
|
xor_lsr r4,r1,2,r3
|
||
|
|
xor_asl r4,r1,r2,r3
|
||
|
|
xor_asl r4,r1,2,r3
|
||
|
|
or_add r4,r1,r2,r3
|
||
|
|
or_add r4,r1,2,r3
|
||
|
|
or_sub r4,r1,r2,r3
|
||
|
|
or_sub r4,r1,2,r3
|
||
|
|
or_cmp r4,r1,r2,r3
|
||
|
|
or_cmp r4,r1,2,r3
|
||
|
|
or_mov r4,r1,r2,r3
|
||
|
|
or_mov r4,r1,2,r3
|
||
|
|
or_asr r4,r1,r2,r3
|
||
|
|
or_asr r4,r1,2,r3
|
||
|
|
or_lsr r4,r1,r2,r3
|
||
|
|
or_lsr r4,r1,2,r3
|
||
|
|
or_asl r4,r1,r2,r3
|
||
|
|
or_asl r4,r1,2,r3
|
||
|
|
|
||
|
|
dsp_misc_tests:
|
||
|
|
dmach_add r4,r1,r2,r3
|
||
|
|
dmach_add r4,r1,2,r3
|
||
|
|
dmach_sub r4,r1,r2,r3
|
||
|
|
dmach_sub r4,r1,2,r3
|
||
|
|
dmach_cmp r4,r1,r2,r3
|
||
|
|
dmach_cmp r4,r1,2,r3
|
||
|
|
dmach_mov r4,r1,r2,r3
|
||
|
|
dmach_mov r4,r1,2,r3
|
||
|
|
dmach_asr r4,r1,r2,r3
|
||
|
|
dmach_asr r4,r1,2,r3
|
||
|
|
dmach_lsr r4,r1,r2,r3
|
||
|
|
dmach_lsr r4,r1,2,r3
|
||
|
|
dmach_asl r4,r1,r2,r3
|
||
|
|
dmach_asl r4,r1,2,r3
|
||
|
|
swhw_add r4,r1,r2,r3
|
||
|
|
swhw_add r4,r1,2,r3
|
||
|
|
swhw_sub r4,r1,r2,r3
|
||
|
|
swhw_sub r4,r1,2,r3
|
||
|
|
swhw_cmp r4,r1,r2,r3
|
||
|
|
swhw_cmp r4,r1,2,r3
|
||
|
|
swhw_mov r4,r1,r2,r3
|
||
|
|
swhw_mov r4,r1,2,r3
|
||
|
|
swhw_asr r4,r1,r2,r3
|
||
|
|
swhw_asr r4,r1,2,r3
|
||
|
|
swhw_lsr r4,r1,r2,r3
|
||
|
|
swhw_lsr r4,r1,2,r3
|
||
|
|
swhw_asl r4,r1,r2,r3
|
||
|
|
swhw_asl r4,r1,2,r3
|
||
|
|
sat16_add r4,r1,r2,r3
|
||
|
|
sat16_add r4,r1,2,r3
|
||
|
|
sat16_sub r4,r1,r2,r3
|
||
|
|
sat16_sub r4,r1,2,r3
|
||
|
|
sat16_cmp r4,r1,r2,r3
|
||
|
|
sat16_cmp r4,r1,2,r3
|
||
|
|
sat16_mov r4,r1,r2,r3
|
||
|
|
sat16_mov r4,r1,2,r3
|
||
|
|
sat16_asr r4,r1,r2,r3
|
||
|
|
sat16_asr r4,r1,2,r3
|
||
|
|
sat16_lsr r4,r1,r2,r3
|
||
|
|
sat16_lsr r4,r1,2,r3
|
||
|
|
sat16_asl r4,r1,r2,r3
|
||
|
|
sat16_asl r4,r1,2,r3
|
||
|
|
|
||
|
|
autoincrement_tests:
|
||
|
|
mov (r1+),r2
|
||
|
|
mov r3,(r4+)
|
||
|
|
movhu (r6+),r7
|
||
|
|
movhu r8,(r9+)
|
||
|
|
mov (r1+,64),r2
|
||
|
|
mov r1,(r2+,64)
|
||
|
|
movhu (r1+,64),r2
|
||
|
|
movhu r1,(r2+,64)
|
||
|
|
mov (r1+,0x1ffef),r2
|
||
|
|
mov r1,(r2+,0x1ffef)
|
||
|
|
movhu (r1+,0x1ffef),r2
|
||
|
|
movhu r1,(r2+,0x1ffef)
|
||
|
|
mov (r1+,0x7ffefdfc),r2
|
||
|
|
mov r1,(r2+,0x7ffefdfc)
|
||
|
|
movhu (r1+,0x7ffefdfc),r2
|
||
|
|
movhu r1,(r2+,0x7ffefdfc)
|
||
|
|
|
||
|
|
dsp_autoincrement_tests:
|
||
|
|
mov_llt (r1+,4),r2
|
||
|
|
mov_lgt (r1+,4),r2
|
||
|
|
mov_lge (r1+,4),r2
|
||
|
|
mov_lle (r1+,4),r2
|
||
|
|
mov_lcs (r1+,4),r2
|
||
|
|
mov_lhi (r1+,4),r2
|
||
|
|
mov_lcc (r1+,4),r2
|
||
|
|
mov_lls (r1+,4),r2
|
||
|
|
mov_leq (r1+,4),r2
|
||
|
|
mov_lne (r1+,4),r2
|
||
|
|
mov_lra (r1+,4),r2
|