2018-11-02 18:37:29 +01:00
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/* Ravenscar Aarch64 target support.
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2019-01-01 07:01:51 +01:00
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Copyright (C) 2017-2019 Free Software Foundation, Inc.
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2018-11-02 18:37:29 +01:00
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "gdbcore.h"
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#include "regcache.h"
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#include "aarch64-tdep.h"
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#include "inferior.h"
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#include "ravenscar-thread.h"
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#include "aarch64-ravenscar-thread.h"
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#define NO_OFFSET -1
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/* See aarch64-tdep.h for register numbers. */
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static const int aarch64_context_offsets[] =
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{
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/* X0 - X28 */
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, 0,
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8, 16, 24, 32,
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40, 48, 56, 64,
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72,
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/* FP, LR, SP, PC, CPSR */
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/* Note that as task switch is synchronous, PC is in fact the LR here */
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80, 88, 96, 88,
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NO_OFFSET,
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/* Q0 - Q31 */
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112, 128, 144, 160,
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176, 192, 208, 224,
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240, 256, 272, 288,
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304, 320, 336, 352,
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368, 384, 400, 416,
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432, 448, 464, 480,
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496, 512, 528, 544,
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560, 576, 592, 608,
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/* FPSR, FPCR */
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104, 108,
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/* FPU Saved field */
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624
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};
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/* The register layout info. */
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struct ravenscar_reg_info
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{
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/* A table providing the offset relative to the context structure
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where each register is saved. */
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const int *context_offsets;
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/* The number of elements in the context_offsets table above. */
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int context_offsets_size;
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};
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/* supply register REGNUM, which has been saved on REGISTER_ADDR, to the
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regcache. */
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static void
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supply_register_at_address (struct regcache *regcache, int regnum,
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CORE_ADDR register_addr)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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int buf_size = register_size (gdbarch, regnum);
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gdb_byte *buf;
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buf = (gdb_byte *) alloca (buf_size);
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read_memory (register_addr, buf, buf_size);
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regcache->raw_supply (regnum, buf);
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}
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/* Return true if, for a non-running thread, REGNUM has been saved on the
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Thread_Descriptor. */
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static int
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register_in_thread_descriptor_p (const struct ravenscar_reg_info *reg_info,
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int regnum)
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{
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/* Check FPU registers */
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return (regnum < reg_info->context_offsets_size
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&& reg_info->context_offsets[regnum] != NO_OFFSET);
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}
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/* to_fetch_registers when inferior_ptid is different from the running
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thread. */
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static void
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aarch64_ravenscar_generic_fetch_registers
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(const struct ravenscar_reg_info *reg_info,
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struct regcache *regcache, int regnum)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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const int num_regs = gdbarch_num_regs (gdbarch);
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int current_regnum;
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CORE_ADDR current_address;
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CORE_ADDR thread_descriptor_address;
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/* The tid is the thread_id field, which is a pointer to the thread. */
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thread_descriptor_address = (CORE_ADDR) inferior_ptid.tid ();
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/* Read registers. */
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for (current_regnum = 0; current_regnum < num_regs; current_regnum++)
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{
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if (register_in_thread_descriptor_p (reg_info, current_regnum))
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{
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current_address = thread_descriptor_address
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+ reg_info->context_offsets[current_regnum];
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supply_register_at_address (regcache, current_regnum,
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current_address);
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}
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}
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}
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/* to_store_registers when inferior_ptid is different from the running
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thread. */
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static void
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aarch64_ravenscar_generic_store_registers
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(const struct ravenscar_reg_info *reg_info,
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struct regcache *regcache, int regnum)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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int buf_size = register_size (gdbarch, regnum);
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gdb_byte buf[buf_size];
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ULONGEST register_address;
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if (register_in_thread_descriptor_p (reg_info, regnum))
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register_address
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= inferior_ptid.tid () + reg_info->context_offsets [regnum];
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else
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return;
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regcache->raw_collect (regnum, buf);
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write_memory (register_address,
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buf,
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buf_size);
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}
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/* The ravenscar_reg_info for most Aarch64 targets. */
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static const struct ravenscar_reg_info aarch64_reg_info =
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{
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aarch64_context_offsets,
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ARRAY_SIZE (aarch64_context_offsets),
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};
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2019-02-05 11:08:02 +01:00
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struct aarch64_ravenscar_ops : public ravenscar_arch_ops
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2018-11-02 18:37:29 +01:00
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{
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2019-02-05 11:08:02 +01:00
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void fetch_registers (struct regcache *regcache, int regnum) override
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{
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aarch64_ravenscar_generic_fetch_registers
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(&aarch64_reg_info, regcache, regnum);
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}
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void store_registers (struct regcache *regcache, int regnum) override
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{
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aarch64_ravenscar_generic_store_registers
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(&aarch64_reg_info, regcache, regnum);
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}
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};
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2018-11-02 18:37:29 +01:00
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/* The ravenscar_arch_ops vector for most Aarch64 targets. */
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2019-02-05 11:08:02 +01:00
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static struct aarch64_ravenscar_ops aarch64_ravenscar_ops;
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2018-11-02 18:37:29 +01:00
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/* Register aarch64_ravenscar_ops in GDBARCH. */
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void
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register_aarch64_ravenscar_ops (struct gdbarch *gdbarch)
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{
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set_gdbarch_ravenscar_ops (gdbarch, &aarch64_ravenscar_ops);
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}
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