binutils-gdb/gdb/common/common-regcache.h

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/* Cache and manage the values of registers
Copyright (C) 2014-2017 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef COMMON_REGCACHE_H
#define COMMON_REGCACHE_H
/* This header is a stopgap until we have an independent regcache. */
enum register_status
{
/* The register value is not in the cache, and we don't know yet
whether it's available in the target (or traceframe). */
REG_UNKNOWN = 0,
/* The register value is valid and cached. */
REG_VALID = 1,
/* The register value is unavailable. E.g., we're inspecting a
traceframe, and this register wasn't collected. Note that this
is different a different "unavailable" from saying the register
does not exist in the target's architecture --- in that case,
the target should have given us a target description that does
not include the register in the first place. */
REG_UNAVAILABLE = -1
};
/* Return a pointer to the register cache associated with the
thread specified by PTID. This function must be provided by
the client. */
extern struct regcache *get_thread_regcache_for_ptid (ptid_t ptid);
aarch64 multi-arch part 6: HW breakpoint on unaligned address Nowadays, both aarch64 GDB and linux kernel assumes that address for setting breakpoint should be 4-byte aligned. However that is not true after we support multi-arch, because thumb instruction can be at 2-byte aligned address. Patch http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/375141.html to linux kernel is to teach kernel to handle 2-byte aligned address for HW breakpoint, while this patch is to teach aarch64 GDB handle 2-byte aligned address. First of all, we call gdbarch_breakpoint_from_pc to get the instruction length rather than using hard-coded 4. Secondly, in GDBserver, we set length back to 2 if it is 3, because GDB encode 3 in it to indicate it is a 32-bit thumb breakpoint. Then we relax the address alignment check from 4-byte aligned to 2-byte aligned. This patch enables some tests (such as gdb.base/break-idempotent.exp, gdb.base/cond-eval-mode.exp, gdb.base/watchpoint-reuse-slot.exp,) and fixes many fails (such as gdb.base/hbreak2.exp) when the program is compiled in thumb mode on aarch64. Regression tested on aarch64-linux, both native and gdbserver. This is the last patch of multi-arch work. gdb: 2015-10-15 Yao Qi <yao.qi@linaro.org> * aarch64-linux-nat.c (aarch64_linux_insert_hw_breakpoint): Call gdbarch_breakpoint_from_pc to instruction length. (aarch64_linux_remove_hw_breakpoint): Likewise. * common/common-regcache.h (regcache_register_size): Declare. * nat/aarch64-linux-hw-point.c: Include "common-regcache.h". (aarch64_point_is_aligned): Set alignment to 2 for breakpoint if the process is 32bit, otherwise set alignment to 4. (aarch64_handle_breakpoint): Update comments. * regcache.c (regcache_register_size): New function. gdb/gdbserver: 2015-10-15 Yao Qi <yao.qi@linaro.org> * linux-aarch64-low.c (aarch64_insert_point): Set len to 2 if it is 3. (aarch64_remove_point): Likewise. * regcache.c (regcache_register_size): New function.
2015-10-15 16:05:10 +02:00
/* Return the size of register numbered N in REGCACHE. This function
must be provided by the client. */
extern int regcache_register_size (const struct regcache *regcache, int n);
/* Read the PC register. This function must be provided by the
client. */
extern CORE_ADDR regcache_read_pc (struct regcache *regcache);
/* Read a raw register into a unsigned integer. */
extern enum register_status regcache_raw_read_unsigned
(struct regcache *regcache, int regnum, ULONGEST *val);
ULONGEST regcache_raw_get_unsigned (struct regcache *regcache, int regnum);
#endif /* COMMON_REGCACHE_H */