binutils-gdb/gas/testsuite/gas/s390/zarch-z13.d

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S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 12:19:21 +01:00
#name: s390x opcode
#objdump: -dr
.*: +file format .*
Disassembly of section .text:
.* <foo>:
.*: e7 69 bf a0 d0 27 [ ]*lcbb %r6,4000\(%r9,%r11\),13
.*: e7 f6 9f a0 d0 13 [ ]*vgef %v15,4000\(%v6,%r9\),13
.*: e7 f6 9f a0 d0 12 [ ]*vgeg %v15,4000\(%v6,%r9\),13
.*: e7 f0 ff fd 00 44 [ ]*vgbm %v15,65533
.*: e7 f0 00 00 00 44 [ ]*vzero %v15
.*: e7 f0 ff ff 00 44 [ ]*vone %v15
.*: e7 f0 fd fc b0 46 [ ]*vgm %v15,253,252,11
.*: e7 f0 fd fc 00 46 [ ]*vgmb %v15,253,252
.*: e7 f0 fd fc 10 46 [ ]*vgmh %v15,253,252
.*: e7 f0 fd fc 20 46 [ ]*vgmf %v15,253,252
.*: e7 f0 fd fc 30 46 [ ]*vgmg %v15,253,252
.*: e7 f1 00 00 04 56 [ ]*vlr %v15,%v17
.*: e7 f6 9f a0 d0 05 [ ]*vlrep %v15,4000\(%r6,%r9\),13
.*: e7 f6 9f a0 00 05 [ ]*vlrepb %v15,4000\(%r6,%r9\)
.*: e7 f6 9f a0 10 05 [ ]*vlreph %v15,4000\(%r6,%r9\)
.*: e7 f6 9f a0 20 05 [ ]*vlrepf %v15,4000\(%r6,%r9\)
.*: e7 f6 9f a0 30 05 [ ]*vlrepg %v15,4000\(%r6,%r9\)
.*: e7 f6 9f a0 d0 00 [ ]*vleb %v15,4000\(%r6,%r9\),13
.*: e7 f6 9f a0 d0 01 [ ]*vleh %v15,4000\(%r6,%r9\),13
.*: e7 f6 9f a0 d0 03 [ ]*vlef %v15,4000\(%r6,%r9\),13
.*: e7 f6 9f a0 d0 02 [ ]*vleg %v15,4000\(%r6,%r9\),13
.*: e7 f0 80 03 c0 40 [ ]*vleib %v15,-32765,12
.*: e7 f0 80 03 c0 41 [ ]*vleih %v15,-32765,12
.*: e7 f0 80 03 c0 43 [ ]*vleif %v15,-32765,12
.*: e7 f0 80 03 c0 42 [ ]*vleig %v15,-32765,12
.*: e7 6f 9f a0 d0 21 [ ]*vlgv %r6,%v15,4000\(%r9\),13
.*: e7 6f 9f a0 00 21 [ ]*vlgvb %r6,%v15,4000\(%r9\)
.*: e7 6f 9f a0 10 21 [ ]*vlgvh %r6,%v15,4000\(%r9\)
.*: e7 6f 9f a0 20 21 [ ]*vlgvf %r6,%v15,4000\(%r9\)
.*: e7 6f 9f a0 30 21 [ ]*vlgvg %r6,%v15,4000\(%r9\)
.*: e7 f6 9f a0 d0 04 [ ]*vllez %v15,4000\(%r6,%r9\),13
.*: e7 f6 9f a0 00 04 [ ]*vllezb %v15,4000\(%r6,%r9\)
.*: e7 f6 9f a0 10 04 [ ]*vllezh %v15,4000\(%r6,%r9\)
.*: e7 f6 9f a0 20 04 [ ]*vllezf %v15,4000\(%r6,%r9\)
.*: e7 f6 9f a0 30 04 [ ]*vllezg %v15,4000\(%r6,%r9\)
.*: e7 f6 9f a0 d0 07 [ ]*vlbb %v15,4000\(%r6,%r9\),13
.*: e7 f6 9f a0 d0 22 [ ]*vlvg %v15,%r6,4000\(%r9\),13
.*: e7 f6 9f a0 00 22 [ ]*vlvgb %v15,%r6,4000\(%r9\)
.*: e7 f6 9f a0 10 22 [ ]*vlvgh %v15,%r6,4000\(%r9\)
.*: e7 f6 9f a0 20 22 [ ]*vlvgf %v15,%r6,4000\(%r9\)
.*: e7 f6 9f a0 30 22 [ ]*vlvgg %v15,%r6,4000\(%r9\)
.*: e7 f6 90 00 00 62 [ ]*vlvgp %v15,%r6,%r9
.*: e7 f6 9f a0 00 37 [ ]*vll %v15,%r6,4000\(%r9\)
.*: e7 f1 40 00 d6 61 [ ]*vmrh %v15,%v17,%v20,13
.*: e7 f1 40 00 06 61 [ ]*vmrhb %v15,%v17,%v20
.*: e7 f1 40 00 16 61 [ ]*vmrhh %v15,%v17,%v20
.*: e7 f1 40 00 26 61 [ ]*vmrhf %v15,%v17,%v20
.*: e7 f1 40 00 36 61 [ ]*vmrhg %v15,%v17,%v20
.*: e7 f1 40 00 d6 60 [ ]*vmrl %v15,%v17,%v20,13
.*: e7 f1 40 00 06 60 [ ]*vmrlb %v15,%v17,%v20
.*: e7 f1 40 00 16 60 [ ]*vmrlh %v15,%v17,%v20
.*: e7 f1 40 00 26 60 [ ]*vmrlf %v15,%v17,%v20
.*: e7 f1 40 00 36 60 [ ]*vmrlg %v15,%v17,%v20
.*: e7 f1 40 00 d6 94 [ ]*vpk %v15,%v17,%v20,13
.*: e7 f1 40 00 16 94 [ ]*vpkh %v15,%v17,%v20
.*: e7 f1 40 00 26 94 [ ]*vpkf %v15,%v17,%v20
.*: e7 f1 40 00 36 94 [ ]*vpkg %v15,%v17,%v20
.*: e7 f1 40 c0 d6 97 [ ]*vpks %v15,%v17,%v20,13,12
.*: e7 f1 40 00 16 97 [ ]*vpksh %v15,%v17,%v20
.*: e7 f1 40 00 26 97 [ ]*vpksf %v15,%v17,%v20
.*: e7 f1 40 00 36 97 [ ]*vpksg %v15,%v17,%v20
.*: e7 f1 40 10 16 97 [ ]*vpkshs %v15,%v17,%v20
.*: e7 f1 40 10 26 97 [ ]*vpksfs %v15,%v17,%v20
.*: e7 f1 40 10 36 97 [ ]*vpksgs %v15,%v17,%v20
.*: e7 f1 40 c0 d6 95 [ ]*vpkls %v15,%v17,%v20,13,12
.*: e7 f1 40 00 16 95 [ ]*vpklsh %v15,%v17,%v20
.*: e7 f1 40 00 26 95 [ ]*vpklsf %v15,%v17,%v20
.*: e7 f1 40 00 36 95 [ ]*vpklsg %v15,%v17,%v20
.*: e7 f1 40 10 16 95 [ ]*vpklshs %v15,%v17,%v20
.*: e7 f1 40 10 26 95 [ ]*vpklsfs %v15,%v17,%v20
.*: e7 f1 40 10 36 95 [ ]*vpklsgs %v15,%v17,%v20
.*: e7 f1 40 00 87 8c [ ]*vperm %v15,%v17,%v20,%v24
.*: e7 f1 40 00 d6 84 [ ]*vpdi %v15,%v17,%v20,13
.*: e7 f1 ff fd c4 4d [ ]*vrep %v15,%v17,65533,12
.*: e7 f1 ff fd 04 4d [ ]*vrepb %v15,%v17,65533
.*: e7 f1 ff fd 14 4d [ ]*vreph %v15,%v17,65533
.*: e7 f1 ff fd 24 4d [ ]*vrepf %v15,%v17,65533
.*: e7 f1 ff fd 34 4d [ ]*vrepg %v15,%v17,65533
.*: e7 f0 80 03 c0 45 [ ]*vrepi %v15,-32765,12
.*: e7 f0 80 03 00 45 [ ]*vrepib %v15,-32765
.*: e7 f0 80 03 10 45 [ ]*vrepih %v15,-32765
.*: e7 f0 80 03 20 45 [ ]*vrepif %v15,-32765
.*: e7 f0 80 03 30 45 [ ]*vrepig %v15,-32765
.*: e7 f6 9f a0 d0 1b [ ]*vscef %v15,4000\(%v6,%r9\),13
.*: e7 f6 9f a0 d0 1a [ ]*vsceg %v15,4000\(%v6,%r9\),13
.*: e7 f1 40 00 87 8d [ ]*vsel %v15,%v17,%v20,%v24
.*: e7 f1 00 00 d4 5f [ ]*vseg %v15,%v17,13
.*: e7 f1 00 00 04 5f [ ]*vsegb %v15,%v17
.*: e7 f1 00 00 14 5f [ ]*vsegh %v15,%v17
.*: e7 f1 00 00 24 5f [ ]*vsegf %v15,%v17
.*: e7 f6 9f a0 d0 08 [ ]*vsteb %v15,4000\(%r6,%r9\),13
.*: e7 f6 9f a0 d0 09 [ ]*vsteh %v15,4000\(%r6,%r9\),13
.*: e7 f6 9f a0 d0 0b [ ]*vstef %v15,4000\(%r6,%r9\),13
.*: e7 f6 9f a0 d0 0a [ ]*vsteg %v15,4000\(%r6,%r9\),13
.*: e7 f6 9f a0 00 3f [ ]*vstl %v15,%r6,4000\(%r9\)
.*: e7 f1 00 00 d4 d7 [ ]*vuph %v15,%v17,13
.*: e7 f1 00 00 04 d7 [ ]*vuphb %v15,%v17
.*: e7 f1 00 00 14 d7 [ ]*vuphh %v15,%v17
.*: e7 f1 00 00 24 d7 [ ]*vuphf %v15,%v17
.*: e7 f1 00 00 d4 d5 [ ]*vuplh %v15,%v17,13
.*: e7 f1 00 00 04 d5 [ ]*vuplhb %v15,%v17
.*: e7 f1 00 00 14 d5 [ ]*vuplhh %v15,%v17
.*: e7 f1 00 00 24 d5 [ ]*vuplhf %v15,%v17
.*: e7 f1 00 00 d4 d6 [ ]*vupl %v15,%v17,13
.*: e7 f1 00 00 04 d6 [ ]*vuplb %v15,%v17
.*: e7 f1 00 00 14 d6 [ ]*vuplhw %v15,%v17
.*: e7 f1 00 00 24 d6 [ ]*vuplf %v15,%v17
.*: e7 f1 00 00 d4 d4 [ ]*vupll %v15,%v17,13
.*: e7 f1 00 00 04 d4 [ ]*vupllb %v15,%v17
.*: e7 f1 00 00 14 d4 [ ]*vupllh %v15,%v17
.*: e7 f1 00 00 24 d4 [ ]*vupllf %v15,%v17
.*: e7 f1 40 00 d6 f3 [ ]*va %v15,%v17,%v20,13
.*: e7 f1 40 00 06 f3 [ ]*vab %v15,%v17,%v20
.*: e7 f1 40 00 16 f3 [ ]*vah %v15,%v17,%v20
.*: e7 f1 40 00 26 f3 [ ]*vaf %v15,%v17,%v20
.*: e7 f1 40 00 36 f3 [ ]*vag %v15,%v17,%v20
.*: e7 f1 40 00 46 f3 [ ]*vaq %v15,%v17,%v20
.*: e7 f1 40 00 d6 f1 [ ]*vacc %v15,%v17,%v20,13
.*: e7 f1 40 00 06 f1 [ ]*vaccb %v15,%v17,%v20
.*: e7 f1 40 00 16 f1 [ ]*vacch %v15,%v17,%v20
.*: e7 f1 40 00 26 f1 [ ]*vaccf %v15,%v17,%v20
.*: e7 f1 40 00 36 f1 [ ]*vaccg %v15,%v17,%v20
.*: e7 f1 40 00 46 f1 [ ]*vaccq %v15,%v17,%v20
.*: e7 f1 4d 00 87 bb [ ]*vac %v15,%v17,%v20,%v24,13
.*: e7 f1 44 00 87 bb [ ]*vacq %v15,%v17,%v20,%v24
.*: e7 f1 4d 00 87 b9 [ ]*vaccc %v15,%v17,%v20,%v24,13
.*: e7 f1 44 00 87 b9 [ ]*vacccq %v15,%v17,%v20,%v24
.*: e7 f1 40 00 06 68 [ ]*vn %v15,%v17,%v20
.*: e7 f1 40 00 06 69 [ ]*vnc %v15,%v17,%v20
.*: e7 f1 40 00 d6 f2 [ ]*vavg %v15,%v17,%v20,13
.*: e7 f1 40 00 06 f2 [ ]*vavgb %v15,%v17,%v20
.*: e7 f1 40 00 16 f2 [ ]*vavgh %v15,%v17,%v20
.*: e7 f1 40 00 26 f2 [ ]*vavgf %v15,%v17,%v20
.*: e7 f1 40 00 36 f2 [ ]*vavgg %v15,%v17,%v20
.*: e7 f1 40 00 d6 f0 [ ]*vavgl %v15,%v17,%v20,13
.*: e7 f1 40 00 06 f0 [ ]*vavglb %v15,%v17,%v20
.*: e7 f1 40 00 16 f0 [ ]*vavglh %v15,%v17,%v20
.*: e7 f1 40 00 26 f0 [ ]*vavglf %v15,%v17,%v20
.*: e7 f1 40 00 36 f0 [ ]*vavglg %v15,%v17,%v20
.*: e7 f1 40 00 06 66 [ ]*vcksm %v15,%v17,%v20
.*: e7 f1 00 00 d4 db [ ]*vec %v15,%v17,13
.*: e7 f1 00 00 04 db [ ]*vecb %v15,%v17
.*: e7 f1 00 00 14 db [ ]*vech %v15,%v17
.*: e7 f1 00 00 24 db [ ]*vecf %v15,%v17
.*: e7 f1 00 00 34 db [ ]*vecg %v15,%v17
.*: e7 f1 00 00 d4 d9 [ ]*vecl %v15,%v17,13
.*: e7 f1 00 00 04 d9 [ ]*veclb %v15,%v17
.*: e7 f1 00 00 14 d9 [ ]*veclh %v15,%v17
.*: e7 f1 00 00 24 d9 [ ]*veclf %v15,%v17
.*: e7 f1 00 00 34 d9 [ ]*veclg %v15,%v17
.*: e7 f1 40 c0 d6 f8 [ ]*vceq %v15,%v17,%v20,13,12
.*: e7 f1 40 00 06 f8 [ ]*vceqb %v15,%v17,%v20
.*: e7 f1 40 00 16 f8 [ ]*vceqh %v15,%v17,%v20
.*: e7 f1 40 00 26 f8 [ ]*vceqf %v15,%v17,%v20
.*: e7 f1 40 00 36 f8 [ ]*vceqg %v15,%v17,%v20
.*: e7 f1 40 10 06 f8 [ ]*vceqbs %v15,%v17,%v20
.*: e7 f1 40 10 16 f8 [ ]*vceqhs %v15,%v17,%v20
.*: e7 f1 40 10 26 f8 [ ]*vceqfs %v15,%v17,%v20
.*: e7 f1 40 10 36 f8 [ ]*vceqgs %v15,%v17,%v20
.*: e7 f1 40 c0 d6 fb [ ]*vch %v15,%v17,%v20,13,12
.*: e7 f1 40 00 06 fb [ ]*vchb %v15,%v17,%v20
.*: e7 f1 40 00 16 fb [ ]*vchh %v15,%v17,%v20
.*: e7 f1 40 00 26 fb [ ]*vchf %v15,%v17,%v20
.*: e7 f1 40 00 36 fb [ ]*vchg %v15,%v17,%v20
.*: e7 f1 40 10 06 fb [ ]*vchbs %v15,%v17,%v20
.*: e7 f1 40 10 16 fb [ ]*vchhs %v15,%v17,%v20
.*: e7 f1 40 10 26 fb [ ]*vchfs %v15,%v17,%v20
.*: e7 f1 40 10 36 fb [ ]*vchgs %v15,%v17,%v20
.*: e7 f1 40 c0 d6 f9 [ ]*vchl %v15,%v17,%v20,13,12
.*: e7 f1 40 00 06 f9 [ ]*vchlb %v15,%v17,%v20
.*: e7 f1 40 00 16 f9 [ ]*vchlh %v15,%v17,%v20
.*: e7 f1 40 00 26 f9 [ ]*vchlf %v15,%v17,%v20
.*: e7 f1 40 00 36 f9 [ ]*vchlg %v15,%v17,%v20
.*: e7 f1 40 10 06 f9 [ ]*vchlbs %v15,%v17,%v20
.*: e7 f1 40 10 16 f9 [ ]*vchlhs %v15,%v17,%v20
.*: e7 f1 40 10 26 f9 [ ]*vchlfs %v15,%v17,%v20
.*: e7 f1 40 10 36 f9 [ ]*vchlgs %v15,%v17,%v20
.*: e7 f1 00 00 d4 53 [ ]*vclz %v15,%v17,13
.*: e7 f1 00 00 04 53 [ ]*vclzb %v15,%v17
.*: e7 f1 00 00 14 53 [ ]*vclzh %v15,%v17
.*: e7 f1 00 00 24 53 [ ]*vclzf %v15,%v17
.*: e7 f1 00 00 34 53 [ ]*vclzg %v15,%v17
.*: e7 f1 00 00 d4 52 [ ]*vctz %v15,%v17,13
.*: e7 f1 00 00 04 52 [ ]*vctzb %v15,%v17
.*: e7 f1 00 00 14 52 [ ]*vctzh %v15,%v17
.*: e7 f1 00 00 24 52 [ ]*vctzf %v15,%v17
.*: e7 f1 00 00 34 52 [ ]*vctzg %v15,%v17
.*: e7 f1 40 00 06 6d [ ]*vx %v15,%v17,%v20
.*: e7 f1 40 00 d6 b4 [ ]*vgfm %v15,%v17,%v20,13
.*: e7 f1 40 00 06 b4 [ ]*vgfmb %v15,%v17,%v20
.*: e7 f1 40 00 16 b4 [ ]*vgfmh %v15,%v17,%v20
.*: e7 f1 40 00 26 b4 [ ]*vgfmf %v15,%v17,%v20
.*: e7 f1 40 00 36 b4 [ ]*vgfmg %v15,%v17,%v20
.*: e7 f1 4d 00 87 bc [ ]*vgfma %v15,%v17,%v20,%v24,13
.*: e7 f1 40 00 87 bc [ ]*vgfmab %v15,%v17,%v20,%v24
.*: e7 f1 41 00 87 bc [ ]*vgfmah %v15,%v17,%v20,%v24
.*: e7 f1 42 00 87 bc [ ]*vgfmaf %v15,%v17,%v20,%v24
.*: e7 f1 43 00 87 bc [ ]*vgfmag %v15,%v17,%v20,%v24
.*: e7 f1 00 00 d4 de [ ]*vlc %v15,%v17,13
.*: e7 f1 00 00 04 de [ ]*vlcb %v15,%v17
.*: e7 f1 00 00 14 de [ ]*vlch %v15,%v17
.*: e7 f1 00 00 24 de [ ]*vlcf %v15,%v17
.*: e7 f1 00 00 34 de [ ]*vlcg %v15,%v17
.*: e7 f1 00 00 d4 df [ ]*vlp %v15,%v17,13
.*: e7 f1 00 00 04 df [ ]*vlpb %v15,%v17
.*: e7 f1 00 00 14 df [ ]*vlph %v15,%v17
.*: e7 f1 00 00 24 df [ ]*vlpf %v15,%v17
.*: e7 f1 00 00 34 df [ ]*vlpg %v15,%v17
.*: e7 f1 40 00 d6 ff [ ]*vmx %v15,%v17,%v20,13
.*: e7 f1 40 00 06 ff [ ]*vmxb %v15,%v17,%v20
.*: e7 f1 40 00 16 ff [ ]*vmxh %v15,%v17,%v20
.*: e7 f1 40 00 26 ff [ ]*vmxf %v15,%v17,%v20
.*: e7 f1 40 00 36 ff [ ]*vmxg %v15,%v17,%v20
.*: e7 f1 40 00 d6 fd [ ]*vmxl %v15,%v17,%v20,13
.*: e7 f1 40 00 06 fd [ ]*vmxlb %v15,%v17,%v20
.*: e7 f1 40 00 16 fd [ ]*vmxlh %v15,%v17,%v20
.*: e7 f1 40 00 26 fd [ ]*vmxlf %v15,%v17,%v20
.*: e7 f1 40 00 36 fd [ ]*vmxlg %v15,%v17,%v20
.*: e7 f1 40 00 d6 fe [ ]*vmn %v15,%v17,%v20,13
.*: e7 f1 40 00 06 fe [ ]*vmnb %v15,%v17,%v20
.*: e7 f1 40 00 16 fe [ ]*vmnh %v15,%v17,%v20
.*: e7 f1 40 00 26 fe [ ]*vmnf %v15,%v17,%v20
.*: e7 f1 40 00 36 fe [ ]*vmng %v15,%v17,%v20
.*: e7 f1 40 00 d6 fc [ ]*vmnl %v15,%v17,%v20,13
.*: e7 f1 40 00 06 fc [ ]*vmnlb %v15,%v17,%v20
.*: e7 f1 40 00 16 fc [ ]*vmnlh %v15,%v17,%v20
.*: e7 f1 40 00 26 fc [ ]*vmnlf %v15,%v17,%v20
.*: e7 f1 40 00 36 fc [ ]*vmnlg %v15,%v17,%v20
.*: e7 f1 4d 00 87 aa [ ]*vmal %v15,%v17,%v20,%v24,13
.*: e7 f1 40 00 87 aa [ ]*vmalb %v15,%v17,%v20,%v24
.*: e7 f1 41 00 87 aa [ ]*vmalhw %v15,%v17,%v20,%v24
.*: e7 f1 42 00 87 aa [ ]*vmalf %v15,%v17,%v20,%v24
.*: e7 f1 4d 00 87 ab [ ]*vmah %v15,%v17,%v20,%v24,13
.*: e7 f1 40 00 87 ab [ ]*vmahb %v15,%v17,%v20,%v24
.*: e7 f1 41 00 87 ab [ ]*vmahh %v15,%v17,%v20,%v24
.*: e7 f1 42 00 87 ab [ ]*vmahf %v15,%v17,%v20,%v24
.*: e7 f1 4d 00 87 a9 [ ]*vmalh %v15,%v17,%v20,%v24,13
.*: e7 f1 40 00 87 a9 [ ]*vmalhb %v15,%v17,%v20,%v24
.*: e7 f1 41 00 87 a9 [ ]*vmalhh %v15,%v17,%v20,%v24
.*: e7 f1 42 00 87 a9 [ ]*vmalhf %v15,%v17,%v20,%v24
.*: e7 f1 4d 00 87 ae [ ]*vmae %v15,%v17,%v20,%v24,13
.*: e7 f1 40 00 87 ae [ ]*vmaeb %v15,%v17,%v20,%v24
.*: e7 f1 41 00 87 ae [ ]*vmaeh %v15,%v17,%v20,%v24
.*: e7 f1 42 00 87 ae [ ]*vmaef %v15,%v17,%v20,%v24
.*: e7 f1 4d 00 87 ac [ ]*vmale %v15,%v17,%v20,%v24,13
.*: e7 f1 40 00 87 ac [ ]*vmaleb %v15,%v17,%v20,%v24
.*: e7 f1 41 00 87 ac [ ]*vmaleh %v15,%v17,%v20,%v24
.*: e7 f1 42 00 87 ac [ ]*vmalef %v15,%v17,%v20,%v24
.*: e7 f1 4d 00 87 af [ ]*vmao %v15,%v17,%v20,%v24,13
.*: e7 f1 40 00 87 af [ ]*vmaob %v15,%v17,%v20,%v24
.*: e7 f1 41 00 87 af [ ]*vmaoh %v15,%v17,%v20,%v24
.*: e7 f1 42 00 87 af [ ]*vmaof %v15,%v17,%v20,%v24
.*: e7 f1 4d 00 87 ad [ ]*vmalo %v15,%v17,%v20,%v24,13
.*: e7 f1 40 00 87 ad [ ]*vmalob %v15,%v17,%v20,%v24
.*: e7 f1 41 00 87 ad [ ]*vmaloh %v15,%v17,%v20,%v24
.*: e7 f1 42 00 87 ad [ ]*vmalof %v15,%v17,%v20,%v24
.*: e7 f1 40 00 d6 a3 [ ]*vmh %v15,%v17,%v20,13
.*: e7 f1 40 00 06 a3 [ ]*vmhb %v15,%v17,%v20
.*: e7 f1 40 00 16 a3 [ ]*vmhh %v15,%v17,%v20
.*: e7 f1 40 00 26 a3 [ ]*vmhf %v15,%v17,%v20
.*: e7 f1 40 00 d6 a1 [ ]*vmlh %v15,%v17,%v20,13
.*: e7 f1 40 00 06 a1 [ ]*vmlhb %v15,%v17,%v20
.*: e7 f1 40 00 16 a1 [ ]*vmlhh %v15,%v17,%v20
.*: e7 f1 40 00 26 a1 [ ]*vmlhf %v15,%v17,%v20
.*: e7 f1 40 00 d6 a2 [ ]*vml %v15,%v17,%v20,13
.*: e7 f1 40 00 06 a2 [ ]*vmlb %v15,%v17,%v20
.*: e7 f1 40 00 16 a2 [ ]*vmlhw %v15,%v17,%v20
.*: e7 f1 40 00 26 a2 [ ]*vmlf %v15,%v17,%v20
.*: e7 f1 40 00 d6 a6 [ ]*vme %v15,%v17,%v20,13
.*: e7 f1 40 00 06 a6 [ ]*vmeb %v15,%v17,%v20
.*: e7 f1 40 00 16 a6 [ ]*vmeh %v15,%v17,%v20
.*: e7 f1 40 00 26 a6 [ ]*vmef %v15,%v17,%v20
.*: e7 f1 40 00 d6 a4 [ ]*vmle %v15,%v17,%v20,13
.*: e7 f1 40 00 06 a4 [ ]*vmleb %v15,%v17,%v20
.*: e7 f1 40 00 16 a4 [ ]*vmleh %v15,%v17,%v20
.*: e7 f1 40 00 26 a4 [ ]*vmlef %v15,%v17,%v20
.*: e7 f1 40 00 d6 a7 [ ]*vmo %v15,%v17,%v20,13
.*: e7 f1 40 00 06 a7 [ ]*vmob %v15,%v17,%v20
.*: e7 f1 40 00 16 a7 [ ]*vmoh %v15,%v17,%v20
.*: e7 f1 40 00 26 a7 [ ]*vmof %v15,%v17,%v20
.*: e7 f1 40 00 d6 a5 [ ]*vmlo %v15,%v17,%v20,13
.*: e7 f1 40 00 06 a5 [ ]*vmlob %v15,%v17,%v20
.*: e7 f1 40 00 16 a5 [ ]*vmloh %v15,%v17,%v20
.*: e7 f1 40 00 26 a5 [ ]*vmlof %v15,%v17,%v20
.*: e7 f1 40 00 06 6b [ ]*vno %v15,%v17,%v20
.*: e7 f1 10 00 06 6b [ ]*vno %v15,%v17,%v17
.*: e7 f1 40 00 06 6a [ ]*vo %v15,%v17,%v20
.*: e7 f1 00 00 d4 50 [ ]*vpopct %v15,%v17,13
.*: e7 f1 40 00 d6 73 [ ]*verllv %v15,%v17,%v20,13
.*: e7 f1 40 00 06 73 [ ]*verllvb %v15,%v17,%v20
.*: e7 f1 40 00 16 73 [ ]*verllvh %v15,%v17,%v20
.*: e7 f1 40 00 26 73 [ ]*verllvf %v15,%v17,%v20
.*: e7 f1 40 00 36 73 [ ]*verllvg %v15,%v17,%v20
.*: e7 f1 6f a0 d4 33 [ ]*verll %v15,%v17,4000\(%r6\),13
.*: e7 f1 6f a0 04 33 [ ]*verllb %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 14 33 [ ]*verllh %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 24 33 [ ]*verllf %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 34 33 [ ]*verllg %v15,%v17,4000\(%r6\)
.*: e7 f1 40 fd c6 72 [ ]*verim %v15,%v17,%v20,253,12
.*: e7 f1 40 fd 06 72 [ ]*verimb %v15,%v17,%v20,253
.*: e7 f1 40 fd 16 72 [ ]*verimh %v15,%v17,%v20,253
.*: e7 f1 40 fd 26 72 [ ]*verimf %v15,%v17,%v20,253
.*: e7 f1 40 fd 36 72 [ ]*verimg %v15,%v17,%v20,253
.*: e7 f1 40 00 d6 70 [ ]*veslv %v15,%v17,%v20,13
.*: e7 f1 40 00 06 70 [ ]*veslvb %v15,%v17,%v20
.*: e7 f1 40 00 16 70 [ ]*veslvh %v15,%v17,%v20
.*: e7 f1 40 00 26 70 [ ]*veslvf %v15,%v17,%v20
.*: e7 f1 40 00 36 70 [ ]*veslvg %v15,%v17,%v20
.*: e7 f1 6f a0 d4 30 [ ]*vesl %v15,%v17,4000\(%r6\),13
.*: e7 f1 6f a0 04 30 [ ]*veslb %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 14 30 [ ]*veslh %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 24 30 [ ]*veslf %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 34 30 [ ]*veslg %v15,%v17,4000\(%r6\)
.*: e7 f1 40 00 d6 7a [ ]*vesrav %v15,%v17,%v20,13
.*: e7 f1 40 00 06 7a [ ]*vesravb %v15,%v17,%v20
.*: e7 f1 40 00 16 7a [ ]*vesravh %v15,%v17,%v20
.*: e7 f1 40 00 26 7a [ ]*vesravf %v15,%v17,%v20
.*: e7 f1 40 00 36 7a [ ]*vesravg %v15,%v17,%v20
.*: e7 f1 6f a0 d4 3a [ ]*vesra %v15,%v17,4000\(%r6\),13
.*: e7 f1 6f a0 04 3a [ ]*vesrab %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 14 3a [ ]*vesrah %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 24 3a [ ]*vesraf %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 34 3a [ ]*vesrag %v15,%v17,4000\(%r6\)
.*: e7 f1 40 00 d6 78 [ ]*vesrlv %v15,%v17,%v20,13
.*: e7 f1 40 00 06 78 [ ]*vesrlvb %v15,%v17,%v20
.*: e7 f1 40 00 16 78 [ ]*vesrlvh %v15,%v17,%v20
.*: e7 f1 40 00 26 78 [ ]*vesrlvf %v15,%v17,%v20
.*: e7 f1 40 00 36 78 [ ]*vesrlvg %v15,%v17,%v20
.*: e7 f1 6f a0 d4 38 [ ]*vesrl %v15,%v17,4000\(%r6\),13
.*: e7 f1 6f a0 04 38 [ ]*vesrlb %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 14 38 [ ]*vesrlh %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 24 38 [ ]*vesrlf %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 34 38 [ ]*vesrlg %v15,%v17,4000\(%r6\)
.*: e7 f1 40 00 06 74 [ ]*vsl %v15,%v17,%v20
.*: e7 f1 40 00 06 75 [ ]*vslb %v15,%v17,%v20
.*: e7 f1 40 fd 06 77 [ ]*vsldb %v15,%v17,%v20,253
.*: e7 f1 40 00 06 7e [ ]*vsra %v15,%v17,%v20
.*: e7 f1 40 00 06 7f [ ]*vsrab %v15,%v17,%v20
.*: e7 f1 40 00 06 7c [ ]*vsrl %v15,%v17,%v20
.*: e7 f1 40 00 06 7d [ ]*vsrlb %v15,%v17,%v20
.*: e7 f1 40 00 d6 f7 [ ]*vs %v15,%v17,%v20,13
.*: e7 f1 40 00 06 f7 [ ]*vsb %v15,%v17,%v20
.*: e7 f1 40 00 16 f7 [ ]*vsh %v15,%v17,%v20
.*: e7 f1 40 00 26 f7 [ ]*vsf %v15,%v17,%v20
.*: e7 f1 40 00 36 f7 [ ]*vsg %v15,%v17,%v20
.*: e7 f1 40 00 46 f7 [ ]*vsq %v15,%v17,%v20
.*: e7 f1 40 00 d6 f5 [ ]*vscbi %v15,%v17,%v20,13
.*: e7 f1 40 00 06 f5 [ ]*vscbib %v15,%v17,%v20
.*: e7 f1 40 00 16 f5 [ ]*vscbih %v15,%v17,%v20
.*: e7 f1 40 00 26 f5 [ ]*vscbif %v15,%v17,%v20
.*: e7 f1 40 00 36 f5 [ ]*vscbig %v15,%v17,%v20
.*: e7 f1 40 00 46 f5 [ ]*vscbiq %v15,%v17,%v20
.*: e7 f1 4d 00 87 bf [ ]*vsbi %v15,%v17,%v20,%v24,13
.*: e7 f1 44 00 87 bf [ ]*vsbiq %v15,%v17,%v20,%v24
.*: e7 f1 4d 00 87 bd [ ]*vsbcbi %v15,%v17,%v20,%v24,13
.*: e7 f1 44 00 87 bd [ ]*vsbcbiq %v15,%v17,%v20,%v24
.*: e7 f1 40 00 d6 65 [ ]*vsumg %v15,%v17,%v20,13
.*: e7 f1 40 00 16 65 [ ]*vsumgh %v15,%v17,%v20
.*: e7 f1 40 00 26 65 [ ]*vsumgf %v15,%v17,%v20
.*: e7 f1 40 00 d6 67 [ ]*vsumq %v15,%v17,%v20,13
.*: e7 f1 40 00 26 67 [ ]*vsumqf %v15,%v17,%v20
.*: e7 f1 40 00 36 67 [ ]*vsumqg %v15,%v17,%v20
.*: e7 f1 40 00 d6 64 [ ]*vsum %v15,%v17,%v20,13
.*: e7 f1 40 00 06 64 [ ]*vsumb %v15,%v17,%v20
.*: e7 f1 40 00 16 64 [ ]*vsumh %v15,%v17,%v20
.*: e7 f1 00 00 04 d8 [ ]*vtm %v15,%v17
.*: e7 f1 40 00 d6 82 [ ]*vfae %v15,%v17,%v20,13
.*: e7 f1 40 c0 d6 82 [ ]*vfae %v15,%v17,%v20,13,12
.*: e7 f1 40 00 06 82 [ ]*vfaeb %v15,%v17,%v20
.*: e7 f1 40 d0 06 82 [ ]*vfaebs %v15,%v17,%v20,12
.*: e7 f1 40 00 16 82 [ ]*vfaeh %v15,%v17,%v20
.*: e7 f1 40 d0 16 82 [ ]*vfaehs %v15,%v17,%v20,12
.*: e7 f1 40 00 26 82 [ ]*vfaef %v15,%v17,%v20
.*: e7 f1 40 d0 26 82 [ ]*vfaefs %v15,%v17,%v20,12
.*: e7 f1 40 10 06 82 [ ]*vfaebs %v15,%v17,%v20
.*: e7 f1 40 d0 06 82 [ ]*vfaebs %v15,%v17,%v20,12
.*: e7 f1 40 10 16 82 [ ]*vfaehs %v15,%v17,%v20
.*: e7 f1 40 d0 16 82 [ ]*vfaehs %v15,%v17,%v20,12
.*: e7 f1 40 10 26 82 [ ]*vfaefs %v15,%v17,%v20
.*: e7 f1 40 d0 26 82 [ ]*vfaefs %v15,%v17,%v20,12
.*: e7 f1 40 20 06 82 [ ]*vfaezb %v15,%v17,%v20
.*: e7 f1 40 f0 06 82 [ ]*vfaezbs %v15,%v17,%v20,12
.*: e7 f1 40 20 16 82 [ ]*vfaezh %v15,%v17,%v20
.*: e7 f1 40 f0 16 82 [ ]*vfaezhs %v15,%v17,%v20,12
.*: e7 f1 40 20 26 82 [ ]*vfaezf %v15,%v17,%v20
.*: e7 f1 40 f0 26 82 [ ]*vfaezfs %v15,%v17,%v20,12
.*: e7 f1 40 30 06 82 [ ]*vfaezbs %v15,%v17,%v20
.*: e7 f1 40 f0 06 82 [ ]*vfaezbs %v15,%v17,%v20,12
.*: e7 f1 40 30 16 82 [ ]*vfaezhs %v15,%v17,%v20
.*: e7 f1 40 f0 16 82 [ ]*vfaezhs %v15,%v17,%v20,12
.*: e7 f1 40 30 26 82 [ ]*vfaezfs %v15,%v17,%v20
.*: e7 f1 40 f0 26 82 [ ]*vfaezfs %v15,%v17,%v20,12
.*: e7 f1 40 00 d6 80 [ ]*vfee %v15,%v17,%v20,13
.*: e7 f1 40 c0 d6 80 [ ]*vfee %v15,%v17,%v20,13,12
.*: e7 f1 40 00 06 80 [ ]*vfeeb %v15,%v17,%v20
.*: e7 f1 40 d0 06 80 [ ]*vfeeb %v15,%v17,%v20,13
.*: e7 f1 40 00 16 80 [ ]*vfeeh %v15,%v17,%v20
.*: e7 f1 40 d0 16 80 [ ]*vfeeh %v15,%v17,%v20,13
.*: e7 f1 40 00 26 80 [ ]*vfeef %v15,%v17,%v20
.*: e7 f1 40 d0 26 80 [ ]*vfeef %v15,%v17,%v20,13
.*: e7 f1 40 10 06 80 [ ]*vfeebs %v15,%v17,%v20
.*: e7 f1 40 10 16 80 [ ]*vfeehs %v15,%v17,%v20
.*: e7 f1 40 10 26 80 [ ]*vfeefs %v15,%v17,%v20
.*: e7 f1 40 20 06 80 [ ]*vfeezb %v15,%v17,%v20
.*: e7 f1 40 20 16 80 [ ]*vfeezh %v15,%v17,%v20
.*: e7 f1 40 20 26 80 [ ]*vfeezf %v15,%v17,%v20
.*: e7 f1 40 30 06 80 [ ]*vfeezbs %v15,%v17,%v20
.*: e7 f1 40 30 16 80 [ ]*vfeezhs %v15,%v17,%v20
.*: e7 f1 40 30 26 80 [ ]*vfeezfs %v15,%v17,%v20
.*: e7 f1 40 00 d6 81 [ ]*vfene %v15,%v17,%v20,13
.*: e7 f1 40 c0 d6 81 [ ]*vfene %v15,%v17,%v20,13,12
.*: e7 f1 40 00 06 81 [ ]*vfeneb %v15,%v17,%v20
.*: e7 f1 40 d0 06 81 [ ]*vfeneb %v15,%v17,%v20,13
.*: e7 f1 40 00 16 81 [ ]*vfeneh %v15,%v17,%v20
.*: e7 f1 40 d0 16 81 [ ]*vfeneh %v15,%v17,%v20,13
.*: e7 f1 40 00 26 81 [ ]*vfenef %v15,%v17,%v20
.*: e7 f1 40 d0 26 81 [ ]*vfenef %v15,%v17,%v20,13
.*: e7 f1 40 10 06 81 [ ]*vfenebs %v15,%v17,%v20
.*: e7 f1 40 10 16 81 [ ]*vfenehs %v15,%v17,%v20
.*: e7 f1 40 10 26 81 [ ]*vfenefs %v15,%v17,%v20
.*: e7 f1 40 20 06 81 [ ]*vfenezb %v15,%v17,%v20
.*: e7 f1 40 20 16 81 [ ]*vfenezh %v15,%v17,%v20
.*: e7 f1 40 20 26 81 [ ]*vfenezf %v15,%v17,%v20
.*: e7 f1 40 30 06 81 [ ]*vfenezbs %v15,%v17,%v20
.*: e7 f1 40 30 16 81 [ ]*vfenezhs %v15,%v17,%v20
.*: e7 f1 40 30 26 81 [ ]*vfenezfs %v15,%v17,%v20
.*: e7 f1 00 00 d4 5c [ ]*vistr %v15,%v17,13
.*: e7 f1 00 c0 d4 5c [ ]*vistr %v15,%v17,13,12
.*: e7 f1 00 00 04 5c [ ]*vistrb %v15,%v17
.*: e7 f1 00 d0 04 5c [ ]*vistrb %v15,%v17,13
.*: e7 f1 00 00 14 5c [ ]*vistrh %v15,%v17
.*: e7 f1 00 d0 14 5c [ ]*vistrh %v15,%v17,13
.*: e7 f1 00 00 24 5c [ ]*vistrf %v15,%v17
.*: e7 f1 00 d0 24 5c [ ]*vistrf %v15,%v17,13
.*: e7 f1 00 10 04 5c [ ]*vistrbs %v15,%v17
.*: e7 f1 00 10 14 5c [ ]*vistrhs %v15,%v17
.*: e7 f1 00 10 24 5c [ ]*vistrfs %v15,%v17
.*: e7 f1 4d 00 87 8a [ ]*vstrc %v15,%v17,%v20,%v24,13
.*: e7 f1 4d c0 87 8a [ ]*vstrc %v15,%v17,%v20,%v24,13,12
.*: e7 f1 40 00 87 8a [ ]*vstrcb %v15,%v17,%v20,%v24
.*: e7 f1 40 d0 87 8a [ ]*vstrcbs %v15,%v17,%v20,%v24,12
.*: e7 f1 41 00 87 8a [ ]*vstrch %v15,%v17,%v20,%v24
.*: e7 f1 41 d0 87 8a [ ]*vstrchs %v15,%v17,%v20,%v24,12
.*: e7 f1 42 00 87 8a [ ]*vstrcf %v15,%v17,%v20,%v24
.*: e7 f1 42 d0 87 8a [ ]*vstrcfs %v15,%v17,%v20,%v24,12
.*: e7 f1 40 10 87 8a [ ]*vstrcbs %v15,%v17,%v20,%v24
.*: e7 f1 40 d0 87 8a [ ]*vstrcbs %v15,%v17,%v20,%v24,12
.*: e7 f1 41 10 87 8a [ ]*vstrchs %v15,%v17,%v20,%v24
.*: e7 f1 41 d0 87 8a [ ]*vstrchs %v15,%v17,%v20,%v24,12
.*: e7 f1 42 10 87 8a [ ]*vstrcfs %v15,%v17,%v20,%v24
.*: e7 f1 42 d0 87 8a [ ]*vstrcfs %v15,%v17,%v20,%v24,12
.*: e7 f1 40 20 87 8a [ ]*vstrczb %v15,%v17,%v20,%v24
.*: e7 f1 40 f0 87 8a [ ]*vstrczbs %v15,%v17,%v20,%v24,12
.*: e7 f1 41 20 87 8a [ ]*vstrczh %v15,%v17,%v20,%v24
.*: e7 f1 41 f0 87 8a [ ]*vstrczhs %v15,%v17,%v20,%v24,12
.*: e7 f1 42 20 87 8a [ ]*vstrczf %v15,%v17,%v20,%v24
.*: e7 f1 42 f0 87 8a [ ]*vstrczfs %v15,%v17,%v20,%v24,12
.*: e7 f1 40 30 87 8a [ ]*vstrczbs %v15,%v17,%v20,%v24
.*: e7 f1 40 f0 87 8a [ ]*vstrczbs %v15,%v17,%v20,%v24,12
.*: e7 f1 41 30 87 8a [ ]*vstrczhs %v15,%v17,%v20,%v24
.*: e7 f1 41 f0 87 8a [ ]*vstrczhs %v15,%v17,%v20,%v24,12
.*: e7 f1 42 30 87 8a [ ]*vstrczfs %v15,%v17,%v20,%v24
.*: e7 f1 42 f0 87 8a [ ]*vstrczfs %v15,%v17,%v20,%v24,12
.*: e7 f1 40 0c d6 e3 [ ]*vfa %v15,%v17,%v20,13,12
.*: e7 f1 40 00 36 e3 [ ]*vfadb %v15,%v17,%v20
.*: e7 f1 40 08 36 e3 [ ]*wfadb %v15,%v17,%v20
.*: e7 f1 00 0c d4 cb [ ]*wfc %v15,%v17,13,12
S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 12:19:21 +01:00
.*: e7 f1 00 00 34 cb [ ]*wfcdb %v15,%v17
.*: e7 f1 00 0c d4 ca [ ]*wfk %v15,%v17,13,12
S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 12:19:21 +01:00
.*: e7 f1 00 00 34 ca [ ]*wfkdb %v15,%v17
.*: e7 f1 40 bc d6 e8 [ ]*vfce %v15,%v17,%v20,13,12,11
S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 12:19:21 +01:00
.*: e7 f1 40 00 36 e8 [ ]*vfcedb %v15,%v17,%v20
.*: e7 f1 40 10 36 e8 [ ]*vfcedbs %v15,%v17,%v20
.*: e7 f1 40 08 36 e8 [ ]*wfcedb %v15,%v17,%v20
.*: e7 f1 40 18 36 e8 [ ]*wfcedbs %v15,%v17,%v20
.*: e7 f1 40 bc d6 eb [ ]*vfch %v15,%v17,%v20,13,12,11
.*: e7 f1 40 00 36 eb [ ]*vfchdb %v15,%v17,%v20
.*: e7 f1 40 10 36 eb [ ]*vfchdbs %v15,%v17,%v20
.*: e7 f1 40 08 36 eb [ ]*wfchdb %v15,%v17,%v20
.*: e7 f1 40 18 36 eb [ ]*wfchdbs %v15,%v17,%v20
.*: e7 f1 40 bc d6 ea [ ]*vfche %v15,%v17,%v20,13,12,11
.*: e7 f1 40 00 36 ea [ ]*vfchedb %v15,%v17,%v20
.*: e7 f1 40 10 36 ea [ ]*vfchedbs %v15,%v17,%v20
.*: e7 f1 40 08 36 ea [ ]*wfchedb %v15,%v17,%v20
.*: e7 f1 40 18 36 ea [ ]*wfchedbs %v15,%v17,%v20
.*: e7 f1 00 bc d4 c3 [ ]*vcfps %v15,%v17,13,12,11
S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 12:19:21 +01:00
.*: e7 f1 00 cd 34 c3 [ ]*wcdgb %v15,%v17,5,12
.*: e7 f1 00 cd 34 c3 [ ]*wcdgb %v15,%v17,5,12
.*: e7 f1 00 bc d4 c1 [ ]*vcfpl %v15,%v17,13,12,11
S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 12:19:21 +01:00
.*: e7 f1 00 cd 34 c1 [ ]*wcdlgb %v15,%v17,5,12
.*: e7 f1 00 cd 34 c1 [ ]*wcdlgb %v15,%v17,5,12
.*: e7 f1 00 bc d4 c2 [ ]*vcsfp %v15,%v17,13,12,11
S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 12:19:21 +01:00
.*: e7 f1 00 cd 34 c2 [ ]*wcgdb %v15,%v17,5,12
.*: e7 f1 00 cd 34 c2 [ ]*wcgdb %v15,%v17,5,12
.*: e7 f1 00 bc d4 c0 [ ]*vclfp %v15,%v17,13,12,11
S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 12:19:21 +01:00
.*: e7 f1 00 cd 34 c0 [ ]*wclgdb %v15,%v17,5,12
.*: e7 f1 00 cd 34 c0 [ ]*wclgdb %v15,%v17,5,12
.*: e7 f1 40 0c d6 e5 [ ]*vfd %v15,%v17,%v20,13,12
.*: e7 f1 40 00 36 e5 [ ]*vfddb %v15,%v17,%v20
.*: e7 f1 40 08 36 e5 [ ]*wfddb %v15,%v17,%v20
.*: e7 f1 00 bc d4 c7 [ ]*vfi %v15,%v17,13,12,11
.*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12
.*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12
S/390: Add support for new cpu architecture - arch12. This adds support of new instructions to the S/390 specific parts. The important feature of the new instruction set is the support of single and extended precision floating point vector operations. Note: arch12 is NOT the official name of the new CPU. It just continues the series of archXX options supported as alternate names. The archXX terminology refers to the edition number of the Principle of Operations manual. The official CPU name will be added later while keeping support of the arch12 for backwards compatibility. No testsuite regressions. Committed to mainline. Bye, -Andreas- opcodes/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as facility. * s390-opc.c: Add new operand description macros, new instruction types, instruction masks, and new .insn instruction types. * s390-opc.txt: Add new arch12 instructions. include/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): New value S390_OPCODE_ARCH12. (S390_INSTR_FLAG_VX2): New macro definition. gas/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch12. * doc/as.texinfo: Document arch12 as cpu type. * doc/c-s390.texi: Likewise. * testsuite/gas/s390/s390.exp: Run arch12 specific tests. * testsuite/gas/s390/zarch-arch12.d: New test. * testsuite/gas/s390/zarch-arch12.s: New test. * testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the output patterns.
2017-01-02 16:40:29 +01:00
.*: e7 f1 00 0c d4 c4 [ ]*vfll %v15,%v17,13,12
.*: e7 f1 00 00 24 c4 [ ]*vflls %v15,%v17
.*: e7 f1 00 08 24 c4 [ ]*wflls %v15,%v17
.*: e7 f1 00 bc d4 c5 [ ]*vflr %v15,%v17,13,12,11
.*: e7 f1 00 cd 34 c5 [ ]*wflrd %v15,%v17,5,12
.*: e7 f1 00 cd 34 c5 [ ]*wflrd %v15,%v17,5,12
S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 12:19:21 +01:00
.*: e7 f1 40 0c d6 e7 [ ]*vfm %v15,%v17,%v20,13,12
.*: e7 f1 40 00 36 e7 [ ]*vfmdb %v15,%v17,%v20
.*: e7 f1 40 08 36 e7 [ ]*wfmdb %v15,%v17,%v20
.*: e7 f1 4c 0d 87 8f [ ]*vfma %v15,%v17,%v20,%v24,13,12
.*: e7 f1 43 00 87 8f [ ]*vfmadb %v15,%v17,%v20,%v24
.*: e7 f1 43 08 87 8f [ ]*wfmadb %v15,%v17,%v20,%v24
.*: e7 f1 4c 0d 87 8e [ ]*vfms %v15,%v17,%v20,%v24,13,12
.*: e7 f1 43 00 87 8e [ ]*vfmsdb %v15,%v17,%v20,%v24
.*: e7 f1 43 08 87 8e [ ]*wfmsdb %v15,%v17,%v20,%v24
.*: e7 f1 00 bc d4 cc [ ]*vfpso %v15,%v17,13,12,11
.*: e7 f1 00 d0 34 cc [ ]*vfpsodb %v15,%v17,13
.*: e7 f1 00 d8 34 cc [ ]*wfpsodb %v15,%v17,13
.*: e7 f1 00 00 34 cc [ ]*vflcdb %v15,%v17
.*: e7 f1 00 08 34 cc [ ]*wflcdb %v15,%v17
.*: e7 f1 00 10 34 cc [ ]*vflndb %v15,%v17
.*: e7 f1 00 18 34 cc [ ]*wflndb %v15,%v17
.*: e7 f1 00 20 34 cc [ ]*vflpdb %v15,%v17
.*: e7 f1 00 28 34 cc [ ]*wflpdb %v15,%v17
.*: e7 f1 00 0c d4 ce [ ]*vfsq %v15,%v17,13,12
S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 12:19:21 +01:00
.*: e7 f1 00 00 34 ce [ ]*vfsqdb %v15,%v17
.*: e7 f1 00 08 34 ce [ ]*wfsqdb %v15,%v17
.*: e7 f1 40 0c d6 e2 [ ]*vfs %v15,%v17,%v20,13,12
.*: e7 f1 40 00 36 e2 [ ]*vfsdb %v15,%v17,%v20
.*: e7 f1 40 08 36 e2 [ ]*wfsdb %v15,%v17,%v20
.*: e7 f1 ff db c4 4a [ ]*vftci %v15,%v17,4093,12,11
.*: e7 f1 ff d0 34 4a [ ]*vftcidb %v15,%v17,4093
.*: e7 f1 ff d8 34 4a [ ]*wftcidb %v15,%v17,4093
.*: ed fa 6f a0 3c ae [ ]*cdpt %f3,4000\(251,%r6\),12
.*: ed fa 6f a0 1c af [ ]*cxpt %f1,4000\(251,%r6\),12
.*: ed fa 6f a0 3c ac [ ]*cpdt %f3,4000\(251,%r6\),12
.*: ed fa 6f a0 1c ad [ ]*cpxt %f1,4000\(251,%r6\),12
.*: b9 e0 d0 69 [ ]*locfhrnh %r6,%r9
.*: b9 e0 10 69 [ ]*locfhro %r6,%r9
.*: b9 e0 20 69 [ ]*locfhrh %r6,%r9
.*: b9 e0 20 69 [ ]*locfhrh %r6,%r9
.*: b9 e0 30 69 [ ]*locfhrnle %r6,%r9
.*: b9 e0 40 69 [ ]*locfhrl %r6,%r9
.*: b9 e0 40 69 [ ]*locfhrl %r6,%r9
.*: b9 e0 50 69 [ ]*locfhrnhe %r6,%r9
.*: b9 e0 60 69 [ ]*locfhrlh %r6,%r9
.*: b9 e0 70 69 [ ]*locfhrne %r6,%r9
.*: b9 e0 70 69 [ ]*locfhrne %r6,%r9
.*: b9 e0 80 69 [ ]*locfhre %r6,%r9
.*: b9 e0 80 69 [ ]*locfhre %r6,%r9
.*: b9 e0 90 69 [ ]*locfhrnlh %r6,%r9
.*: b9 e0 a0 69 [ ]*locfhrhe %r6,%r9
.*: b9 e0 b0 69 [ ]*locfhrnl %r6,%r9
.*: b9 e0 b0 69 [ ]*locfhrnl %r6,%r9
.*: b9 e0 c0 69 [ ]*locfhrle %r6,%r9
.*: b9 e0 d0 69 [ ]*locfhrnh %r6,%r9
.*: b9 e0 d0 69 [ ]*locfhrnh %r6,%r9
.*: b9 e0 e0 69 [ ]*locfhrno %r6,%r9
.*: eb 6d 98 f0 fd e0 [ ]*locfhnh %r6,-10000\(%r9\)
.*: eb 61 98 f0 fd e0 [ ]*locfho %r6,-10000\(%r9\)
.*: eb 62 98 f0 fd e0 [ ]*locfhh %r6,-10000\(%r9\)
.*: eb 62 98 f0 fd e0 [ ]*locfhh %r6,-10000\(%r9\)
.*: eb 63 98 f0 fd e0 [ ]*locfhnle %r6,-10000\(%r9\)
.*: eb 64 98 f0 fd e0 [ ]*locfhl %r6,-10000\(%r9\)
.*: eb 64 98 f0 fd e0 [ ]*locfhl %r6,-10000\(%r9\)
.*: eb 65 98 f0 fd e0 [ ]*locfhnhe %r6,-10000\(%r9\)
.*: eb 66 98 f0 fd e0 [ ]*locfhlh %r6,-10000\(%r9\)
.*: eb 67 98 f0 fd e0 [ ]*locfhne %r6,-10000\(%r9\)
.*: eb 67 98 f0 fd e0 [ ]*locfhne %r6,-10000\(%r9\)
.*: eb 68 98 f0 fd e0 [ ]*locfhe %r6,-10000\(%r9\)
.*: eb 68 98 f0 fd e0 [ ]*locfhe %r6,-10000\(%r9\)
.*: eb 69 98 f0 fd e0 [ ]*locfhnlh %r6,-10000\(%r9\)
.*: eb 6a 98 f0 fd e0 [ ]*locfhhe %r6,-10000\(%r9\)
.*: eb 6b 98 f0 fd e0 [ ]*locfhnl %r6,-10000\(%r9\)
.*: eb 6b 98 f0 fd e0 [ ]*locfhnl %r6,-10000\(%r9\)
.*: eb 6c 98 f0 fd e0 [ ]*locfhle %r6,-10000\(%r9\)
.*: eb 6d 98 f0 fd e0 [ ]*locfhnh %r6,-10000\(%r9\)
.*: eb 6d 98 f0 fd e0 [ ]*locfhnh %r6,-10000\(%r9\)
.*: eb 6e 98 f0 fd e0 [ ]*locfhno %r6,-10000\(%r9\)
.*: ec 6c 80 03 00 42 [ ]*lochile %r6,-32765
.*: ec 61 80 03 00 42 [ ]*lochio %r6,-32765
.*: ec 62 80 03 00 42 [ ]*lochih %r6,-32765
.*: ec 62 80 03 00 42 [ ]*lochih %r6,-32765
.*: ec 63 80 03 00 42 [ ]*lochinle %r6,-32765
.*: ec 64 80 03 00 42 [ ]*lochil %r6,-32765
.*: ec 64 80 03 00 42 [ ]*lochil %r6,-32765
.*: ec 65 80 03 00 42 [ ]*lochinhe %r6,-32765
.*: ec 66 80 03 00 42 [ ]*lochilh %r6,-32765
.*: ec 67 80 03 00 42 [ ]*lochine %r6,-32765
.*: ec 67 80 03 00 42 [ ]*lochine %r6,-32765
.*: ec 68 80 03 00 42 [ ]*lochie %r6,-32765
.*: ec 68 80 03 00 42 [ ]*lochie %r6,-32765
.*: ec 69 80 03 00 42 [ ]*lochinlh %r6,-32765
.*: ec 6a 80 03 00 42 [ ]*lochihe %r6,-32765
.*: ec 6b 80 03 00 42 [ ]*lochinl %r6,-32765
.*: ec 6b 80 03 00 42 [ ]*lochinl %r6,-32765
.*: ec 6c 80 03 00 42 [ ]*lochile %r6,-32765
.*: ec 6d 80 03 00 42 [ ]*lochinh %r6,-32765
.*: ec 6d 80 03 00 42 [ ]*lochinh %r6,-32765
.*: ec 6e 80 03 00 42 [ ]*lochino %r6,-32765
.*: ec 6c 80 03 00 46 [ ]*locghile %r6,-32765
.*: ec 61 80 03 00 46 [ ]*locghio %r6,-32765
.*: ec 62 80 03 00 46 [ ]*locghih %r6,-32765
.*: ec 62 80 03 00 46 [ ]*locghih %r6,-32765
.*: ec 63 80 03 00 46 [ ]*locghinle %r6,-32765
.*: ec 64 80 03 00 46 [ ]*locghil %r6,-32765
.*: ec 64 80 03 00 46 [ ]*locghil %r6,-32765
.*: ec 65 80 03 00 46 [ ]*locghinhe %r6,-32765
.*: ec 66 80 03 00 46 [ ]*locghilh %r6,-32765
.*: ec 67 80 03 00 46 [ ]*locghine %r6,-32765
.*: ec 67 80 03 00 46 [ ]*locghine %r6,-32765
.*: ec 68 80 03 00 46 [ ]*locghie %r6,-32765
.*: ec 68 80 03 00 46 [ ]*locghie %r6,-32765
.*: ec 69 80 03 00 46 [ ]*locghinlh %r6,-32765
.*: ec 6a 80 03 00 46 [ ]*locghihe %r6,-32765
.*: ec 6b 80 03 00 46 [ ]*locghinl %r6,-32765
.*: ec 6b 80 03 00 46 [ ]*locghinl %r6,-32765
.*: ec 6c 80 03 00 46 [ ]*locghile %r6,-32765
.*: ec 6d 80 03 00 46 [ ]*locghinh %r6,-32765
.*: ec 6d 80 03 00 46 [ ]*locghinh %r6,-32765
.*: ec 6e 80 03 00 46 [ ]*locghino %r6,-32765
.*: ec 6c 80 03 00 4e [ ]*lochhile %r6,-32765
.*: ec 61 80 03 00 4e [ ]*lochhio %r6,-32765
.*: ec 62 80 03 00 4e [ ]*lochhih %r6,-32765
.*: ec 62 80 03 00 4e [ ]*lochhih %r6,-32765
.*: ec 63 80 03 00 4e [ ]*lochhinle %r6,-32765
.*: ec 64 80 03 00 4e [ ]*lochhil %r6,-32765
.*: ec 64 80 03 00 4e [ ]*lochhil %r6,-32765
.*: ec 65 80 03 00 4e [ ]*lochhinhe %r6,-32765
.*: ec 66 80 03 00 4e [ ]*lochhilh %r6,-32765
.*: ec 67 80 03 00 4e [ ]*lochhine %r6,-32765
.*: ec 67 80 03 00 4e [ ]*lochhine %r6,-32765
.*: ec 68 80 03 00 4e [ ]*lochhie %r6,-32765
.*: ec 68 80 03 00 4e [ ]*lochhie %r6,-32765
.*: ec 69 80 03 00 4e [ ]*lochhinlh %r6,-32765
.*: ec 6a 80 03 00 4e [ ]*lochhihe %r6,-32765
.*: ec 6b 80 03 00 4e [ ]*lochhinl %r6,-32765
.*: ec 6b 80 03 00 4e [ ]*lochhinl %r6,-32765
.*: ec 6c 80 03 00 4e [ ]*lochhile %r6,-32765
.*: ec 6d 80 03 00 4e [ ]*lochhinh %r6,-32765
.*: ec 6d 80 03 00 4e [ ]*lochhinh %r6,-32765
.*: ec 6e 80 03 00 4e [ ]*lochhino %r6,-32765
.*: eb 6d 98 f0 fd e1 [ ]*stocfhnh %r6,-10000\(%r9\)
.*: eb 61 98 f0 fd e1 [ ]*stocfho %r6,-10000\(%r9\)
.*: eb 62 98 f0 fd e1 [ ]*stocfhh %r6,-10000\(%r9\)
.*: eb 62 98 f0 fd e1 [ ]*stocfhh %r6,-10000\(%r9\)
.*: eb 63 98 f0 fd e1 [ ]*stocfhnle %r6,-10000\(%r9\)
.*: eb 64 98 f0 fd e1 [ ]*stocfhl %r6,-10000\(%r9\)
.*: eb 64 98 f0 fd e1 [ ]*stocfhl %r6,-10000\(%r9\)
.*: eb 65 98 f0 fd e1 [ ]*stocfhnhe %r6,-10000\(%r9\)
.*: eb 66 98 f0 fd e1 [ ]*stocfhlh %r6,-10000\(%r9\)
.*: eb 67 98 f0 fd e1 [ ]*stocfhne %r6,-10000\(%r9\)
.*: eb 67 98 f0 fd e1 [ ]*stocfhne %r6,-10000\(%r9\)
.*: eb 68 98 f0 fd e1 [ ]*stocfhe %r6,-10000\(%r9\)
.*: eb 68 98 f0 fd e1 [ ]*stocfhe %r6,-10000\(%r9\)
.*: eb 69 98 f0 fd e1 [ ]*stocfhnlh %r6,-10000\(%r9\)
.*: eb 6a 98 f0 fd e1 [ ]*stocfhhe %r6,-10000\(%r9\)
.*: eb 6b 98 f0 fd e1 [ ]*stocfhnl %r6,-10000\(%r9\)
.*: eb 6b 98 f0 fd e1 [ ]*stocfhnl %r6,-10000\(%r9\)
.*: eb 6c 98 f0 fd e1 [ ]*stocfhle %r6,-10000\(%r9\)
.*: eb 6d 98 f0 fd e1 [ ]*stocfhnh %r6,-10000\(%r9\)
.*: eb 6d 98 f0 fd e1 [ ]*stocfhnh %r6,-10000\(%r9\)
.*: eb 6e 98 f0 fd e1 [ ]*stocfhno %r6,-10000\(%r9\)
.*: e3 69 b8 f0 fd 3a [ ]*llzrgf %r6,-10000\(%r9,%r11\)
.*: e3 69 b8 f0 fd 3b [ ]*lzrf %r6,-10000\(%r9,%r11\)
.*: e3 69 b8 f0 fd 2a [ ]*lzrg %r6,-10000\(%r9,%r11\)
.*: b9 3c 00 69 [ ]*prno %r6,%r9
.*: e7 f6 9f a0 00 06 [ ]*vl %v15,4000\(%r6,%r9\)
.*: e7 f6 9f a0 d0 06 [ ]*vl %v15,4000\(%r6,%r9\),13
.*: e7 f1 6f a0 04 36 [ ]*vlm %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 d4 36 [ ]*vlm %v15,%v17,4000\(%r6\),13
.*: e7 f6 9f a0 00 0e [ ]*vst %v15,4000\(%r6,%r9\)
.*: e7 f6 9f a0 d0 0e [ ]*vst %v15,4000\(%r6,%r9\),13
.*: e7 f1 6f a0 04 3e [ ]*vstm %v15,%v17,4000\(%r6\)
.*: e7 f1 6f a0 d4 3e [ ]*vstm %v15,%v17,4000\(%r6\),13