* tic80-dis.c (print_insn_tic80): Print floating point operands
as floats.
* tic80-opc.c (SPFI): Add single precision floating point
immediate operand type.
(ROTATE): Add rotate operand type for shifts.
(ENDMASK): Add for shifts.
(n): Macro for the 'n' bit.
(i): Macro for the 'i' bit.
(PD): Macro for the 'PD' field.
(P2): Macro for the 'P2' field.
(P1): Macro for the 'P1' field.
(tic80_operands): Add entries for "exts", "extu", "fadd",
"fcmp", and "fdiv".
This commit is contained in:
Fred Fish
parent
ed6e7b0897
commit
003df61759
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@ -1,3 +1,21 @@
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start-sanitize-tic80
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Mon Jan 13 15:58:56 1997 Fred Fish <fnf@cygnus.com>
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* tic80-dis.c (print_insn_tic80): Print floating point operands
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as floats.
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* tic80-opc.c (SPFI): Add single precision floating point
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immediate operand type.
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(ROTATE): Add rotate operand type for shifts.
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(ENDMASK): Add for shifts.
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(n): Macro for the 'n' bit.
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(i): Macro for the 'i' bit.
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(PD): Macro for the 'PD' field.
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(P2): Macro for the 'P2' field.
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(P1): Macro for the 'P1' field.
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(tic80_operands): Add entries for "exts", "extu", "fadd",
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"fcmp", and "fdiv".
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end-sanitize-tic80
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Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com)
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* mn10200-dis.c (disassemble): Mask off unwanted bits after
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@ -280,6 +280,14 @@ print_insn_tic80 (memaddr, info)
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(*info -> fprintf_func) (info -> stream, "%#lx", value);
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}
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}
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else if ((operand -> flags & TIC80_OPERAND_FLOAT) != 0)
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{
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/* FIXME: depends upon sizeof (long) == sizeof (float) */
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union { float f; long l; } fval;
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fval.l = value;
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(*info -> fprintf_func) (info -> stream, "%g", fval.f);
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}
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else
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{
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if ((value > 999 || value < -999)
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@ -77,9 +77,15 @@ const struct tic80_operand tic80_operands[] =
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#define LUBF (LUI + 1)
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{ 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
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/* Single precision floating point immediate in following 32 bit
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word. */
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#define SPFI (LUBF + 1)
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{ 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },
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/* Register in bits 4-0 */
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#define REG_0 (LUBF + 1)
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#define REG_0 (SPFI + 1)
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{ 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
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/* Register in bits 26-22 */
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@ -144,6 +150,16 @@ const struct tic80_operand tic80_operands[] =
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#define LSI_SCALED (REG_SCALED + 1)
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{ 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
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/* Unsigned immediate in bits 4-0, used only for shift instructions */
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#define ROTATE (LSI_SCALED + 1)
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{ 5, 0, NULL, NULL, 0 },
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/* Unsigned immediate in bits 9-5, used only for shift instructions */
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#define ENDMASK (ROTATE + 1)
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{ 5, 5, NULL, NULL, 0 },
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};
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const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
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@ -165,6 +181,12 @@ const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
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#define OP_REG(x) OP_LI(x) /* For readability */
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#define MASK_REG MASK_LI /* For readability */
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/* The 'n' bit at bit 10 */
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#define n(x) ((x) << 10)
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/* The 'i' bit at bit 11 */
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#define i(x) ((x) << 11)
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/* The 'F' bit at bit 27 */
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#define F(x) ((x) << 27)
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@ -193,6 +215,15 @@ const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
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and register opcodes. */
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#define S(x) ((x) << 11)
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/* The 'PD' field at bits 10-9 in floating point instructions */
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#define PD(x) ((x) << 9)
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/* The 'P2' field at bits 8-7 in floating point instructions */
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#define P2(x) ((x) << 7)
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/* The 'P1' field at bits 6-5 in floating point instructions */
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#define P1(x) ((x) << 5)
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const struct tic80_opcode tic80_opcodes[] = {
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@ -377,6 +408,56 @@ const struct tic80_opcode tic80_opcodes[] = {
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{"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), FMT_LI, {LUI} },
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{"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), FMT_REG, {REG_0} },
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/* Extract signed field (actually an sr.ds instruction) */
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{"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
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{"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
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/* Extract unsigned field (actually an sr.dz instruction */
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{"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
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{"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
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/* Floating-point addition */
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{"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
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{"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
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{"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
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{"fadd.dsd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
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{"fadd.ddd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
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{"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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{"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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{"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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{"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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{"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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/* Floating point compare */
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{"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
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{"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
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{"fcmp.ds", OP_LI(0x3EB) | PD(0) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
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{"fcmp.dd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
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{"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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{"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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{"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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{"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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/* Floating point divide */
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{"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
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{"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
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{"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
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{"fdiv.dsd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
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{"fdiv.ddd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
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{"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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{"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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{"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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{"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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{"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
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/* WORK IN PROGRESS BELOW THIS POINT */
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{"illop0", OP_SI(0), MASK_SI, FMT_SI, FIXME},
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