Switch r3 to scratch register, r0 to stack register.
Other misc changes before beta shipment to customer.
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99eceb9a73
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@ -1,6 +1,6 @@
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/* tc-rce.c -- Assemble code for the Experimental RCE
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/* tc-rce.c -- Assemble code for the Experimental RCE
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Copyright (C) 1993 Free Software Foundation.
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Copyright (C) 1993,1994 Free Software Foundation.
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This file is part of GAS, the GNU Assembler.
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This file is part of GAS, the GNU Assembler.
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@ -513,8 +513,8 @@ char *str;
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break;
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break;
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case LR:
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case LR:
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op_end = parse_reg(op_end + 1, ®);
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op_end = parse_reg(op_end + 1, ®);
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if( reg==3 || reg==15 )
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if( reg==0 || reg==15 )
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as_bad ("invalid register 'r3' and 'r15' illegal");
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as_bad ("invalid register 'r0' and 'r15' illegal");
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inst |= (reg<<8);
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inst |= (reg<<8);
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if (*op_end++ == ',')
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if (*op_end++ == ',')
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{
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{
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@ -573,10 +573,10 @@ char *str;
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{ op_end = parse_reg(op_end + 1, &basereg);
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{ op_end = parse_reg(op_end + 1, &basereg);
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if (*op_end == ')')
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if (*op_end == ')')
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op_end++;
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op_end++;
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if (endreg == 15 && basereg == 3)
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if (endreg == 15 && basereg == 0)
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{
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{
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if(reg==0 || reg==15)
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if(reg==0 || reg==15)
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as_bad("bad register list, 'r3' and 'r15' invalid as starting registers");
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as_bad("bad register list, 'r0' and 'r15' invalid as starting registers");
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inst |= 0x0080; /* list form */
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inst |= 0x0080; /* list form */
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inst |= reg;
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inst |= reg;
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}
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}
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@ -1,6 +1,6 @@
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/* This file is tc-rce.h
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/* This file is tc-rce.h
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Copyright (C) 1993 Free Software Foundation, Inc.
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Copyright (C) 1993-1994 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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This file is part of GAS, the GNU Assembler.
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@ -19,9 +19,7 @@ SECTIONS
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*(.data)
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*(.data)
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${CONSTRUCTING+CONSTRUCTORS}
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${CONSTRUCTING+CONSTRUCTORS}
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${RELOCATING+_edata = .;}
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${RELOCATING+_edata = .;}
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}
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.bss ${RELOCATING+SIZEOF(.data) + ADDR(.data)} :
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{
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${RELOCATING+ __bss_start = .};
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${RELOCATING+ __bss_start = .};
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*(.bss)
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*(.bss)
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*(COMMON)
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*(COMMON)
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@ -28,7 +28,6 @@ rce_opcode_info rce_table[]={
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*****/
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*****/
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{ "tstne", O1, 0x0080 },
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{ "tstne", O1, 0x0080 },
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{ "tstgt", O1, 0x0090 },
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{ "tstgt", O1, 0x0090 },
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{ "tstlt", O1, 0x00A0 },
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{ "tstnbz", O1, 0x00B0 },
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{ "tstnbz", O1, 0x00B0 },
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{ "inct", O1, 0x00C0 },
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{ "inct", O1, 0x00C0 },
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{ "incf", O1, 0x00D0 },
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{ "incf", O1, 0x00D0 },
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