Switch r3 to scratch register, r0 to stack register.

Other misc changes before beta shipment to customer.
This commit is contained in:
Michael Tiemann 1994-12-06 02:04:58 +00:00
parent 99eceb9a73
commit 0041db5a97
4 changed files with 7 additions and 10 deletions

View File

@ -1,6 +1,6 @@
/* tc-rce.c -- Assemble code for the Experimental RCE /* tc-rce.c -- Assemble code for the Experimental RCE
Copyright (C) 1993 Free Software Foundation. Copyright (C) 1993,1994 Free Software Foundation.
This file is part of GAS, the GNU Assembler. This file is part of GAS, the GNU Assembler.
@ -513,8 +513,8 @@ char *str;
break; break;
case LR: case LR:
op_end = parse_reg(op_end + 1, &reg); op_end = parse_reg(op_end + 1, &reg);
if( reg==3 || reg==15 ) if( reg==0 || reg==15 )
as_bad ("invalid register 'r3' and 'r15' illegal"); as_bad ("invalid register 'r0' and 'r15' illegal");
inst |= (reg<<8); inst |= (reg<<8);
if (*op_end++ == ',') if (*op_end++ == ',')
{ {
@ -573,10 +573,10 @@ char *str;
{ op_end = parse_reg(op_end + 1, &basereg); { op_end = parse_reg(op_end + 1, &basereg);
if (*op_end == ')') if (*op_end == ')')
op_end++; op_end++;
if (endreg == 15 && basereg == 3) if (endreg == 15 && basereg == 0)
{ {
if(reg==0 || reg==15) if(reg==0 || reg==15)
as_bad("bad register list, 'r3' and 'r15' invalid as starting registers"); as_bad("bad register list, 'r0' and 'r15' invalid as starting registers");
inst |= 0x0080; /* list form */ inst |= 0x0080; /* list form */
inst |= reg; inst |= reg;
} }

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@ -1,6 +1,6 @@
/* This file is tc-rce.h /* This file is tc-rce.h
Copyright (C) 1993 Free Software Foundation, Inc. Copyright (C) 1993-1994 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler. This file is part of GAS, the GNU Assembler.

View File

@ -19,9 +19,7 @@ SECTIONS
*(.data) *(.data)
${CONSTRUCTING+CONSTRUCTORS} ${CONSTRUCTING+CONSTRUCTORS}
${RELOCATING+_edata = .;} ${RELOCATING+_edata = .;}
}
.bss ${RELOCATING+SIZEOF(.data) + ADDR(.data)} :
{
${RELOCATING+ __bss_start = .}; ${RELOCATING+ __bss_start = .};
*(.bss) *(.bss)
*(COMMON) *(COMMON)

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@ -28,7 +28,6 @@ rce_opcode_info rce_table[]={
*****/ *****/
{ "tstne", O1, 0x0080 }, { "tstne", O1, 0x0080 },
{ "tstgt", O1, 0x0090 }, { "tstgt", O1, 0x0090 },
{ "tstlt", O1, 0x00A0 },
{ "tstnbz", O1, 0x00B0 }, { "tstnbz", O1, 0x00B0 },
{ "inct", O1, 0x00C0 }, { "inct", O1, 0x00C0 },
{ "incf", O1, 0x00D0 }, { "incf", O1, 0x00D0 },