opcodes/
* mips-opc.c (mips_builtin_opcodes): Correct register use annotation of "alnv.ps". gas/testsuite/ * gas/mips/alnv_ps-swap.d: New test for ALNV.PS instruction branch swapping. * gas/mips/alnv_ps-swap.s: Source for the new test. * gas/mips/mips.exp: Run the new test.
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@ -1,3 +1,10 @@
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2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
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* gas/mips/alnv_ps-swap.d: New test for ALNV.PS instruction
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branch swapping.
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* gas/mips/alnv_ps-swap.s: Source for the new test.
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* gas/mips/mips.exp: Run the new test.
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2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
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* gas/mips/relax-bposge.l: New test for DSP branch relaxation.
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39
gas/testsuite/gas/mips/alnv_ps-swap.d
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39
gas/testsuite/gas/mips/alnv_ps-swap.d
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: MIPS ALNV.PS instruction branch swapping
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#as: -32
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# Check that a register dependency between ALNV.PS and the following
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# branch prevents from branch swapping.
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.*: +file format .*mips.*
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Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> 1000ffff b 0+0000 <foo>
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[0-9a-f]+ <[^>]*> 4c60111e alnv\.ps \$f4,\$f2,\$f0,v1
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[0-9a-f]+ <[^>]*> 0411fffd bal 0+0000 <foo>
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[0-9a-f]+ <[^>]*> 4c60111e alnv\.ps \$f4,\$f2,\$f0,v1
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[0-9a-f]+ <[^>]*> 0470fffb bltzal v1,0+0000 <foo>
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[0-9a-f]+ <[^>]*> 4c60111e alnv\.ps \$f4,\$f2,\$f0,v1
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[0-9a-f]+ <[^>]*> 0060f809 jalr v1
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[0-9a-f]+ <[^>]*> 4c60111e alnv\.ps \$f4,\$f2,\$f0,v1
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[0-9a-f]+ <[^>]*> 00602009 jalr a0,v1
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[0-9a-f]+ <[^>]*> 4c60111e alnv\.ps \$f4,\$f2,\$f0,v1
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[0-9a-f]+ <[^>]*> 4c60111e alnv\.ps \$f4,\$f2,\$f0,v1
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[0-9a-f]+ <[^>]*> 03e01809 jalr v1,ra
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 1000fff2 b 0+0000 <foo>
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[0-9a-f]+ <[^>]*> 4fe0111e alnv\.ps \$f4,\$f2,\$f0,ra
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[0-9a-f]+ <[^>]*> 4fe0111e alnv\.ps \$f4,\$f2,\$f0,ra
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[0-9a-f]+ <[^>]*> 0411ffef bal 0+0000 <foo>
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 4fe0111e alnv\.ps \$f4,\$f2,\$f0,ra
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[0-9a-f]+ <[^>]*> 0470ffec bltzal v1,0+0000 <foo>
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 4fe0111e alnv\.ps \$f4,\$f2,\$f0,ra
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[0-9a-f]+ <[^>]*> 0060f809 jalr v1
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 00602009 jalr a0,v1
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[0-9a-f]+ <[^>]*> 4fe0111e alnv\.ps \$f4,\$f2,\$f0,ra
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[0-9a-f]+ <[^>]*> 03e01809 jalr v1,ra
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[0-9a-f]+ <[^>]*> 4fe0111e alnv\.ps \$f4,\$f2,\$f0,ra
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\.\.\.
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33
gas/testsuite/gas/mips/alnv_ps-swap.s
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33
gas/testsuite/gas/mips/alnv_ps-swap.s
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# Source file to test branch swapping with the ALNV.PS instruction.
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.text
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foo:
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alnv.ps $f4, $f2, $f0, $3
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b foo
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alnv.ps $f4, $f2, $f0, $3
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bal foo
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alnv.ps $f4, $f2, $f0, $3
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bltzal $3, foo
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alnv.ps $f4, $f2, $f0, $3
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jalr $3
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alnv.ps $f4, $f2, $f0, $3
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jalr $4, $3
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alnv.ps $f4, $f2, $f0, $3
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jalr $3, $31
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alnv.ps $f4, $f2, $f0, $31
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b foo
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alnv.ps $f4, $f2, $f0, $31
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bal foo
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alnv.ps $f4, $f2, $f0, $31
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bltzal $3, foo
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alnv.ps $f4, $f2, $f0, $31
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jalr $3
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alnv.ps $f4, $f2, $f0, $31
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jalr $4, $3
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alnv.ps $f4, $f2, $f0, $31
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jalr $3, $31
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.align 2
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.space 8
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@ -979,6 +979,9 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "mips32-sync"
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run_dump_test_arches "mips32r2-sync" \
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[mips_arch_list_matching mips32r2]
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run_dump_test_arches "alnv_ps-swap" [lsort -dictionary -unique [concat \
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[mips_arch_list_matching mips5] \
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[mips_arch_list_matching mips32r2] ] ]
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if $has_newabi { run_dump_test "cfi-n64-1" }
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}
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@ -1,3 +1,8 @@
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2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-opc.c (mips_builtin_opcodes): Correct register use
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annotation of "alnv.ps".
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2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
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@ -297,7 +297,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
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{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 },
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{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
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{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 },
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{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, I5_33 },
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{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 },
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{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX },
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{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
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