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* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo.
	(bfd_elf32_bigarm_symbian_vec): Likewise.
	(bfd_elf32_bigarm_vxworks_vec): Likewise.
	(bfd_elf32_littlearm_vec): Likewise.
	(bfd_elf32_littlearm_symbian_vec): Likewise.
	(bfd_elf32_littlearm_vxworks_vec): Likewise.
	* configure: Regenerate.
	* elf32-arm.c: Include libiberty.h and elf-vxworks.h.
	(RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros.
	(elf32_arm_vxworks_bed): Add forward declaration.
	(elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12.
	(elf32_arm_vxworks_exec_plt0_entry): New table.
	(elf32_arm_vxworks_exec_plt_entry): Likewise.
	(elf32_arm_vxworks_shared_plt_entry): Likewise.
	(elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields.
	(reloc_section_p): New function.
	(create_got_section): Use RELOC_SECTION.
	(elf32_arm_create_dynamic_sections): Likewise.  Call
	elf_vxworks_create_dynamic_sections for VxWorks targets.
	Choose between the two possible values of plt_header_size
	and plt_entry_size.
	(elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2.
	(elf32_arm_abs12_reloc): New function.
	(elf32_arm_final_link_relocate): Call it.  Allow the creation of
	dynamic R_ARM_ABS12 relocs on VxWorks.  Use reloc_section_p,
	RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION.  Initialize the
	r_addend fields of relocs.  On rela targets, skip any code that
	adjusts in-place addends.  When using _bfd_link_final_relocate
	to perform a final relocation, pass rel->r_addend as the addend
	argument.
	(elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks
	object, ignore flags that are not standard on VxWorks.
	(elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12
	relocs on VxWorks.  Use reloc_section_p.
	(elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE.
	(allocate_dynrelocs): Use RELOC_SIZE.  Account for the size of
	.rela.plt.unloaded relocs on VxWorks targets.
	(elf32_arm_size_dynamic_sections): Use RELOC_SIZE.  Check for
	.rela.plt.unloaded as well as .rel(a).plt.  Add DT_RELA* tags
	instead of DT_REL* tags on RELA targets.
	(elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE
	and SWAP_RELOC_OUT.  Initialize r_addend fields.  Handle VxWorks
	PLT entries.  Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
	(elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE
	and SWAP_RELOC_OUT.  Initialize r_addend fields.  Handle DT_RELASZ
	like DT_RELSZ.  Handle the VxWorks form of initial PLT entry.
	Correct the .rela.plt.unreloaded symbol indexes.
	(elf32_arm_output_symbol_hook): Call the VxWorks version of this
	hook on VxWorks targets.
	(elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true.
	Minor formatting tweak.
	(elf32_arm_vxworks_final_write_processing): New function.
	(elf_backend_add_symbol_hook): Override for VxWorks and reset
	for Symbian.
	(elf_backend_final_write_processing): Likewise.
	(elf_backend_emit_relocs): Likewise.
	(elf_backend_want_plt_sym): Likewise.
	(ELF_MAXPAGESIZE): Likewise.
	(elf_backend_may_use_rel_p): Minor formatting tweak.
	(elf_backend_may_use_rela_p): Likewise.
	(elf_backend_default_use_rela_p): Likewise.
	(elf_backend_rela_normal): Likewise.
	* Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h.

gas/
	* config/tc-arm.c (md_apply_fix): Install a value of zero into a
	BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
	R_ARM_ABS12 reloc.
	(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
	relocs, but adjust by md_pcrel_from_section.  Create R_ARM_ABS12
	relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.

gas/testsuite/
	* gas/arm/abs12.s, gas/arm/abs12.d: New test.
	* gas/arm/pic.d: Skip for *-*-vxworks*...
	* gas/arm/pic_vxworks.d: ...use this version instead.
	* gas/arm/unwind_vxworks.d: Fix expected output.

ld/
	* emulparams/armelf_vxworks.sh: Include vxworks.sh.
	(MAXPAGESIZE): Define.
	* emulparams/vxworks.sh: Undefine.
	* Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em.
	* Makefile.in: Regenerate.

ld/testsuite/
	* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
	* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
	* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
	* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
	* ld-arm/vxworks2-static.sd: New tests.
	* ld-arm/arm-elf.exp: Run them.
This commit is contained in:
Richard Sandiford 2006-03-07 08:39:21 +00:00
parent 5f4a23d95c
commit 00a976722a
33 changed files with 969 additions and 196 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

72
bfd/ChangeLog
View File

@ -1,3 +1,75 @@
2006-03-07 Richard Sandiford <richard@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Zack Weinberg <zack@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
Paul Brook <paul@codesourcery.com>
Ricardo Anguiano <anguiano@codesourcery.com>
Phil Edwards <phil@codesourcery.com>
* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerate.
* elf32-arm.c: Include libiberty.h and elf-vxworks.h.
(RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros.
(elf32_arm_vxworks_bed): Add forward declaration.
(elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12.
(elf32_arm_vxworks_exec_plt0_entry): New table.
(elf32_arm_vxworks_exec_plt_entry): Likewise.
(elf32_arm_vxworks_shared_plt_entry): Likewise.
(elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields.
(reloc_section_p): New function.
(create_got_section): Use RELOC_SECTION.
(elf32_arm_create_dynamic_sections): Likewise. Call
elf_vxworks_create_dynamic_sections for VxWorks targets.
Choose between the two possible values of plt_header_size
and plt_entry_size.
(elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2.
(elf32_arm_abs12_reloc): New function.
(elf32_arm_final_link_relocate): Call it. Allow the creation of
dynamic R_ARM_ABS12 relocs on VxWorks. Use reloc_section_p,
RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION. Initialize the
r_addend fields of relocs. On rela targets, skip any code that
adjusts in-place addends. When using _bfd_link_final_relocate
to perform a final relocation, pass rel->r_addend as the addend
argument.
(elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks
object, ignore flags that are not standard on VxWorks.
(elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12
relocs on VxWorks. Use reloc_section_p.
(elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE.
(allocate_dynrelocs): Use RELOC_SIZE. Account for the size of
.rela.plt.unloaded relocs on VxWorks targets.
(elf32_arm_size_dynamic_sections): Use RELOC_SIZE. Check for
.rela.plt.unloaded as well as .rel(a).plt. Add DT_RELA* tags
instead of DT_REL* tags on RELA targets.
(elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle VxWorks
PLT entries. Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
(elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle DT_RELASZ
like DT_RELSZ. Handle the VxWorks form of initial PLT entry.
Correct the .rela.plt.unreloaded symbol indexes.
(elf32_arm_output_symbol_hook): Call the VxWorks version of this
hook on VxWorks targets.
(elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true.
Minor formatting tweak.
(elf32_arm_vxworks_final_write_processing): New function.
(elf_backend_add_symbol_hook): Override for VxWorks and reset
for Symbian.
(elf_backend_final_write_processing): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_want_plt_sym): Likewise.
(ELF_MAXPAGESIZE): Likewise.
(elf_backend_may_use_rel_p): Minor formatting tweak.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
(elf_backend_rela_normal): Likewise.
* Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h.
2006-03-06 Nathan Sidwell <nathan@codesourcery.com>
* archures.c (bfd_mach_mcf_isa_a_nodiv, bfd_mach_mcf_isa_b_nousp):

4
bfd/Makefile.am
View File

@ -1220,8 +1220,8 @@ elf32-arc.lo: elf32-arc.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
elf32-target.h
elf32-arm.lo: elf32-arm.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arm.h \
$(INCDIR)/elf/reloc-macros.h elf32-target.h
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h elf-vxworks.h \
$(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h elf32-target.h
elf32-avr.lo: elf32-avr.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/avr.h \

4
bfd/Makefile.in
View File

@ -1787,8 +1787,8 @@ elf32-arc.lo: elf32-arc.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
elf32-target.h
elf32-arm.lo: elf32-arm.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arm.h \
$(INCDIR)/elf/reloc-macros.h elf32-target.h
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h elf-vxworks.h \
$(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h elf32-target.h
elf32-avr.lo: elf32-avr.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/avr.h \

12
bfd/configure vendored
View File

@ -13073,11 +13073,11 @@ do
bfd_elf32_bfin_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
bfd_elf32_big_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
bfd_elf32_bigarc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
bfd_elf32_bigarm_vec) tb="$tb elf32-arm.lo elf32.lo $elf" ;;
bfd_elf32_bigarm_vec) tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigarm_symbian_vec)
tb="$tb elf32-arm.lo elf32.lo $elf" ;;
tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigarm_vxworks_vec)
tb="$tb elf32-arm.lo elf32.lo $elf" ;;
tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_cr16c_vec) tb="$tb elf32-cr16c.lo elf32.lo $elf" ;;
bfd_elf32_cris_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;;
@ -13106,10 +13106,10 @@ do
bfd_elf32_little_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
bfd_elf32_littlearc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_symbian_vec)
tb="$tb elf32-arm.lo elf32.lo $elf" ;;
tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_littlearm_vxworks_vec)
tb="$tb elf32-arm.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo $elf" ;;
tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;;
bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;

12
bfd/configure.in
View File

@ -586,11 +586,11 @@ do
bfd_elf32_bfin_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
bfd_elf32_big_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
bfd_elf32_bigarc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
bfd_elf32_bigarm_vec) tb="$tb elf32-arm.lo elf32.lo $elf" ;;
bfd_elf32_bigarm_vec) tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigarm_symbian_vec)
tb="$tb elf32-arm.lo elf32.lo $elf" ;;
tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigarm_vxworks_vec)
tb="$tb elf32-arm.lo elf32.lo $elf" ;;
tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_bigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_cr16c_vec) tb="$tb elf32-cr16c.lo elf32.lo $elf" ;;
bfd_elf32_cris_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;;
@ -619,10 +619,10 @@ do
bfd_elf32_little_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
bfd_elf32_littlearc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_symbian_vec)
tb="$tb elf32-arm.lo elf32.lo $elf" ;;
tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_littlearm_vxworks_vec)
tb="$tb elf32-arm.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo $elf" ;;
tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo elf-vxworks.lo $elf" ;;
bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;;
bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;

655
bfd/elf32-arm.c
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File diff suppressed because it is too large Load Diff

15
gas/ChangeLog
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@ -1,3 +1,18 @@
2006-03-07 Richard Sandiford <richard@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Zack Weinberg <zack@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
Paul Brook <paul@codesourcery.com>
Ricardo Anguiano <anguiano@codesourcery.com>
Phil Edwards <phil@codesourcery.com>
* config/tc-arm.c (md_apply_fix): Install a value of zero into a
BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
R_ARM_ABS12 reloc.
(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
2006-03-06 Bob Wilson <bob.wilson@acm.org>
* config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables

19
gas/config/tc-arm.c
View File

@ -11535,6 +11535,9 @@ md_apply_fix (fixS * fixP,
break;
case BFD_RELOC_ARM_OFFSET_IMM:
if (!fixP->fx_done && seg->use_rela_p)
value = 0;
case BFD_RELOC_ARM_LITERAL:
sign = value >= 0;
@ -12256,8 +12259,7 @@ md_apply_fix (fixS * fixP,
format. */
arelent *
tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
fixS * fixp)
tc_gen_reloc (asection *section, fixS *fixp)
{
arelent * reloc;
bfd_reloc_code_real_type code;
@ -12269,7 +12271,12 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
if (fixp->fx_pcrel)
fixp->fx_offset = reloc->address;
{
if (section->use_rela_p)
fixp->fx_offset -= md_pcrel_from_section (fixp, section);
else
fixp->fx_offset = reloc->address;
}
reloc->addend = fixp->fx_offset;
switch (fixp->fx_r_type)
@ -12357,6 +12364,12 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
return NULL;
case BFD_RELOC_ARM_OFFSET_IMM:
if (section->use_rela_p)
{
code = fixp->fx_r_type;
break;
}
if (fixp->fx_addsy != NULL
&& !S_IS_DEFINED (fixp->fx_addsy)
&& S_IS_LOCAL (fixp->fx_addsy))

7
gas/testsuite/ChangeLog
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@ -1,3 +1,10 @@
2006-03-07 Richard Sandiford <richard@codesourcery.com>
* gas/arm/abs12.s, gas/arm/abs12.d: New test.
* gas/arm/pic.d: Skip for *-*-vxworks*...
* gas/arm/pic_vxworks.d: ...use this version instead.
* gas/arm/unwind_vxworks.d: Fix expected output.
2006-03-06 Nathan Sidwell <nathan@codesourcery.com>
* gas/m68k/arch-cpu-1.s: Tweak.

20
gas/testsuite/gas/arm/abs12.d Normal file
View File

@ -0,0 +1,20 @@
#objdump: -dr
#not-skip: *-vxworks
.*: file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: e5910000 ldr r0, \[r1\]
0: R_ARM_ABS12 global
4: e5910000 ldr r0, \[r1\]
4: R_ARM_ABS12 global\+0xc
8: e5910000 ldr r0, \[r1\]
8: R_ARM_ABS12 global\+0x100000
c: e5910000 ldr r0, \[r1\]
c: R_ARM_ABS12 \.text\+0x18
10: e5910000 ldr r0, \[r1\]
10: R_ARM_ABS12 \.text\+0x24
14: e5910000 ldr r0, \[r1\]
14: R_ARM_ABS12 \.text\+0x100018

7
gas/testsuite/gas/arm/abs12.s Normal file
View File

@ -0,0 +1,7 @@
ldr r0,[r1,#global]
ldr r0,[r1,#global + 12]
ldr r0,[r1,#global + 0x100000]
ldr r0,[r1,#local]
ldr r0,[r1,#local + 12]
ldr r0,[r1,#local + 0x100000]
local:

2
gas/testsuite/gas/arm/pic.d
View File

@ -2,6 +2,8 @@
#name: PIC
# This test is only valid on ELF based ports.
#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
# VxWorks needs a special variant of this file.
#skip: *-*-vxworks*
# Test generation of PIC

22
gas/testsuite/gas/arm/pic_vxworks.d Normal file
View File

@ -0,0 +1,22 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: PIC
#source: pic.s
#not-skip: *-*-vxworks*
# Test generation of PIC
.*: +file format .*arm.*
Disassembly of section .text:
00+0 <[^>]*> eb000000 bl .*
0: R_ARM_PC24 foo\+0xfffffff8
00+4 <[^>]*> eb000000 bl .*
4: R_ARM_PLT32 foo\+0xfffffff8
\.\.\.
8: R_ARM_ABS32 sym
c: R_ARM_GOT32 sym
10: R_ARM_GOTOFF32 sym
14: R_ARM_GOTPC _GLOBAL_OFFSET_TABLE_
18: R_ARM_TARGET1 foo2
1c: R_ARM_SBREL32 foo3
20: R_ARM_TARGET2 foo4

26
gas/testsuite/gas/arm/unwind_vxworks.d
View File

@ -1,7 +1,5 @@
#objdump: -sr
#name: Unwind table generation
# This test is only valid on ELF based ports.
#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
# This is the VxWorks variant of this file.
#source: unwind.s
#not-skip: *-*-vxworks*
@ -10,22 +8,22 @@
RELOCATION RECORDS FOR \[.ARM.extab\]:
OFFSET TYPE VALUE
0000000c R_ARM_PREL31 .text\+0x0+c
0000000c R_ARM_PREL31 .text
RELOCATION RECORDS FOR \[.ARM.exidx\]:
OFFSET TYPE VALUE
00000000 R_ARM_PREL31 .text
00000000 R_ARM_NONE __aeabi_unwind_cpp_pr0
00000008 R_ARM_PREL31 .text.*
00000008 R_ARM_NONE __aeabi_unwind_cpp_pr1\+0x0+8
0000000c R_ARM_PREL31 .ARM.extab\+0x0+c
00000010 R_ARM_PREL31 .text.*
00000014 R_ARM_PREL31 .ARM.extab.*
00000018 R_ARM_PREL31 .text.*
0000001c R_ARM_PREL31 .ARM.extab.*
00000020 R_ARM_PREL31 .text.*
00000028 R_ARM_PREL31 .text.*
00000008 R_ARM_PREL31 .text.*\+0x00000004
00000008 R_ARM_NONE __aeabi_unwind_cpp_pr1
0000000c R_ARM_PREL31 .ARM.extab
00000010 R_ARM_PREL31 .text.*\+0x00000008
00000014 R_ARM_PREL31 .ARM.extab.*\+0x0000000c
00000018 R_ARM_PREL31 .text.*\+0x0000000c
0000001c R_ARM_PREL31 .ARM.extab.*\+0x0000001c
00000020 R_ARM_PREL31 .text.*\+0x00000010
00000028 R_ARM_PREL31 .text.*\+0x00000012
Contents of section .text:
@ -36,8 +34,8 @@ Contents of section .ARM.extab:
0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600) .*
0020 (b0b0c1c1|c1c1b0b0) 00000000 .*
Contents of section .ARM.exidx:
0000 00000000 (b0b0a880 00000000|80a8b0b0 00000000) 00000000 .*
0000 00000000 (b0b0a880|80a8b0b0) 00000000 00000000 .*
0010 00000000 00000000 00000000 00000000 .*
0020 (00000000 08849780 00000000 b00fb180|00000000 80978408 00000000 80b10fb0) .*
0020 00000000 (08849780|80978408) 00000000 (b00fb180|80b10fb0) .*
# Ignore .ARM.attributes section
#...

14
ld/ChangeLog
View File

@ -1,3 +1,17 @@
2006-03-07 Richard Sandiford <richard@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Zack Weinberg <zack@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
Paul Brook <paul@codesourcery.com>
Ricardo Anguiano <anguiano@codesourcery.com>
Phil Edwards <phil@codesourcery.com>
* emulparams/armelf_vxworks.sh: Include vxworks.sh.
(MAXPAGESIZE): Define.
* emulparams/vxworks.sh: Undefine EMBEDDED.
* Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em.
* Makefile.in: Regenerate.
2006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
* scripttempl/avr.sc: Add *(.jumptables) *(.lowtext) sections.

3
ld/Makefile.am
View File

@ -539,7 +539,8 @@ earmelfb_nbsd.c: $(srcdir)/emulparams/armelfb_nbsd.sh \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} armelfb_nbsd "$(tdir_armelfb_nbsd)"
earmelf_vxworks.c: $(srcdir)/emulparams/armelf_vxworks.sh \
$(srcdir)/emulparams/armelf.sh $(srcdir)/emultempl/elf32.em \
$(srcdir)/emulparams/vxworks.sh $(srcdir)/emulparams/armelf.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/vxworks.em \
$(srcdir)/emultempl/armelf.em $(srcdir)/scripttempl/elf.sc \
${GEN_DEPENDS}
${GENSCRIPTS} armelf_vxworks "$(tdir_armelf)"

3
ld/Makefile.in
View File

@ -1345,7 +1345,8 @@ earmelfb_nbsd.c: $(srcdir)/emulparams/armelfb_nbsd.sh \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} armelfb_nbsd "$(tdir_armelfb_nbsd)"
earmelf_vxworks.c: $(srcdir)/emulparams/armelf_vxworks.sh \
$(srcdir)/emulparams/armelf.sh $(srcdir)/emultempl/elf32.em \
$(srcdir)/emulparams/vxworks.sh $(srcdir)/emulparams/armelf.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/vxworks.em \
$(srcdir)/emultempl/armelf.em $(srcdir)/scripttempl/elf.sc \
${GEN_DEPENDS}
${GENSCRIPTS} armelf_vxworks "$(tdir_armelf)"

2
ld/emulparams/armelf_vxworks.sh
View File

@ -2,3 +2,5 @@
OUTPUT_FORMAT="elf32-littlearm-vxworks"
BIG_OUTPUT_FORMAT="elf32-bigarm-vxworks"
LITTLE_OUTPUT_FORMAT="$OUTPUT_FORMAT"
MAXPAGESIZE=0x1000
. ${srcdir}/emulparams/vxworks.sh

1
ld/emulparams/vxworks.sh
View File

@ -25,3 +25,4 @@ OTHER_SYMBOLS="PROVIDE (_ehdr = ${TEXT_START_ADDR});"
DATA_END_SYMBOLS=".edata : { PROVIDE (_edata = .); }"
VXWORKS_BASE_EM_FILE=$EXTRA_EM_FILE
EXTRA_EM_FILE=vxworks
unset EMBEDDED

9
ld/testsuite/ChangeLog
View File

@ -1,3 +1,12 @@
2006-03-07 Richard Sandiford <richard@codesourcery.com>
* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
* ld-arm/vxworks2-static.sd: New tests.
* ld-arm/arm-elf.exp: Run them.
2006-03-06 Nathan Sidwell <nathan@codesourcery.com>
* ld-m68k: New tests.

27
ld/testsuite/ld-arm/arm-elf.exp
View File

@ -16,6 +16,33 @@
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#
if {[istarget "arm-*-vxworks"]} {
set armvxworkstests {
{"VxWorks shared library test 1" "-shared -Tvxworks1.ld"
"" {vxworks1-lib.s}
{{readelf --relocs vxworks1-lib.rd} {objdump -dr vxworks1-lib.dd}
{readelf --symbols vxworks1-lib.nd}}
"libvxworks1.so"}
{"VxWorks executable test 1 (dynamic)" \
"tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic"
"" {vxworks1.s}
{{readelf --relocs vxworks1.rd} {objdump -dr vxworks1.dd}}
"vxworks1"}
{"VxWorks executable test 2 (dynamic)" \
"-Tvxworks1.ld -q --force-dynamic"
"" {vxworks2.s}
{{readelf --segments vxworks2.sd}}
"vxworks2"}
{"VxWorks executable test 2 (static)"
"-Tvxworks1.ld"
"" {vxworks2.s}
{{readelf --segments vxworks2-static.sd}}
"vxworks2"}
}
run_ld_link_tests $armvxworkstests
run_dump_test "vxworks1-static"
}
# Exclude non-ARM-ELF targets.
if { ![is_elf_format] || ![istarget "arm*-*-*"] } {

41
ld/testsuite/ld-arm/vxworks1-lib.dd Normal file
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@ -0,0 +1,41 @@
.*: file format .*
Disassembly of section \.plt:
00080800 <_PROCEDURE_LINKAGE_TABLE_>:
80800: e59fc000 ldr ip, \[pc, #0\] ; 80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>
80804: e79cf009 ldr pc, \[ip, r9\]
80808: 0000000c andeq r0, r0, ip
8080c: e59fc000 ldr ip, \[pc, #0\] ; 80814 <_PROCEDURE_LINKAGE_TABLE_\+0x14>
80810: e599f008 ldr pc, \[r9, #8\]
80814: 00000000 andeq r0, r0, r0
80818: e59fc000 ldr ip, \[pc, #0\] ; 80820 <_PROCEDURE_LINKAGE_TABLE_\+0x20>
8081c: e79cf009 ldr pc, \[ip, r9\]
80820: 00000010 andeq r0, r0, r0, lsl r0
80824: e59fc000 ldr ip, \[pc, #0\] ; 8082c <_PROCEDURE_LINKAGE_TABLE_\+0x2c>
80828: e599f008 ldr pc, \[r9, #8\]
8082c: 0000000c andeq r0, r0, ip
Disassembly of section \.text:
00080c00 <foo>:
80c00: e92dc200 stmdb sp!, {r9, lr, pc}
80c04: e59f9024 ldr r9, \[pc, #36\] ; 80c30 <\.text\+0x30>
80c08: e5999000 ldr r9, \[r9\]
80c0c: e5999000 ldr r9, \[r9\]
80c10: e59f001c ldr r0, \[pc, #28\] ; 80c34 <\.text\+0x34>
80c14: e7991000 ldr r1, \[r9, r0\]
80c18: e2811001 add r1, r1, #1 ; 0x1
80c1c: e7891000 str r1, \[r9, r0\]
80c20: eb000004 bl 80c38 <slocal>
80c24: ebfffefb bl 80818 <_PROCEDURE_LINKAGE_TABLE_\+0x18>
80c28: ebfffef4 bl 80800 <_PROCEDURE_LINKAGE_TABLE_>
80c2c: e8bd8200 ldmia sp!, {r9, pc}
80c30: 00000000 andeq r0, r0, r0
80c34: 00000014 andeq r0, r0, r4, lsl r0
00080c38 <slocal>:
80c38: e1a0f00e mov pc, lr
00080c3c <sglobal>:
80c3c: e1a0f00e mov pc, lr

9
ld/testsuite/ld-arm/vxworks1-lib.nd Normal file
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@ -0,0 +1,9 @@
#...
Symbol table '\.dynsym' .*:
#...
.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
#...
Symbol table '\.symtab' .*:
#...
.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
#pass

12
ld/testsuite/ld-arm/vxworks1-lib.rd Normal file
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@ -0,0 +1,12 @@
Relocation section '\.rela\.plt' at offset .* contains 2 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend
0008140c .*16 R_ARM_JUMP_SLOT 00000000 sexternal \+ 0
00081410 .*16 R_ARM_JUMP_SLOT 00080c3c sglobal \+ 0
Relocation section '\.rela\.dyn' at offset .* contains 4 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend
00081c00 00000017 R_ARM_RELATIVE * 00080c38
00080c0c .*06 R_ARM_ABS12 00000000 __GOTT_INDEX__ \+ 0
00080c30 .*02 R_ARM_ABS32 00000000 __GOTT_BASE__ \+ 0
00081414 .*15 R_ARM_GLOB_DAT 00081800 x \+ 0

36
ld/testsuite/ld-arm/vxworks1-lib.s Normal file
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@ -0,0 +1,36 @@
.text
.globl foo
.type foo, %function
foo:
stmfd sp!, {r9, lr, pc}
ldr r9, 1f
ldr r9, [r9]
ldr r9, [r9, #__GOTT_INDEX__]
ldr r0, 1f + 4
ldr r1, [r9, r0]
add r1, r1, #1
str r1, [r9, r0]
bl slocal(PLT)
bl sglobal(PLT)
bl sexternal(PLT)
ldmfd sp!, {r9, pc}
1:
.word __GOTT_BASE__
.word x(got)
.size foo, .-foo
.type slocal, %function
slocal:
mov pc,lr
.size slocal, .-slocal
.globl sglobal
.type sglobal, %function
sglobal:
mov pc,lr
.size sglobal, .-sglobal
.data
.4byte slocal
.comm x,4,4

4
ld/testsuite/ld-arm/vxworks1-static.d Normal file
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@ -0,0 +1,4 @@
#name: VxWorks executable test 1 (static)
#source: vxworks1.s
#ld: tmpdir/libvxworks1.so -Tvxworks1.ld
#error: Dynamic sections created in non-dynamic link

37
ld/testsuite/ld-arm/vxworks1.dd Normal file
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@ -0,0 +1,37 @@
.*: file format .*
Disassembly of section \.plt:
00080800 <_PROCEDURE_LINKAGE_TABLE_>:
80800: e52dc008 str ip, \[sp, #-8\]!
80804: e59fc000 ldr ip, \[pc, #0\] ; 8080c <_PROCEDURE_LINKAGE_TABLE_\+0xc>
80808: e59cf008 ldr pc, \[ip, #8\]
8080c: 00081400 andeq r1, r8, r0, lsl #8
8080c: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_
80810: e59fc000 ldr ip, \[pc, #0\] ; 80818 <_PROCEDURE_LINKAGE_TABLE_\+0x18>
80814: e59cf000 ldr pc, \[ip\]
80818: 0008140c andeq r1, r8, ip, lsl #8
80818: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0xc
8081c: e59fc000 ldr ip, \[pc, #0\] ; 80824 <_PROCEDURE_LINKAGE_TABLE_\+0x24>
80820: eafffff6 b 80800 <_PROCEDURE_LINKAGE_TABLE_>
80824: 00000000 andeq r0, r0, r0
80828: e59fc000 ldr ip, \[pc, #0\] ; 80830 <_PROCEDURE_LINKAGE_TABLE_\+0x30>
8082c: e59cf000 ldr pc, \[ip\]
80830: 00081410 andeq r1, r8, r0, lsl r4
80830: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0x10
80834: e59fc000 ldr ip, \[pc, #0\] ; 8083c <_PROCEDURE_LINKAGE_TABLE_\+0x3c>
80838: eafffff0 b 80800 <_PROCEDURE_LINKAGE_TABLE_>
8083c: 0000000c andeq r0, r0, ip
Disassembly of section \.text:
00080c00 <_start>:
80c00: ebffff08 bl 80428 <_PROCEDURE_LINKAGE_TABLE_-0x3d8>
80c00: R_ARM_PC24 \.plt\+0x20
80c04: eb000000 bl 80c14 <sexternal\+0x8>
80c04: R_ARM_PC24 sexternal\+0xfffffff8
80c08: eaffff00 b 80408 <_PROCEDURE_LINKAGE_TABLE_-0x3f8>
80c08: R_ARM_PC24 \.plt\+0x8
00080c0c <sexternal>:
80c0c: e1a0f00e mov pc, lr

30
ld/testsuite/ld-arm/vxworks1.ld Normal file
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@ -0,0 +1,30 @@
SECTIONS
{
. = 0x80000;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
. = ALIGN (0x400);
.rela.dyn : { *(.rela.dyn) }
.rela.plt : { *(.rela.plt) }
. = ALIGN (0x400);
.plt : { *(.plt) }
. = ALIGN (0x400);
.text : { *(.text) }
. = ALIGN (0x1000);
.dynamic : { *(.dynamic) }
. = ALIGN (0x400);
.got : { *(.got.plt) *(.got) }
. = ALIGN (0x400);
.bss : { *(.bss) *(.dynbss) }
. = ALIGN (0x400);
.data : { *(.data) }
}

19
ld/testsuite/ld-arm/vxworks1.rd Normal file
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@ -0,0 +1,19 @@
Relocation section '\.rela\.plt' at offset .* contains 2 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend
0008140c .*16 R_ARM_JUMP_SLOT 00080810 sglobal \+ 0
00081410 .*16 R_ARM_JUMP_SLOT 00080828 foo \+ 0
Relocation section '\.rela\.text' at offset .* contains 3 entries:
Offset Info Type Sym.Value Sym. Name \+ Addend
00080c00 .*01 R_ARM_PC24 00080800 \.plt \+ 20
00080c04 .*01 R_ARM_PC24 00080c0c sexternal \+ fffffff8
00080c08 .*01 R_ARM_PC24 00080800 \.plt \+ 8
Relocation section '\.rela\.plt\.unloaded' at offset .* contains 5 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend
0008080c .*02 R_ARM_ABS32 00081400 _GLOBAL_OFFSET_TABLE_ \+ 0
00080818 .*02 R_ARM_ABS32 00081400 _GLOBAL_OFFSET_TABLE_ \+ c
0008140c .*02 R_ARM_ABS32 00080800 _PROCEDURE_LINKAGE_TAB.* \+ 0
00080830 .*02 R_ARM_ABS32 00081400 _GLOBAL_OFFSET_TABLE_ \+ 10
00081410 .*02 R_ARM_ABS32 00080800 _PROCEDURE_LINKAGE_TAB.* \+ 0

14
ld/testsuite/ld-arm/vxworks1.s Normal file
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@ -0,0 +1,14 @@
.text
.globl _start
.type _start, %function
_start:
bl foo
bl sexternal
b sglobal
.size _start, .-_start
.globl sexternal
.type sexternal, %function
sexternal:
mov pc, lr
.size sexternal, .-sexternal

9
ld/testsuite/ld-arm/vxworks2-static.sd Normal file
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@ -0,0 +1,9 @@
#...
Elf file type is EXEC \(Executable file\)
Entry point 0x80000
#...
Program Headers:
Type .*
LOAD .* 0x00080000 0x00080000 .* R E 0x1000
#...

5
ld/testsuite/ld-arm/vxworks2.s Normal file
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@ -0,0 +1,5 @@
.globl _start
.type _start, %function
_start:
mov pc, lr
.end _start

13
ld/testsuite/ld-arm/vxworks2.sd Normal file
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@ -0,0 +1,13 @@
#...
Elf file type is EXEC \(Executable file\)
Entry point 0x80400
#...
Program Headers:
Type .*
PHDR .*
#...
LOAD .* 0x00080000 0x00080000 .* R E 0x1000
LOAD .* 0x00081000 0x00081000 .* RW 0x1000
DYNAMIC .*
#...