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Add Disp32S to 64bit call. 

gas/testsuite/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/13046
	* gas/i386/x86-64-branch.s: Add tests for direct branch.
	* gas/i386/x86-64-branch.d: Updated.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.

opcodes/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/13046
	* i386-opc.tbl: Add Disp32S to 64bit call.
	* i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu 2011-08-01 19:25:48 +00:00
parent 3fbb6ffa98
commit 00f51a41a8
7 changed files with 27 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gas/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR gas/13046
* gas/i386/x86-64-branch.s: Add tests for direct branch.
* gas/i386/x86-64-branch.d: Updated.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
2011-07-29 Nick Clifton <nickc@redhat.com>
* gas/elf/warn-2.s: Add other types of NOP insn.

4
gas/testsuite/gas/i386/ilp32/x86-64-branch.d
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@ -18,6 +18,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x1f 1b: R_X86_64_PC32 \*ABS\*\+0x10003c
[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x24 20: R_X86_64_PC32 \*ABS\*\+0x10003c
[ ]*[a-f0-9]+: ff d0 callq \*%rax
[ ]*[a-f0-9]+: ff d0 callq \*%rax
[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
@ -28,4 +30,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x43 3f: R_X86_64_PC32 \*ABS\*\+0x10003c
[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x48 44: R_X86_64_PC32 \*ABS\*\+0x10003c
#pass

4
gas/testsuite/gas/i386/x86-64-branch.d
View File

@ -17,6 +17,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x1f 1b: R_X86_64_PC32 \*ABS\*\+0x10003c
[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x24 20: R_X86_64_PC32 \*ABS\*\+0x10003c
[ ]*[a-f0-9]+: ff d0 callq \*%rax
[ ]*[a-f0-9]+: ff d0 callq \*%rax
[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
@ -27,4 +29,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x43 3f: R_X86_64_PC32 \*ABS\*\+0x10003c
[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x48 44: R_X86_64_PC32 \*ABS\*\+0x10003c
#pass

4
gas/testsuite/gas/i386/x86-64-branch.s
View File

@ -9,6 +9,8 @@
jmp *%ax
jmpw *%ax
jmpw *(%rax)
call 0x100040
jmp 0x100040
.intel_syntax noprefix
call rax
@ -21,3 +23,5 @@
jmp ax
jmpw ax
jmpw [rax]
call 0x100040
jmp 0x100040

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR gas/13046
* i386-opc.tbl: Add Disp32S to 64bit call.
* i386-tbl.h: Regenerated.
2011-07-24 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>

2
opcodes/i386-opc.tbl
View File

@ -320,7 +320,7 @@ shrd, 2, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, {
// Control transfer instructions.
call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32 }
call, 1, 0xe8, None, 1, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Disp16|Disp32 }
call, 1, 0xe8, None, 1, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Disp16|Disp32|Disp32S }
call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
call, 1, 0xff, 0x2, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
// Intel Syntax

2
opcodes/i386-tbl.h
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@ -2558,7 +2558,7 @@ const insn_template i386_optab[] =
1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
{ "call", 1, 0xff, 0x2, 1,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,