Add Disp32S to 64bit call.
gas/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR gas/13046 * gas/i386/x86-64-branch.s: Add tests for direct branch. * gas/i386/x86-64-branch.d: Updated. * gas/i386/ilp32/x86-64-branch.d: Likewise. opcodes/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR gas/13046 * i386-opc.tbl: Add Disp32S to 64bit call. * i386-tbl.h: Regenerated.
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@ -1,3 +1,10 @@
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2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/13046
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* gas/i386/x86-64-branch.s: Add tests for direct branch.
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* gas/i386/x86-64-branch.d: Updated.
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* gas/i386/ilp32/x86-64-branch.d: Likewise.
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2011-07-29 Nick Clifton <nickc@redhat.com>
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* gas/elf/warn-2.s: Add other types of NOP insn.
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@ -18,6 +18,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
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[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x1f 1b: R_X86_64_PC32 \*ABS\*\+0x10003c
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[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x24 20: R_X86_64_PC32 \*ABS\*\+0x10003c
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
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@ -28,4 +30,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
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[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x43 3f: R_X86_64_PC32 \*ABS\*\+0x10003c
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[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x48 44: R_X86_64_PC32 \*ABS\*\+0x10003c
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#pass
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@ -17,6 +17,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
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[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x1f 1b: R_X86_64_PC32 \*ABS\*\+0x10003c
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[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x24 20: R_X86_64_PC32 \*ABS\*\+0x10003c
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
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@ -27,4 +29,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
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[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x43 3f: R_X86_64_PC32 \*ABS\*\+0x10003c
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[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x48 44: R_X86_64_PC32 \*ABS\*\+0x10003c
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#pass
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@ -9,6 +9,8 @@
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jmp *%ax
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jmpw *%ax
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jmpw *(%rax)
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call 0x100040
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jmp 0x100040
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.intel_syntax noprefix
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call rax
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@ -21,3 +23,5 @@
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jmp ax
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jmpw ax
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jmpw [rax]
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call 0x100040
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jmp 0x100040
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@ -1,3 +1,9 @@
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2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/13046
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* i386-opc.tbl: Add Disp32S to 64bit call.
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* i386-tbl.h: Regenerated.
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2011-07-24 Chao-ying Fu <fu@mips.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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@ -320,7 +320,7 @@ shrd, 2, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, {
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// Control transfer instructions.
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call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32 }
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call, 1, 0xe8, None, 1, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Disp16|Disp32 }
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call, 1, 0xe8, None, 1, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Disp16|Disp32|Disp32S }
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call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
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call, 1, 0xff, 0x2, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
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// Intel Syntax
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@ -2558,7 +2558,7 @@ const insn_template i386_optab[] =
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1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "call", 1, 0xff, 0x2, 1,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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