x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so gas should accept such input. As the brojen code got
released already we sadly will need to continue to also accept the
badly ordered operands.
gas/testsuite/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f-intel.d: Adjust expectations on operand order.
* gas/i386/evex-lig256-intel.d: Likewise.
* gas/i386/evex-lig512-intel.d: Likewise.
* gas/i386/x86-64-avx512f-intel.d: Likewise.
* gas/i386/x86-64-evex-lig256-intel.d: Likewise.
* gas/i386/x86-64-evex-lig512-intel.d: Likewise.
opcodes/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
* i386-tbl.h: Regenerate.
This commit is contained in:
Jan Beulich
Jan Beulich
parent
b2e38b610c
commit
015c54d5a6
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@ -1,3 +1,12 @@
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2015-06-01 Jan Beulich <jbeulich@suse.com>
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* gas/i386/avx512f-intel.d: Adjust expectations on operand order.
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* gas/i386/evex-lig256-intel.d: Likewise.
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* gas/i386/evex-lig512-intel.d: Likewise.
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* gas/i386/x86-64-avx512f-intel.d: Likewise.
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* gas/i386/x86-64-evex-lig256-intel.d: Likewise.
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* gas/i386/x86-64-evex-lig512-intel.d: Likewise.
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2015-05-28 Catherine Moore <clm@codesourcery.com>
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Bernd Schmidt <bernds@codesourcery.com>
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@ -9904,14 +9904,14 @@ _start:
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vcvtsd2ss xmm6{k7}, xmm5, QWORD PTR [edx-1032] # AVX512F
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vcvtsi2ss xmm6, xmm5, {rn-sae}, eax # AVX512F
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vcvtsi2ss xmm6, xmm5, {ru-sae}, eax # AVX512F
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vcvtsi2ss xmm6, xmm5, {rd-sae}, eax # AVX512F
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vcvtsi2ss xmm6, xmm5, {rz-sae}, eax # AVX512F
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vcvtsi2ss xmm6, xmm5, {rn-sae}, ebp # AVX512F
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vcvtsi2ss xmm6, xmm5, {ru-sae}, ebp # AVX512F
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vcvtsi2ss xmm6, xmm5, {rd-sae}, ebp # AVX512F
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vcvtsi2ss xmm6, xmm5, {rz-sae}, ebp # AVX512F
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vcvtsi2ss xmm6, xmm5, eax, {rn-sae} # AVX512F
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vcvtsi2ss xmm6, xmm5, eax, {ru-sae} # AVX512F
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vcvtsi2ss xmm6, xmm5, eax, {rd-sae} # AVX512F
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vcvtsi2ss xmm6, xmm5, eax, {rz-sae} # AVX512F
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vcvtsi2ss xmm6, xmm5, ebp, {rn-sae} # AVX512F
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vcvtsi2ss xmm6, xmm5, ebp, {ru-sae} # AVX512F
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vcvtsi2ss xmm6, xmm5, ebp, {rd-sae} # AVX512F
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vcvtsi2ss xmm6, xmm5, ebp, {rz-sae} # AVX512F
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vcvtss2sd xmm6{k7}, xmm5, xmm4 # AVX512F
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vcvtss2sd xmm6{k7}{z}, xmm5, xmm4 # AVX512F
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@ -13704,15 +13704,15 @@ _start:
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vcvtusi2sd xmm6, xmm5, DWORD PTR [edx-516] # AVX512F
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vcvtusi2ss xmm6, xmm5, eax # AVX512F
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vcvtusi2ss xmm6, xmm5, {rn-sae}, eax # AVX512F
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vcvtusi2ss xmm6, xmm5, {ru-sae}, eax # AVX512F
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vcvtusi2ss xmm6, xmm5, {rd-sae}, eax # AVX512F
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vcvtusi2ss xmm6, xmm5, {rz-sae}, eax # AVX512F
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vcvtusi2ss xmm6, xmm5, eax, {rn-sae} # AVX512F
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vcvtusi2ss xmm6, xmm5, eax, {ru-sae} # AVX512F
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vcvtusi2ss xmm6, xmm5, eax, {rd-sae} # AVX512F
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vcvtusi2ss xmm6, xmm5, eax, {rz-sae} # AVX512F
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vcvtusi2ss xmm6, xmm5, ebp # AVX512F
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vcvtusi2ss xmm6, xmm5, {rn-sae}, ebp # AVX512F
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vcvtusi2ss xmm6, xmm5, {ru-sae}, ebp # AVX512F
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vcvtusi2ss xmm6, xmm5, {rd-sae}, ebp # AVX512F
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vcvtusi2ss xmm6, xmm5, {rz-sae}, ebp # AVX512F
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vcvtusi2ss xmm6, xmm5, ebp, {rn-sae} # AVX512F
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vcvtusi2ss xmm6, xmm5, ebp, {ru-sae} # AVX512F
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vcvtusi2ss xmm6, xmm5, ebp, {rd-sae} # AVX512F
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vcvtusi2ss xmm6, xmm5, ebp, {rz-sae} # AVX512F
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vcvtusi2ss xmm6, xmm5, DWORD PTR [ecx] # AVX512F
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vcvtusi2ss xmm6, xmm5, DWORD PTR [esp+esi*8-123456] # AVX512F
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vcvtusi2ss xmm6, xmm5, DWORD PTR [edx+508] # AVX512F Disp8
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@ -10339,15 +10339,15 @@ _start:
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vcvtsi2sd xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F
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vcvtsi2sd xmm30, xmm29, rax # AVX512F
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vcvtsi2sd xmm30, xmm29, {rn-sae}, rax # AVX512F
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vcvtsi2sd xmm30, xmm29, {ru-sae}, rax # AVX512F
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vcvtsi2sd xmm30, xmm29, {rd-sae}, rax # AVX512F
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vcvtsi2sd xmm30, xmm29, {rz-sae}, rax # AVX512F
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vcvtsi2sd xmm30, xmm29, rax, {rn-sae} # AVX512F
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vcvtsi2sd xmm30, xmm29, rax, {ru-sae} # AVX512F
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vcvtsi2sd xmm30, xmm29, rax, {rd-sae} # AVX512F
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vcvtsi2sd xmm30, xmm29, rax, {rz-sae} # AVX512F
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vcvtsi2sd xmm30, xmm29, r8 # AVX512F
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vcvtsi2sd xmm30, xmm29, {rn-sae}, r8 # AVX512F
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vcvtsi2sd xmm30, xmm29, {ru-sae}, r8 # AVX512F
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vcvtsi2sd xmm30, xmm29, {rd-sae}, r8 # AVX512F
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vcvtsi2sd xmm30, xmm29, {rz-sae}, r8 # AVX512F
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vcvtsi2sd xmm30, xmm29, r8, {rn-sae} # AVX512F
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vcvtsi2sd xmm30, xmm29, r8, {ru-sae} # AVX512F
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vcvtsi2sd xmm30, xmm29, r8, {rd-sae} # AVX512F
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vcvtsi2sd xmm30, xmm29, r8, {rz-sae} # AVX512F
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vcvtsi2sd xmm30, xmm29, QWORD PTR [rcx] # AVX512F
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vcvtsi2sd xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F
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vcvtsi2sd xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8
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@ -10356,20 +10356,20 @@ _start:
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vcvtsi2sd xmm30, xmm29, QWORD PTR [rdx-1032] # AVX512F
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vcvtsi2ss xmm30, xmm29, eax # AVX512F
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vcvtsi2ss xmm30, xmm29, {rn-sae}, eax # AVX512F
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vcvtsi2ss xmm30, xmm29, {ru-sae}, eax # AVX512F
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vcvtsi2ss xmm30, xmm29, {rd-sae}, eax # AVX512F
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vcvtsi2ss xmm30, xmm29, {rz-sae}, eax # AVX512F
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vcvtsi2ss xmm30, xmm29, eax, {rn-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, eax, {ru-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, eax, {rd-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, eax, {rz-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, ebp # AVX512F
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vcvtsi2ss xmm30, xmm29, {rn-sae}, ebp # AVX512F
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vcvtsi2ss xmm30, xmm29, {ru-sae}, ebp # AVX512F
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vcvtsi2ss xmm30, xmm29, {rd-sae}, ebp # AVX512F
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vcvtsi2ss xmm30, xmm29, {rz-sae}, ebp # AVX512F
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vcvtsi2ss xmm30, xmm29, ebp, {rn-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, ebp, {ru-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, ebp, {rd-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, ebp, {rz-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, r13d # AVX512F
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vcvtsi2ss xmm30, xmm29, {rn-sae}, r13d # AVX512F
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vcvtsi2ss xmm30, xmm29, {ru-sae}, r13d # AVX512F
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vcvtsi2ss xmm30, xmm29, {rd-sae}, r13d # AVX512F
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vcvtsi2ss xmm30, xmm29, {rz-sae}, r13d # AVX512F
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vcvtsi2ss xmm30, xmm29, r13d, {rn-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, r13d, {ru-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, r13d, {rd-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, r13d, {rz-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, DWORD PTR [rcx] # AVX512F
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vcvtsi2ss xmm30, xmm29, DWORD PTR [rax+r14*8+0x1234] # AVX512F
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vcvtsi2ss xmm30, xmm29, DWORD PTR [rdx+508] # AVX512F Disp8
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@ -10378,15 +10378,15 @@ _start:
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vcvtsi2ss xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F
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vcvtsi2ss xmm30, xmm29, rax # AVX512F
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vcvtsi2ss xmm30, xmm29, {rn-sae}, rax # AVX512F
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vcvtsi2ss xmm30, xmm29, {ru-sae}, rax # AVX512F
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vcvtsi2ss xmm30, xmm29, {rd-sae}, rax # AVX512F
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vcvtsi2ss xmm30, xmm29, {rz-sae}, rax # AVX512F
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vcvtsi2ss xmm30, xmm29, rax, {rn-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, rax, {ru-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, rax, {rd-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, rax, {rz-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, r8 # AVX512F
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vcvtsi2ss xmm30, xmm29, {rn-sae}, r8 # AVX512F
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vcvtsi2ss xmm30, xmm29, {ru-sae}, r8 # AVX512F
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vcvtsi2ss xmm30, xmm29, {rd-sae}, r8 # AVX512F
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vcvtsi2ss xmm30, xmm29, {rz-sae}, r8 # AVX512F
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vcvtsi2ss xmm30, xmm29, r8, {rn-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, r8, {ru-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, r8, {rd-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, r8, {rz-sae} # AVX512F
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vcvtsi2ss xmm30, xmm29, QWORD PTR [rcx] # AVX512F
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vcvtsi2ss xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F
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vcvtsi2ss xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8
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@ -14409,15 +14409,15 @@ _start:
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vcvtusi2sd xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F
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vcvtusi2sd xmm30, xmm29, rax # AVX512F
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vcvtusi2sd xmm30, xmm29, {rn-sae}, rax # AVX512F
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vcvtusi2sd xmm30, xmm29, {ru-sae}, rax # AVX512F
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vcvtusi2sd xmm30, xmm29, {rd-sae}, rax # AVX512F
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vcvtusi2sd xmm30, xmm29, {rz-sae}, rax # AVX512F
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vcvtusi2sd xmm30, xmm29, rax, {rn-sae} # AVX512F
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vcvtusi2sd xmm30, xmm29, rax, {ru-sae} # AVX512F
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vcvtusi2sd xmm30, xmm29, rax, {rd-sae} # AVX512F
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vcvtusi2sd xmm30, xmm29, rax, {rz-sae} # AVX512F
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vcvtusi2sd xmm30, xmm29, r8 # AVX512F
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vcvtusi2sd xmm30, xmm29, {rn-sae}, r8 # AVX512F
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vcvtusi2sd xmm30, xmm29, {ru-sae}, r8 # AVX512F
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vcvtusi2sd xmm30, xmm29, {rd-sae}, r8 # AVX512F
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vcvtusi2sd xmm30, xmm29, {rz-sae}, r8 # AVX512F
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vcvtusi2sd xmm30, xmm29, r8, {rn-sae} # AVX512F
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vcvtusi2sd xmm30, xmm29, r8, {ru-sae} # AVX512F
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vcvtusi2sd xmm30, xmm29, r8, {rd-sae} # AVX512F
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vcvtusi2sd xmm30, xmm29, r8, {rz-sae} # AVX512F
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vcvtusi2sd xmm30, xmm29, QWORD PTR [rcx] # AVX512F
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vcvtusi2sd xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F
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vcvtusi2sd xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8
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@ -14426,20 +14426,20 @@ _start:
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vcvtusi2sd xmm30, xmm29, QWORD PTR [rdx-1032] # AVX512F
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vcvtusi2ss xmm30, xmm29, eax # AVX512F
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vcvtusi2ss xmm30, xmm29, {rn-sae}, eax # AVX512F
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vcvtusi2ss xmm30, xmm29, {ru-sae}, eax # AVX512F
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vcvtusi2ss xmm30, xmm29, {rd-sae}, eax # AVX512F
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vcvtusi2ss xmm30, xmm29, {rz-sae}, eax # AVX512F
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vcvtusi2ss xmm30, xmm29, eax, {rn-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, eax, {ru-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, eax, {rd-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, eax, {rz-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, ebp # AVX512F
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vcvtusi2ss xmm30, xmm29, {rn-sae}, ebp # AVX512F
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vcvtusi2ss xmm30, xmm29, {ru-sae}, ebp # AVX512F
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vcvtusi2ss xmm30, xmm29, {rd-sae}, ebp # AVX512F
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vcvtusi2ss xmm30, xmm29, {rz-sae}, ebp # AVX512F
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vcvtusi2ss xmm30, xmm29, ebp, {rn-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, ebp, {ru-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, ebp, {rd-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, ebp, {rz-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, r13d # AVX512F
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vcvtusi2ss xmm30, xmm29, {rn-sae}, r13d # AVX512F
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vcvtusi2ss xmm30, xmm29, {ru-sae}, r13d # AVX512F
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vcvtusi2ss xmm30, xmm29, {rd-sae}, r13d # AVX512F
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vcvtusi2ss xmm30, xmm29, {rz-sae}, r13d # AVX512F
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vcvtusi2ss xmm30, xmm29, r13d, {rn-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, r13d, {ru-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, r13d, {rd-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, r13d, {rz-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, DWORD PTR [rcx] # AVX512F
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vcvtusi2ss xmm30, xmm29, DWORD PTR [rax+r14*8+0x1234] # AVX512F
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vcvtusi2ss xmm30, xmm29, DWORD PTR [rdx+508] # AVX512F Disp8
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@ -14448,15 +14448,15 @@ _start:
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vcvtusi2ss xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F
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vcvtusi2ss xmm30, xmm29, rax # AVX512F
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vcvtusi2ss xmm30, xmm29, {rn-sae}, rax # AVX512F
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vcvtusi2ss xmm30, xmm29, {ru-sae}, rax # AVX512F
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vcvtusi2ss xmm30, xmm29, {rd-sae}, rax # AVX512F
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vcvtusi2ss xmm30, xmm29, {rz-sae}, rax # AVX512F
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vcvtusi2ss xmm30, xmm29, rax, {rn-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, rax, {ru-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, rax, {rd-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, rax, {rz-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, r8 # AVX512F
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vcvtusi2ss xmm30, xmm29, {rn-sae}, r8 # AVX512F
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vcvtusi2ss xmm30, xmm29, {ru-sae}, r8 # AVX512F
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vcvtusi2ss xmm30, xmm29, {rd-sae}, r8 # AVX512F
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vcvtusi2ss xmm30, xmm29, {rz-sae}, r8 # AVX512F
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vcvtusi2ss xmm30, xmm29, r8, {rn-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, r8, {ru-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, r8, {rd-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, r8, {rz-sae} # AVX512F
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vcvtusi2ss xmm30, xmm29, QWORD PTR [rcx] # AVX512F
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vcvtusi2ss xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F
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vcvtusi2ss xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8
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@ -1,3 +1,8 @@
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2015-06-01 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
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* i386-tbl.h: Regenerate.
|
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|
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2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
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@ -3651,18 +3651,24 @@ vcvtsd2ss, 4, 0xF25A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|Ve
|
|||
vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
|
||||
vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
|
||||
vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
|
||||
vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
|
||||
|
||||
vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Reg32, Imm8, RegXMM, RegXMM }
|
||||
vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32, RegXMM, RegXMM }
|
||||
vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
|
||||
vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
|
||||
vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Reg32, Imm8, RegXMM, RegXMM }
|
||||
vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32, RegXMM, RegXMM }
|
||||
vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
|
||||
vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
|
||||
|
||||
vcvtss2sd, 3, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vcvtss2sd, 4, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
|
||||
|
|
|
|||
|
|
@ -36737,6 +36737,28 @@ const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtsi2sd", 4, 0xF22A, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 4, 0, 1, 0, 1, 1, 0, 0, 0, 0,
|
||||
0, 1 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtsi2ss", 3, 0xf32a, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -36816,6 +36838,28 @@ const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtsi2ss", 4, 0xF32A, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 1, 1, 0, 0, 0, 0,
|
||||
0, 1 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtsi2ss", 3, 0xF32A, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -36857,6 +36901,28 @@ const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtsi2ss", 4, 0xF32A, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 4, 0, 1, 0, 1, 1, 0, 0, 0, 0,
|
||||
0, 1 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtss2sd", 3, 0xf35a, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -76701,6 +76767,28 @@ const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtusi2sd", 4, 0xF27B, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 4, 0, 1, 0, 1, 1, 0, 0, 0, 0,
|
||||
0, 1 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtusi2ss", 3, 0xF37B, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -76742,6 +76830,28 @@ const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtusi2ss", 4, 0xF37B, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 1, 1, 0, 0, 0, 0,
|
||||
0, 1 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtusi2ss", 3, 0xF37B, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -76783,6 +76893,28 @@ const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtusi2ss", 4, 0xF37B, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 4, 0, 1, 0, 1, 1, 0, 0, 0, 0,
|
||||
0, 1 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "vcvtss2usi", 2, 0xF379, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
|
|||
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Reference in New Issue