Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a.
The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory from Armv8.4-a. gas/ * config/tc-arm.c (arm_ext_fp16_fml, fp16fml): New. (do_neon_fmac_maybe_scalar_long): Use arm_ext_fp16_fml. * doc/c-arm.texi (fp16, fp16fml): New. * testsuite/gas/arm/armv8_2-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_3-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d (fp16): Make fp16fml. include/ * opcode/arm.h: (ARM_EXT2_FP16_FML): New. (ARM_AEXT2_V8_4A): Add ARM_EXT2_FP16_FML.
This commit is contained in:
Tamar Christina
parent
c0c11fa91d
commit
01f4802036
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@ -1,3 +1,13 @@
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2017-11-15 Tamar Christina <tamar.christina@arm.com>
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* config/tc-arm.c (arm_ext_fp16_fml, fp16fml): New.
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(do_neon_fmac_maybe_scalar_long): Use arm_ext_fp16_fml.
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* doc/c-arm.texi (fp16, fp16fml): New.
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* testsuite/gas/arm/armv8_2-a-fp16.d (fp16): Make fp16fml.
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* testsuite/gas/arm/armv8_3-a-fp16.d (fp16): Make fp16fml.
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* testsuite/gas/arm/armv8_2-a-fp16-illegal.d (fp16): Make fp16fml.
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* testsuite/gas/arm/armv8_2-a-fp16-thumb2.d (fp16): Make fp16fml.
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2017-11-15 Nick Clifton <nickc@redhat.com>
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PR 15152
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@ -235,6 +235,8 @@ static const arm_feature_set arm_ext_ras =
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/* FP16 instructions. */
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static const arm_feature_set arm_ext_fp16 =
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ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
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static const arm_feature_set arm_ext_fp16_fml =
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ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML);
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static const arm_feature_set arm_ext_v8_2 =
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ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
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static const arm_feature_set arm_ext_v8_3 =
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@ -16210,7 +16212,7 @@ do_neon_fmac_maybe_scalar_long (int subtype)
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as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
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"behaviour is UNPREDICTABLE"));
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml),
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_(BAD_FP16));
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
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@ -26243,6 +26245,11 @@ static const struct arm_option_extension_value_table arm_extensions[] =
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ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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ARM_ARCH_V8_2A),
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ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
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| ARM_EXT2_FP16_FML),
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ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
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| ARM_EXT2_FP16_FML),
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ARM_ARCH_V8_2A),
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ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
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ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
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@ -178,6 +178,8 @@ The following extensions are currently supported:
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@code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
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@code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
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@code{fp} (Floating Point Extensions for v8-A architecture),
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@code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
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@code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
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@code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
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@code{iwmmxt},
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@code{iwmmxt2},
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@ -1,2 +1,2 @@
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#as: -march=armv8.2-a+fp16 -mfpu=neon-fp-armv8
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#as: -march=armv8.2-a+fp16fml -mfpu=neon-fp-armv8
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#error-output: armv8_2-a-fp16-illegal.l
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@ -1,4 +1,4 @@
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#as: -march=armv8.2-a+fp16 -mfpu=neon-fp-armv8 -mthumb
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#as: -march=armv8.2-a+fp16fml -mfpu=neon-fp-armv8 -mthumb
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#source: armv8_2-a-fp16.s
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#objdump: -d
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@ -1,4 +1,4 @@
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#as: -march=armv8.2-a+fp16 -mfpu=neon-fp-armv8
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#as: -march=armv8.2-a+fp16fml -mfpu=neon-fp-armv8
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#source: armv8_2-a-fp16.s
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#objdump: -d
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@ -1,4 +1,4 @@
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#as: -march=armv8.3-a+fp16 -mfpu=neon-fp-armv8
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#as: -march=armv8.3-a+fp16fml -mfpu=neon-fp-armv8
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#source: armv8_2-a-fp16.s
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#objdump: -d
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@ -1,3 +1,8 @@
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2017-11-15 Tamar Christina <tamar.christina@arm.com>
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* opcode/arm.h: (ARM_EXT2_FP16_FML): New.
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(ARM_AEXT2_V8_4A): Add ARM_EXT2_FP16_FML.
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2017-11-13 Jan Beulich <jbeulich@suse.com>
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* coff/pe.h (COFF_ENCODE_ALIGNMENT): Cap value to maximum one
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@ -67,6 +67,7 @@
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#define ARM_EXT2_V8_3A 0x00000100 /* ARM V8.3A. */
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#define ARM_EXT2_V8A 0x00000200 /* ARMv8-A. */
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#define ARM_EXT2_V8_4A 0x00000400 /* ARM V8.4A. */
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#define ARM_EXT2_FP16_FML 0x00000800 /* ARM V8.2A FP16-FML instructions. */
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/* Co-processor space extensions. */
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#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
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@ -157,7 +158,7 @@
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#define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A | ARM_EXT2_PAN)
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#define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A | ARM_EXT2_RAS)
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#define ARM_AEXT2_V8_3A (ARM_AEXT2_V8_2A | ARM_EXT2_V8_3A)
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#define ARM_AEXT2_V8_4A (ARM_AEXT2_V8_3A | ARM_EXT2_V8_4A)
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#define ARM_AEXT2_V8_4A (ARM_AEXT2_V8_3A | ARM_EXT2_FP16_FML | ARM_EXT2_V8_4A)
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#define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV)
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#define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M
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#define ARM_AEXT_V8M_MAIN_DSP ARM_AEXT_V7EM
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