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RISC-V: Fix assembler for c.addi, rd can be x0 

opcodes/ChangeLog:

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
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Kito Cheng 2017-03-07 19:56:40 +08:00 committed by Palmer Dabbelt
parent 9494d96366
commit 03b039a518
2 changed files with 5 additions and 1 deletions
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opcodes/ChangeLog
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@ -1,3 +1,7 @@
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
2017-03-13 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.

2
opcodes/riscv-opc.c
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@ -625,7 +625,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 },
{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 },
{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 },
{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 },
{"c.add", "C", "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 },
{"c.sub", "C", "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 },
{"c.and", "C", "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 },