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PR gas/11013

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* arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB
        and QDSUB.

        * gas/arm/arch7em.d: Update expected disassembly.
        * gas/arm/thumb32.d: Likewise.

        * config/tc-arm.c (do_t_simd2): New function.
        (insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.
This commit is contained in:
Nick Clifton 2009-12-02 20:26:30 +00:00
parent 8cebebb9a2
commit 03ee1b7f8e
7 changed files with 55 additions and 16 deletions
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7
gas/ChangeLog
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@ -1,3 +1,10 @@
2009-12-02 Nick Clifton <nickc@redhat.com>
Richard Earnshaw <rearnsha@arm.com>
PR gas/11013
* config/tc-arm.c (do_t_simd2): New function.
(insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.
2009-11-30 Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.

26
gas/config/tc-arm.c
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@ -11102,6 +11102,24 @@ do_t_simd (void)
inst.instruction |= Rm;
}
static void
do_t_simd2 (void)
{
unsigned Rd, Rn, Rm;
Rd = inst.operands[0].reg;
Rm = inst.operands[1].reg;
Rn = inst.operands[2].reg;
reject_bad_reg (Rd);
reject_bad_reg (Rn);
reject_bad_reg (Rm);
inst.instruction |= Rd << 8;
inst.instruction |= Rn << 16;
inst.instruction |= Rm;
}
static void
do_t_smc (void)
{
@ -16494,10 +16512,10 @@ static const struct asm_opcode insns[] =
TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd),
TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd),
TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd),
TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd),
TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */

7
gas/testsuite/ChangeLog
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@ -1,3 +1,10 @@
2009-12-02 Nick Clifton <nickc@redhat.com>
Richard Earnshaw <rearnsha@arm.com>
PR gas/11013
* gas/arm/arch7em.d: Update expected disassembly.
* gas/arm/thumb32.d: Likewise.
2009-11-17 Quentin Neill <quentin.neill@amd.com>
Sebastian Pop <sebastian.pop@amd.com>

8
gas/testsuite/gas/arm/arch7em.d
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@ -13,14 +13,14 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> eac0 00c0 pkhbt r0, r0, r0, lsl #3
0[0-9a-f]+ <[^>]+> eac3 0102 pkhbt r1, r3, r2
0[0-9a-f]+ <[^>]+> eac2 4163 pkhtb r1, r2, r3, asr #17
0[0-9a-f]+ <[^>]+> fa82 f183 qadd r1, r2, r3
0[0-9a-f]+ <[^>]+> fa83 f182 qadd r1, r2, r3
0[0-9a-f]+ <[^>]+> fa92 f113 qadd16 r1, r2, r3
0[0-9a-f]+ <[^>]+> fa82 f113 qadd8 r1, r2, r3
0[0-9a-f]+ <[^>]+> faa2 f113 qaddsubx r1, r2, r3
0[0-9a-f]+ <[^>]+> faa2 f113 qaddsubx r1, r2, r3
0[0-9a-f]+ <[^>]+> fa82 f193 qdadd r1, r2, r3
0[0-9a-f]+ <[^>]+> fa82 f1b3 qdsub r1, r2, r3
0[0-9a-f]+ <[^>]+> fa82 f1a3 qsub r1, r2, r3
0[0-9a-f]+ <[^>]+> fa83 f192 qdadd r1, r2, r3
0[0-9a-f]+ <[^>]+> fa83 f1b2 qdsub r1, r2, r3
0[0-9a-f]+ <[^>]+> fa83 f1a2 qsub r1, r2, r3
0[0-9a-f]+ <[^>]+> fad2 f113 qsub16 r1, r2, r3
0[0-9a-f]+ <[^>]+> fac2 f113 qsub8 r1, r2, r3
0[0-9a-f]+ <[^>]+> fae2 f113 qsubaddx r1, r2, r3

8
gas/testsuite/gas/arm/thumb32.d
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@ -695,14 +695,14 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> bd02 pop \{r1, pc\}
0[0-9a-f]+ <[^>]+> e92d 1f00 stmdb sp!, \{r8, r9, sl, fp, ip\}
0[0-9a-f]+ <[^>]+> e8bd 1f00 ldmia\.w sp!, \{r8, r9, sl, fp, ip\}
0[0-9a-f]+ <[^>]+> fa82 f183 qadd r1, r2, r3
0[0-9a-f]+ <[^>]+> fa83 f182 qadd r1, r2, r3
0[0-9a-f]+ <[^>]+> fa92 f113 qadd16 r1, r2, r3
0[0-9a-f]+ <[^>]+> fa82 f113 qadd8 r1, r2, r3
0[0-9a-f]+ <[^>]+> faa2 f113 qaddsubx r1, r2, r3
0[0-9a-f]+ <[^>]+> faa2 f113 qaddsubx r1, r2, r3
0[0-9a-f]+ <[^>]+> fa82 f193 qdadd r1, r2, r3
0[0-9a-f]+ <[^>]+> fa82 f1b3 qdsub r1, r2, r3
0[0-9a-f]+ <[^>]+> fa82 f1a3 qsub r1, r2, r3
0[0-9a-f]+ <[^>]+> fa83 f192 qdadd r1, r2, r3
0[0-9a-f]+ <[^>]+> fa83 f1b2 qdsub r1, r2, r3
0[0-9a-f]+ <[^>]+> fa83 f1a2 qsub r1, r2, r3
0[0-9a-f]+ <[^>]+> fad2 f113 qsub16 r1, r2, r3
0[0-9a-f]+ <[^>]+> fac2 f113 qsub8 r1, r2, r3
0[0-9a-f]+ <[^>]+> fae2 f113 qsubaddx r1, r2, r3

7
opcodes/ChangeLog
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@ -1,3 +1,10 @@
2009-12-02 Nick Clifton <nickc@redhat.com>
Richard Earnshaw <rearnsha@arm.com>
PR gas/11013
* arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB
and QDSUB.
2009-11-30 Massimo Ruo Roch <massimo.ruoroch@polito.it>
PR gas/11030

8
opcodes/arm-dis.c
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@ -1364,10 +1364,10 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
{ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
{ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
{ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
{ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},