[AArch64][SVE 29/32] Add new SVE core & FP register operands
SVE uses some new fields to store W, X and scalar FP registers. This patch adds corresponding operands. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd. (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd) (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core and FP register operands. * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm) (FLD_SVE_Vn): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. (aarch64_print_operand): Handle the new SVE core and FP register operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm-2.c: Likewise. * aarch64-dis-2.c: Likewise. gas/ * config/tc-aarch64.c (parse_operands): Handle the new SVE core and FP register operands.
This commit is contained in:
parent
165d495085
commit
047cd301d4
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@ -1,3 +1,8 @@
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (parse_operands): Handle the new SVE core
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and FP register operands.
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (double_precision_operand_p): New function.
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@ -5292,11 +5292,13 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_Ra:
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case AARCH64_OPND_Rt_SYS:
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case AARCH64_OPND_PAIRREG:
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case AARCH64_OPND_SVE_Rm:
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po_int_reg_or_fail (REG_TYPE_R_Z);
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break;
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case AARCH64_OPND_Rd_SP:
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case AARCH64_OPND_Rn_SP:
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case AARCH64_OPND_SVE_Rn_SP:
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po_int_reg_or_fail (REG_TYPE_R_SP);
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break;
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@ -5328,6 +5330,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_Sd:
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case AARCH64_OPND_Sn:
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case AARCH64_OPND_Sm:
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case AARCH64_OPND_SVE_VZn:
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case AARCH64_OPND_SVE_Vd:
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case AARCH64_OPND_SVE_Vm:
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case AARCH64_OPND_SVE_Vn:
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val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
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if (val == PARSE_FAIL)
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{
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@ -1,3 +1,9 @@
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
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(AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
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(AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
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@ -310,6 +310,8 @@ enum aarch64_opnd
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AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
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AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
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AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
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AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
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AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
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AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
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AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
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AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
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@ -322,6 +324,10 @@ enum aarch64_opnd
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AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
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AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
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AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
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AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
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AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
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AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
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AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
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AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
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AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
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AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
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@ -1,3 +1,16 @@
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
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and FP register operands.
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* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
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(FLD_SVE_Vn): New aarch64_field_kinds.
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* aarch64-opc.c (fields): Add corresponding entries.
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(aarch64_print_operand): Handle the new SVE core and FP register
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operands.
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* aarch64-opc-2.c: Regenerate.
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* aarch64-asm-2.c: Likewise.
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* aarch64-dis-2.c: Likewise.
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
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@ -488,13 +488,19 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 144:
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case 145:
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case 146:
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case 159:
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case 160:
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case 147:
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case 148:
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case 161:
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case 162:
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case 163:
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case 164:
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case 165:
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case 166:
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case 167:
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case 168:
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case 169:
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case 170:
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case 173:
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return aarch64_ins_regno (self, info, code, inst);
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case 12:
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return aarch64_ins_reg_extended (self, info, code, inst);
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@ -534,14 +540,14 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 71:
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case 136:
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case 138:
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case 151:
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case 152:
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case 153:
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case 154:
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case 155:
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case 156:
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case 157:
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case 158:
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case 159:
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case 160:
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return aarch64_ins_imm (self, info, code, inst);
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case 38:
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case 39:
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@ -657,16 +663,16 @@ aarch64_insert_operand (const aarch64_operand *self,
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return aarch64_ins_sve_limm_mov (self, info, code, inst);
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case 137:
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return aarch64_ins_sve_scale (self, info, code, inst);
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case 147:
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case 148:
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return aarch64_ins_sve_shlimm (self, info, code, inst);
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case 149:
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case 150:
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return aarch64_ins_sve_shlimm (self, info, code, inst);
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case 151:
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case 152:
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return aarch64_ins_sve_shrimm (self, info, code, inst);
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case 165:
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case 171:
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return aarch64_ins_sve_index (self, info, code, inst);
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case 166:
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case 168:
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case 172:
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case 174:
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return aarch64_ins_sve_reglist (self, info, code, inst);
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default: assert (0); abort ();
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}
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@ -10434,13 +10434,19 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 144:
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case 145:
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case 146:
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case 159:
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case 160:
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case 147:
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case 148:
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case 161:
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case 162:
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case 163:
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case 164:
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case 165:
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case 166:
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case 167:
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case 168:
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case 169:
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case 170:
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case 173:
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return aarch64_ext_regno (self, info, code, inst);
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case 8:
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return aarch64_ext_regrt_sysins (self, info, code, inst);
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@ -10485,14 +10491,14 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 71:
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case 136:
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case 138:
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case 151:
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case 152:
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case 153:
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case 154:
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case 155:
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case 156:
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case 157:
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case 158:
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case 159:
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case 160:
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return aarch64_ext_imm (self, info, code, inst);
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case 38:
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case 39:
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@ -10610,16 +10616,16 @@ aarch64_extract_operand (const aarch64_operand *self,
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return aarch64_ext_sve_limm_mov (self, info, code, inst);
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case 137:
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return aarch64_ext_sve_scale (self, info, code, inst);
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case 147:
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case 148:
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return aarch64_ext_sve_shlimm (self, info, code, inst);
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case 149:
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case 150:
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return aarch64_ext_sve_shlimm (self, info, code, inst);
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case 151:
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case 152:
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return aarch64_ext_sve_shrimm (self, info, code, inst);
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case 165:
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case 171:
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return aarch64_ext_sve_index (self, info, code, inst);
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case 166:
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case 168:
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case 172:
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case 174:
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return aarch64_ext_sve_reglist (self, info, code, inst);
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default: assert (0); abort ();
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}
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@ -171,6 +171,8 @@ const struct aarch64_operand aarch64_operands[] =
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{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pm}, "an SVE predicate register"},
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{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate register"},
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{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pt}, "an SVE predicate register"},
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{AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rm}, "an integer register or zero"},
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{AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"},
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@ -183,6 +185,10 @@ const struct aarch64_operand aarch64_operands[] =
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3}, "an 8-bit unsigned immediate"},
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{AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"},
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{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"},
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{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"},
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{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vn}, "a SIMD register"},
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{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_5}, "an SVE vector register"},
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{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_16}, "an SVE vector register"},
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{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"},
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@ -273,6 +273,11 @@ const aarch64_field fields[] =
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{ 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
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{ 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
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{ 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
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{ 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
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{ 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
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{ 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
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{ 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
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{ 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
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{ 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
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{ 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
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{ 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
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@ -2949,6 +2954,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
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case AARCH64_OPND_Ra:
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case AARCH64_OPND_Rt_SYS:
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case AARCH64_OPND_PAIRREG:
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case AARCH64_OPND_SVE_Rm:
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/* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
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the <ic_op>, therefore we we use opnd->present to override the
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generic optional-ness information. */
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@ -2966,6 +2972,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
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case AARCH64_OPND_Rd_SP:
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case AARCH64_OPND_Rn_SP:
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case AARCH64_OPND_SVE_Rn_SP:
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assert (opnd->qualifier == AARCH64_OPND_QLF_W
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|| opnd->qualifier == AARCH64_OPND_QLF_WSP
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|| opnd->qualifier == AARCH64_OPND_QLF_X
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case AARCH64_OPND_Sd:
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case AARCH64_OPND_Sn:
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case AARCH64_OPND_Sm:
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case AARCH64_OPND_SVE_VZn:
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case AARCH64_OPND_SVE_Vd:
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case AARCH64_OPND_SVE_Vm:
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case AARCH64_OPND_SVE_Vn:
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snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
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opnd->reg.regno);
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break;
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@ -100,6 +100,11 @@ enum aarch64_field_kind
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FLD_SVE_Pm,
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FLD_SVE_Pn,
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FLD_SVE_Pt,
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FLD_SVE_Rm,
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FLD_SVE_Rn,
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FLD_SVE_Vd,
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FLD_SVE_Vm,
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FLD_SVE_Vn,
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FLD_SVE_Za_5,
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FLD_SVE_Za_16,
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FLD_SVE_Zd,
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@ -2970,6 +2970,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
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"an SVE predicate register") \
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Y(PRED_REG, regno, "SVE_Pt", 0, F(FLD_SVE_Pt), \
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"an SVE predicate register") \
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Y(INT_REG, regno, "SVE_Rm", 0, F(FLD_SVE_Rm), \
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"an integer register or zero") \
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Y(INT_REG, regno, "SVE_Rn_SP", OPD_F_MAYBE_SP, F(FLD_SVE_Rn), \
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"an integer register or SP") \
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Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_PRED", 0, \
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F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \
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Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \
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"an 8-bit unsigned immediate") \
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Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3), \
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"an 8-bit unsigned immediate") \
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Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \
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Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register") \
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Y(SIMD_REG, regno, "SVE_Vm", 0, F(FLD_SVE_Vm), "a SIMD register") \
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Y(SIMD_REG, regno, "SVE_Vn", 0, F(FLD_SVE_Vn), "a SIMD register") \
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Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD_SVE_Za_5), \
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"an SVE vector register") \
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Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD_SVE_Za_16), \
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