* Makefile.am (CGENDIR): Set via configure.
(CGEN): New variable. (CGENFILES): object.scm renamed to cos.scm. (run-cgen): Renamed from cgen. stamp file renamed to stamp-$prefix. (stamp-m32r): Pass prefix to run-cgen. * Makefile.in: Regenerate. * cgen-asm.in: @arch@-opc.h renamed to @prefix@-opc.h. * cgen-dis.in: Ditto. * cgen-opc.in: Ditto. * cgen.sh: New args cgen,prefix. Delete args scheme,schemeflags. * configure.in: AC_SUBST cgen,cgendir. No longer look for guile. * configure: Regenerate. * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
This commit is contained in:
Doug Evans
parent
9eaac302dc
commit
0499462e76
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@ -1,6 +1,20 @@
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Wed Jul 1 09:42:07 1998 Nick Clifton <nickc@cygnus.com>
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Wed Jul 1 16:11:16 1998 Doug Evans <devans@seba.cygnus.com>
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* Makefile.in (CGENFILES): Replace object.scm with cos.scm.
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* m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
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start-sanitize-cygnus
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* Makefile.am (CGENDIR): Set via configure.
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(CGEN): New variable.
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(CGENFILES): object.scm renamed to cos.scm.
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(run-cgen): Renamed from cgen. stamp file renamed to stamp-$prefix.
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(stamp-m32r): Pass prefix to run-cgen.
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* Makefile.in: Regenerate.
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* cgen-asm.in: @arch@-opc.h renamed to @prefix@-opc.h.
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* cgen-dis.in: Ditto.
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* cgen-opc.in: Ditto.
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* cgen.sh: New args cgen,prefix. Delete args scheme,schemeflags.
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* configure.in: AC_SUBST cgen,cgendir. No longer look for guile.
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* configure: Regenerate.
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end-sanitize-cygnus
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start-sanitize-am33
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Tue Jun 30 09:59:37 1998 Jeffrey A Law (law@cygnus.com)
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@ -75,6 +75,7 @@ RANLIB = @RANLIB@
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WIN32LDFLAGS = @WIN32LDFLAGS@
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WIN32LIBADD = @WIN32LIBADD@
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archdefs = @archdefs@
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cgendir = @cgendir@
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AUTOMAKE_OPTIONS = cygnus
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@ -224,9 +225,8 @@ CLEANFILES = libopcodes.a stamp-lib dep.sed .dep .dep1 stamp-m32r
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# Sanitization must be split between assignments and rules because
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# automake splits them that way.
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SCHEME = @SCHEME@
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SCHEMEFLAGS = -s
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CGENDIR = $(srcdir)/../cgen
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CGENDIR = @cgendir@
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CGEN = @cgen@
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CGENFLAGS = -v
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CGENFILES = $(CGENDIR)/cos.scm $(CGENDIR)/utils.scm \
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@ -627,8 +627,8 @@ config.status: $(srcdir)/configure $(srcdir)/../bfd/configure.in
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# start-sanitize-cygnus
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cgen:
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$(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGENDIR) $(CGENFLAGS) $(SCHEME) $(SCHEMEFLAGS) $(arch)
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touch stamp-${arch}
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$(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGEN) $(CGENDIR) $(CGENFLAGS) $(arch) $(prefix)
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touch stamp-${prefix}
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.PHONY: cgen
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@ -1,7 +1,7 @@
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/* Generic opcode table support for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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This file is used to generate @arch@-opc.c.
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THIS FILE IS USED TO GENERATE @prefix@-opc.c.
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Copyright (C) 1998 Free Software Foundation, Inc.
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@ -18,8 +18,8 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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@ -27,7 +27,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "libiberty.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "@arch@-opc.h"
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#include "@prefix@-opc.h"
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#include "opintl.h"
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/* Look up instruction INSN_VALUE and extract its fields.
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@ -1,6 +1,6 @@
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/* Instruction description for m32r.
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This file is machine generated with CGEN.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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@ -22,8 +22,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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*/
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#ifndef m32r_OPC_H
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#define m32r_OPC_H
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#ifndef M32R_OPC_H
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#define M32R_OPC_H
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#define CGEN_ARCH m32r
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@ -51,6 +51,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
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we can't hash on everything up to the space. */
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#define CGEN_MNEMONIC_OPERANDS
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/* Maximum number of operands any insn or macro-insn has. */
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#define CGEN_MAX_INSN_OPERANDS 16
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/* Enums. */
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@ -70,6 +72,32 @@ typedef enum insn_op2 {
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, OP2_12, OP2_13, OP2_14, OP2_15
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} INSN_OP2;
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/* Enum declaration for general registers. */
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typedef enum h_gr {
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H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0
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, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
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, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
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, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
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, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
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} H_GR;
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/* Enum declaration for control registers. */
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typedef enum h_cr {
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H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
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, H_CR_BPC = 6, H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2
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, H_CR_CR3 = 3, H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6
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, H_CR_CR7 = 7, H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10
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, H_CR_CR11 = 11, H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14
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, H_CR_CR15 = 15
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} H_CR;
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/* start-sanitize-m32rx */
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/* Enum declaration for accumulators. */
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typedef enum h_accums {
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H_ACCUMS_A0, H_ACCUMS_A1
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} H_ACCUMS;
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/* end-sanitize-m32rx */
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/* Enum declaration for m32r operand types. */
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typedef enum cgen_operand_type {
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M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
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@ -87,9 +115,9 @@ typedef enum cgen_operand_type {
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/* start-sanitize-m32rx */
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, M32R_OPERAND_ACC
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/* end-sanitize-m32rx */
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, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24
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, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT
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, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
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, M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
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, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
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, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
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} CGEN_OPERAND_TYPE;
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/* Non-boolean attributes. */
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@ -123,9 +151,9 @@ typedef enum pipe_attr {
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/* Enum declaration for cgen_operand attrs. */
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typedef enum cgen_operand_attr {
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CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC
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, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT
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, CGEN_OPERAND_UNSIGNED
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CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE
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, CGEN_OPERAND_PC, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC
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, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_UNSIGNED
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} CGEN_OPERAND_ATTR;
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/* Number of non-boolean elements in cgen_operand. */
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@ -137,54 +165,37 @@ typedef enum cgen_insn_attr {
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/* start-sanitize-m32rx */
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, CGEN_INSN_PIPE
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/* end-sanitize-m32rx */
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, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL
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, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
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, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_NO_DIS
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, CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SPECIAL
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, CGEN_INSN_UNCOND_CTI
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} CGEN_INSN_ATTR;
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/* Number of non-boolean elements in cgen_insn. */
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#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
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/* Insn types are used by the simulator. */
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/* Enum declaration for m32r instruction types. */
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typedef enum cgen_insn_type {
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M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_ADD3_A
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, M32R_INSN_AND, M32R_INSN_AND3, M32R_INSN_AND3_A, M32R_INSN_OR
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, M32R_INSN_OR3, M32R_INSN_OR3_A, M32R_INSN_XOR, M32R_INSN_XOR3
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, M32R_INSN_XOR3_A, M32R_INSN_ADDI, M32R_INSN_ADDI_A, M32R_INSN_ADDV
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, M32R_INSN_ADDV3, M32R_INSN_ADDV3_A, M32R_INSN_ADDX, M32R_INSN_BC8
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, M32R_INSN_BC8_S, M32R_INSN_BC24, M32R_INSN_BC24_L, M32R_INSN_BEQ
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M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND
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, M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR
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, M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3
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, M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ
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||||
, M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
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, M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL8_S
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||||
, M32R_INSN_BL24, M32R_INSN_BL24_L
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||||
, M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24
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||||
/* start-sanitize-m32rx */
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||||
, M32R_INSN_BCL8
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/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_BCL8_S
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||||
/* end-sanitize-m32rx */
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||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_BCL24
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||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_BCL24_L
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L
|
||||
, M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24
|
||||
, M32R_INSN_BRA24_L
|
||||
, M32R_INSN_BNC8, M32R_INSN_BNC24, M32R_INSN_BNE, M32R_INSN_BRA8
|
||||
, M32R_INSN_BRA24
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_BNCL8
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_BNCL8_S
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_BNCL24
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_BNCL24_L
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPI_A, M32R_INSN_CMPU
|
||||
, M32R_INSN_CMPUI, M32R_INSN_CMPUI_A
|
||||
, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU, M32R_INSN_CMPUI
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_CMPEQ
|
||||
/* end-sanitize-m32rx */
|
||||
|
|
@ -201,15 +212,11 @@ typedef enum cgen_insn_type {
|
|||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_JNC
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_2
|
||||
, M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB, M32R_INSN_LDB_2
|
||||
, M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH, M32R_INSN_LDH_2
|
||||
, M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB, M32R_INSN_LDUB_2
|
||||
, M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH, M32R_INSN_LDUH_2
|
||||
, M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS, M32R_INSN_LD24
|
||||
, M32R_INSN_LD24_A, M32R_INSN_LDI8, M32R_INSN_LDI8_A, M32R_INSN_LDI8A
|
||||
, M32R_INSN_LDI8A_A, M32R_INSN_LDI16, M32R_INSN_LDI16A, M32R_INSN_LOCK
|
||||
, M32R_INSN_MACHI
|
||||
, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_D
|
||||
, M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH, M32R_INSN_LDH_D
|
||||
, M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH, M32R_INSN_LDUH_D
|
||||
, M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI16
|
||||
, M32R_INSN_LOCK, M32R_INSN_MACHI
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MACHI_A
|
||||
/* end-sanitize-m32rx */
|
||||
|
|
@ -247,35 +254,19 @@ typedef enum cgen_insn_type {
|
|||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
|
||||
, M32R_INSN_RAC
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RAC_D
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RAC_DS
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RAC_DSI
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_RACH
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RACH_D
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RACH_DS
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RACH_DSI
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SETH_A, M32R_INSN_SLL
|
||||
, M32R_INSN_SLL3, M32R_INSN_SLL3_A, M32R_INSN_SLLI, M32R_INSN_SLLI_A
|
||||
, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRA3_A, M32R_INSN_SRAI
|
||||
, M32R_INSN_SRAI_A, M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRL3_A
|
||||
, M32R_INSN_SRLI, M32R_INSN_SRLI_A, M32R_INSN_ST, M32R_INSN_ST_2
|
||||
, M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB, M32R_INSN_STB_2
|
||||
, M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH, M32R_INSN_STH_2
|
||||
, M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS
|
||||
, M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
|
||||
, M32R_INSN_TRAP_A, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP
|
||||
, M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3
|
||||
, M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI
|
||||
, M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST
|
||||
, M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH
|
||||
, M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB
|
||||
, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_SATB
|
||||
/* end-sanitize-m32rx */
|
||||
|
|
@ -378,9 +369,6 @@ typedef enum hw_type {
|
|||
, HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
|
||||
/* start-sanitize-m32rx */
|
||||
, HW_H_ACCUMS
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, HW_H_ABORT
|
||||
/* end-sanitize-m32rx */
|
||||
, HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE
|
||||
, HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_H_LOCK
|
||||
|
|
@ -416,7 +404,7 @@ extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
|
|||
#define CGEN_DIS_HASH_SIZE 256
|
||||
#undef CGEN_DIS_HASH
|
||||
#define X(b) (((unsigned char *) (b))[0] & 0xf0)
|
||||
#define CGEN_DIS_HASH(buffer, insn) \
|
||||
#define CGEN_DIS_HASH(buffer, value) \
|
||||
(X (buffer) | \
|
||||
(X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
|
||||
: X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
|
||||
|
|
@ -426,4 +414,4 @@ extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
|
|||
/* -- */
|
||||
|
||||
|
||||
#endif /* m32r_OPC_H */
|
||||
#endif /* M32R_OPC_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue