* config/tc-arm.c (md_assemble): Allow barrier instructions on
ARMv6-M cores. * gas/arm/archv6m.s: Add dmb, dsb, and isb. * gas/arm/archv6m.d: Likewise.
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@ -1,3 +1,8 @@
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2009-03-01 Mark Mitchell <mark@codesourcery.com>
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* config/tc-arm.c (md_assemble): Allow barrier instructions on
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ARMv6-M cores.
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2009-03-01 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
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* configure: Regenerate.
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@ -14747,7 +14747,8 @@ md_assemble (char *str)
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/* Implicit require narrow instructions on Thumb-1. This avoids
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relaxation accidentally introducing Thumb-2 instructions. */
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if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
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&& !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
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&& !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
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|| ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
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inst.size_req = 2;
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}
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@ -14805,7 +14806,8 @@ md_assemble (char *str)
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This is overly pessimistic for relaxable instructions. */
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if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
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|| inst.relax)
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&& !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
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&& !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
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|| ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
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ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
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arm_ext_v6t2);
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}
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@ -1,3 +1,8 @@
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2009-03-01 Mark Mitchell <mark@codesourcery.com>
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* gas/arm/archv6m.s: Add dmb, dsb, and isb.
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* gas/arm/archv6m.d: Likewise.
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2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
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* gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests.
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@ -13,3 +13,6 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> bf40 sev
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0[0-9a-f]+ <[^>]+> 4408 add r0, r1
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0[0-9a-f]+ <[^>]+> 46c0 nop.*
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0[0-9a-f]+ <[^>]+> f3bf 8f5f dmb sy
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0[0-9a-f]+ <[^>]+> f3bf 8f4f dsb sy
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0[0-9a-f]+ <[^>]+> f3bf 8f6f isb sy
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@ -14,3 +14,7 @@ foo:
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sev
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add r0, r0, r1
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nop
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dmb
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dsb
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isb
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