2014-07-02 Jing Yu <jingyu@google.com>
Initial patch to enable gold aarch64 backend.
This patch is just a skeleton which almost does nothing.
It does not support ILP32 now.
gold/ChangeLog:
* aarch64.cc: New file
* Makefile.am (TARGETSOURCES): Add aarch64.cc
(ALL_TARGETOBJS): Add aarch64.$(OBJEXT)
* Makefile.in: Regenerate.
* configure.tgt: Add entries for aarch64*.
* configure.ac: Likewise.
* configure: Likewise.
elfcpp/ChangeLog:
* aarch64.h: New file. New enums for aarch64-elf64 relocations.
* elfcpp.h (EM_AARCH64, SHT_AARCH64_ATTRIBUTES, PT_AARCH64_ARCHEXT,
PT_AARCH64_UNWIND): New enum constant.
This commit is contained in:
Jing Yu
Cary Coutant
parent
2b239efbec
commit
053a4d680b
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@ -1,3 +1,9 @@
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2014-07-02 Jing Yu <jingyu@google.com>
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* aarch64.h: New file. New enums for aarch64-elf64 relocations.
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* elfcpp.h (EM_AARCH64, SHT_AARCH64_ATTRIBUTES, PT_AARCH64_ARCHEXT,
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PT_AARCH64_UNWIND): New enum constant.
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2014-04-22 Christian Svensson <blue@cmd.nu>
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* elfcpp.h: Remove openrisc and or32 support.
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@ -0,0 +1,183 @@
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// aarch64.h -- ELF definitions specific to AARCH64 -*- C++ -*-
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// Copyright (C) 2014 Free Software Foundation, Inc.
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// Written by Jing Yu (jingyu@google.com)
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// This file is part of elfcpp.
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// This program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Library General Public License
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// as published by the Free Software Foundation; either version 2, or
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// (at your option) any later version.
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// In addition to the permissions in the GNU Library General Public
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// License, the Free Software Foundation gives you unlimited
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// permission to link the compiled version of this file into
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// combinations with other programs, and to distribute those
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// combinations without any restriction coming from the use of this
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// file. (The Library Public License restrictions do apply in other
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// respects; for example, they cover modification of the file, and
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/// distribution when not linked into a combined executable.)
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// This program is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Library General Public License for more details.
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// You should have received a copy of the GNU Library General Public
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// License along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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// 02110-1301, USA.
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#ifndef ELFCPP_AARCH64_H
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#define ELFCPP_AARCH64_H
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namespace elfcpp
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{
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// The relocation type information is taken from:
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//
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// ELF for the ARM 64-bit Architecture (AArch64)
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// Document number: ARM IHI 0056B, current through AArch64 ABI release 1.0
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// Date of Issue: 22nd May, 2013
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//
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enum
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{
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// Null relocation codes
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R_AARCH64_NONE = 0, // None
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withdrawn = 256, // Treat as R_AARCH64_NONE
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// Static relocations
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R_AARCH64_ABS64 = 257, // S + A
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R_AARCH64_ABS32 = 258, // S + A
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R_AARCH64_ABS16 = 259, // S + A
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R_AARCH64_PREL64 = 260, // S + A - P
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R_AARCH64_PREL32 = 261, // S + A - P
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R_AARCH64_PREL16 = 262, // S + A - P
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R_AARCH64_MOVW_UABS_G0 = 263, // S + A
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R_AARCH64_MOVW_UABS_G0_NC = 264, // S + A
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R_AARCH64_MOVW_UABS_G1 = 265, // S + A
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R_AARCH64_MOVW_UABS_G1_NC = 266, // S + A
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R_AARCH64_MOVW_UABS_G2 = 267, // S + A
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R_AARCH64_MOVW_UABS_G2_NC = 268, // S + A
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R_AARCH64_MOVW_UABS_G3 = 269, // S + A
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R_AARCH64_MOVW_SABS_G0 = 270, // S + A
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R_AARCH64_MOVW_SABS_G1 = 271, // S + A
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R_AARCH64_MOVW_SABS_G2 = 272, // S + A
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R_AARCH64_LD_PREL_LO19 = 273, // S + A - P
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R_AARCH64_ADR_PREL_LO21 = 274, // S + A - P
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R_AARCH64_ADR_PREL_PG_HI21 = 275, // Page(S+A) - Page(P)
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R_AARCH64_ADR_PREL_PG_HI21_NC = 276, // Page(S+A) - Page(P)
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R_AARCH64_ADD_ABS_LO12_NC = 277, // S + A
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R_AARCH64_LDST8_ABS_LO12_NC = 278, // S + A
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R_AARCH64_TSTBR14 = 279, // S + A - P
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R_AARCH64_CONDBR19 = 280, // S + A - P
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R_AARCH64_JUMP26 = 282, // S + A - P
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R_AARCH64_CALL26 = 283, // S + A - P
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R_AARCH64_LDST16_ABS_LO12_NC = 284, // S + A
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R_AARCH64_LDST32_ABS_LO12_NC = 285, // S + A
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R_AARCH64_LDST64_ABS_LO12_NC = 286, // S + A
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R_AARCH64_MOVW_PREL_G0 = 287, // S + A - P
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R_AARCH64_MOVW_PREL_G0_NC = 288, // S + A - P
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R_AARCH64_MOVW_PREL_G1 = 289, // S + A - P
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R_AARCH64_MOVW_PREL_G1_NC = 290, // S + A - P
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R_AARCH64_MOVW_PREL_G2 = 291, // S + A - P
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R_AARCH64_MOVW_PREL_G2_NC = 292, // S + A - P
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R_AARCH64_MOVW_PREL_G3 = 293, // S + A - P
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R_AARCH64_LDST128_ABS_LO12_NC = 299, // S + A
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R_AARCH64_MOVW_GOTOFF_G0 = 300, // G(GDAT(S+A))-GOT
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R_AARCH64_MOVW_GOTOFF_G0_NC = 301, // G(GDAT(S+A))-GOT
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R_AARCH64_MOVW_GOTOFF_G1 = 302, // G(GDAT(S+A))-GOT
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R_AARCH64_MOVW_GOTOFF_G1_NC = 303, // G(GDAT(S+A))-GOT
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R_AARCH64_MOVW_GOTOFF_G2 = 304, // G(GDAT(S+A))-GOT
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R_AARCH64_MOVW_GOTOFF_G2_NC = 305, // G(GDAT(S+A))-GOT
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R_AARCH64_MOVW_GOTOFF_G3 = 306, // G(GDAT(S+A))-GOT
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R_AARCH64_GOTREL64 = 307, // S + A - GOT
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R_AARCH64_GOTREL32 = 308, // S + A - GOT
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R_AARCH64_GOT_LD_PREL19 = 309, // G(GDAT(S+A))-P
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R_AARCH64_LD64_GOTOFF_LO15 = 310, // G(GDAT(S+A))-GOT
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R_AARCH64_ADR_GOT_PAGE = 311, // Page(G(GDAT(S+A)))-Page(P)
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R_AARCH64_LD64_GOT_LO12_NC = 312, // G(GDAT(S+A))
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R_AARCH64_LD64_GOTPAGE_LO15 = 313, // G(GDAT(S+A))-Page(GOT)
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// Relocations for thread-local storage
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R_AARCH64_TLSGD_ADR_PREL21 = 512, // G(GTLSIDX(S,A)) - P
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R_AARCH64_TLSGD_ADR_PAGE21 = 513, // Page(G(GTLSIDX(S,A)))-Page(P)
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R_AARCH64_TLSGD_ADD_LO12_NC = 514, // G(GTLSICX(S,A))
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R_AARCH64_TLSGD_MOVW_G1 = 515, // G(GTLSIDX(S,A)) - GOT
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R_AARCH64_TLSGD_MOVW_G0_NC = 516, // G(GTLSIDX(S,A)) - GOT
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R_AARCH64_TLSLD_ADR_PREL21 = 517, // G(GLDM(S)) - P
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R_AARCH64_TLSLD_ADR_PAGE21 = 518, // Page(G(GLDM(S))) - Page(P)
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R_AARCH64_TLSLD_ADD_LO12_NC = 519, // G(GLDM(S))
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R_AARCH64_TLSLD_MOVW_G1 = 520, // G(GLDM(S)) - GOT
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R_AARCH64_TLSLD_MOVW_G0_NC = 521, // G(GLDM(S)) - GOT
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R_AARCH64_TLSLD_LD_PREL19 = 522, // G(GLDM(S)) - P
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R_AARCH64_TLSLD_MOVW_DTPREL_G2 = 523, // DTPREL(S+A)
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R_AARCH64_TLSLD_MOVW_DTPREL_G1 = 524, // DTPREL(S+A)
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R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC = 525, // DTPREL(S+A)
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R_AARCH64_TLSLD_MOVW_DTPREL_G0 = 526, // DTPREL(S+A)
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R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC = 527, // DTPREL(S+A)
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R_AARCH64_TLSLD_ADD_DTPREL_HI12 = 528, // DTPREL(S+A)
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R_AARCH64_TLSLD_ADD_DTPREL_LO12 = 529, // DTPREL(S+A)
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R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC = 530, // DTPREL(S+A)
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R_AARCH64_TLSLD_LDST8_DTPREL_LO12 = 531, // DTPREL(S+A)
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R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC = 532, // DTPREL(S+A)
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R_AARCH64_TLSLD_LDST16_DTPREL_LO12 = 533, // DTPREL(S+A)
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R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC = 534, // DTPREL(S+A)
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R_AARCH64_TLSLD_LDST32_DTPREL_LO12 = 535, // DTPREL(S+A)
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R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC = 536, // DTPREL(S+A)
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R_AARCH64_TLSLD_LDST64_DTPREL_LO12 = 537, // DTPREL(S+A)
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R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC = 538, // DTPREL(S+A)
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R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 = 539, // G(GTPREL(S+A)) - GOT
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R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC = 540, // G(GTPREL(S+A)) - GOT
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R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 = 541, // Page(G(GTPREL(S+A)))-Page(P)
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R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC = 542, // G(GTPREL(S+A))
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R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 = 543, // G(GTPREL(S+A)) - P
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R_AARCH64_TLSLE_MOVW_TPREL_G2 = 544, // TPREL(S+A)
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R_AARCH64_TLSLE_MOVW_TPREL_G1 = 545, // TPREL(S+A)
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R_AARCH64_TLSLE_MOVW_TPREL_G1_NC = 546, // TPREL(S+A)
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R_AARCH64_TLSLE_MOVW_TPREL_G0 = 547, // TPREL(S+A)
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R_AARCH64_TLSLE_MOVW_TPREL_G0_NC = 548, // TPREL(S+A)
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R_AARCH64_TLSLE_ADD_TPREL_HI12 = 549, // TPREL(S+A)
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R_AARCH64_TLSLE_ADD_TPREL_LO12 = 550, // TPREL(S+A)
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R_AARCH64_TLSLE_ADD_TPREL_LO12_NC = 551, // TPREL(S+A)
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R_AARCH64_TLSLE_LDST8_TPREL_LO12 = 552, // TPREL(S+A)
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R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC = 553, // TPREL(S+A)
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R_AARCH64_TLSLE_LDST16_TPREL_LO12 = 554, // TPREL(S+A)
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R_AARCH64_TLSLE_LSDT16_TPREL_LO12_NC = 555, // TPREL(S+A)
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R_AARCH64_TLSLE_LDST32_TPREL_LO12 = 556, // TPREL(S+A)
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R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC = 557, // TPREL(S+A)
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R_AARCH64_TLSLE_LDST64_TPREL_LO12 = 558, // TPREL(S+A)
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R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC = 559, // TPREL(S+A)
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R_AARCH64_TLSDESC_LD_PREL19 = 560, // G(GTLSDESC(S+A)) - P
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R_AARCH64_TLSDESC_ADR_PREL21 = 561, // G(GTLSDESC(S+A)) - P
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R_AARCH64_TLSDESC_ADR_PAGE21 = 562, // Page(G(GTLSDESC(S+A)))-Page(P)
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R_AARCH64_TLSDESC_LD64_LO12 = 563, // G(GTLSDESC(S+A))
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R_AARCH64_TLSDESC_ADD_LO12 = 564, // G(GTLSDESC(S+A))
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R_AARCH64_TLSDESC_OFF_G1 = 565, // G(GTLSDESC(S+A)) - GOT
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R_AARCH64_TLSDESC_OFF_G0_NC = 566, // G(GTLSDESC(S+A)) - GOT
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R_AARCH64_TLSDESC_LDR = 567, // None
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R_AARCH64_TLSDESC_ADD = 568, // None
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R_AARCH64_TLSDESC_CALL = 569, // None
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R_AARCH64_TLSLE_LDST128_TPREL_LO12 = 570, // TPREL(S+A)
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R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC = 571, // TPREL(S+A)
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R_AARCH64_TLSLD_LDST128_DTPREL_LO12 = 572, // DTPREL(S+A)
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R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC = 573, // DTPREL(S+A)
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// Dynamic relocations
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R_AARCH64_COPY = 1024,
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R_AARCH64_GLOB_DAT = 1025, // S + A
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R_AARCH64_JUMP_SLOT = 1026, // S + A
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R_AARCH64_RELATIVE = 1027, // Delta(S) + A
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R_AARCH64_TLS_DTPREL64 = 1028, // DTPREL(S+A)
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R_AARCH64_TLS_DTPMOD64 = 1029, // LDM(S)
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R_AARCH64_TLS_TPREL64 = 1030, // TPREL(S+A)
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R_AARCH64_TLSDESC = 1031, // TLSDESC(S+A)
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R_AARCH64_IRELATIVE = 1032, // Indirect(Delta(S) + A)
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};
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} // End namespace elfcpp.
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#endif // !defined(ELFCPP_AARCH64_H)
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@ -268,6 +268,7 @@ enum EM
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EM_UNICORE = 110,
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EM_ALTERA_NIOS2 = 113,
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EM_CRX = 114,
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EM_AARCH64 = 183,
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EM_TILEGX = 191,
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// The Morph MT.
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EM_MT = 0x2530,
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@ -406,6 +407,9 @@ enum SHT
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// Section contains miscellaneous options.
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SHT_MIPS_OPTIONS = 0x7000000d,
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// AARCH64-specific section type.
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SHT_AARCH64_ATTRIBUTES = 0x70000003,
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// Link editor is to sort the entries in this section based on the
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// address specified in the associated symbol table entry.
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SHT_ORDERED = 0x7fffffff
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@ -490,7 +494,11 @@ enum PT
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// Runtime procedure table.
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PT_MIPS_RTPROC = 0x70000001,
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// .MIPS.options section.
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PT_MIPS_OPTIONS = 0x70000002
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PT_MIPS_OPTIONS = 0x70000002,
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// Platform architecture compatibility information
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PT_AARCH64_ARCHEXT = 0x70000000,
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// Exception unwind tables
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PT_AARCH64_UNWIND = 0x70000001
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};
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// The valid bit flags found in the Phdr p_flags field.
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@ -1,3 +1,13 @@
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2014-07-02 Jing Yu <jingyu@google.com>
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* aarch64.cc: New file
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* Makefile.am (TARGETSOURCES): Add aarch64.cc
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(ALL_TARGETOBJS): Add aarch64.$(OBJEXT)
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* Makefile.in: Regenerate.
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* configure.tgt: Add entries for aarch64*.
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* configure.ac: Likewise.
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* configure: Likewise.
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2014-06-27 Alan Modra <amodra@gmail.com>
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* symtab.cc (Symbol::should_add_dynsym_entry): Don't make inline.
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@ -164,11 +164,12 @@ EXTRA_DIST = yyscript.c yyscript.h
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TARGETSOURCES = \
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i386.cc x86_64.cc sparc.cc powerpc.cc arm.cc arm-reloc-property.cc tilegx.cc \
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mips.cc
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mips.cc aarch64.cc
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ALL_TARGETOBJS = \
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i386.$(OBJEXT) x86_64.$(OBJEXT) sparc.$(OBJEXT) powerpc.$(OBJEXT) \
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arm.$(OBJEXT) arm-reloc-property.$(OBJEXT) tilegx.$(OBJEXT) mips.$(OBJEXT)
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arm.$(OBJEXT) arm-reloc-property.$(OBJEXT) tilegx.$(OBJEXT) \
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mips.$(OBJEXT) aarch64.$(OBJEXT)
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libgold_a_SOURCES = $(CCFILES) $(HFILES) $(YFILES) $(DEFFILES)
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libgold_a_LIBADD = $(LIBOBJS)
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@ -533,11 +533,12 @@ DEFFILES = arm-reloc.def
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EXTRA_DIST = yyscript.c yyscript.h
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TARGETSOURCES = \
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i386.cc x86_64.cc sparc.cc powerpc.cc arm.cc arm-reloc-property.cc tilegx.cc \
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mips.cc
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mips.cc aarch64.cc
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ALL_TARGETOBJS = \
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i386.$(OBJEXT) x86_64.$(OBJEXT) sparc.$(OBJEXT) powerpc.$(OBJEXT) \
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arm.$(OBJEXT) arm-reloc-property.$(OBJEXT) tilegx.$(OBJEXT) mips.$(OBJEXT)
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arm.$(OBJEXT) arm-reloc-property.$(OBJEXT) tilegx.$(OBJEXT) \
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mips.$(OBJEXT) aarch64.$(OBJEXT)
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libgold_a_SOURCES = $(CCFILES) $(HFILES) $(YFILES) $(DEFFILES)
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libgold_a_LIBADD = $(LIBOBJS)
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@ -761,6 +762,7 @@ distclean-compile:
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@AMDEP_TRUE@@am__include@ @am__quote@$(DEPDIR)/ftruncate.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@$(DEPDIR)/mremap.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@$(DEPDIR)/pread.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/archive.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm-reloc-property.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm.Po@am__quote@
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File diff suppressed because it is too large
Load Diff
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@ -698,6 +698,8 @@ DEFAULT_TARGET_I386_FALSE
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DEFAULT_TARGET_I386_TRUE
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DEFAULT_TARGET_ARM_FALSE
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DEFAULT_TARGET_ARM_TRUE
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DEFAULT_TARGET_AARCH64_FALSE
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DEFAULT_TARGET_AARCH64_TRUE
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PLUGINS_FALSE
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PLUGINS_TRUE
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THREADS_FALSE
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@ -3433,6 +3435,14 @@ for targ in $target $canon_targets; do
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default_big_endian=$targ_big_endian
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default_osabi=$targ_osabi
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|
||||
if test "$targ_obj" = "aarch64"; then
|
||||
DEFAULT_TARGET_AARCH64_TRUE=
|
||||
DEFAULT_TARGET_AARCH64_FALSE='#'
|
||||
else
|
||||
DEFAULT_TARGET_AARCH64_TRUE='#'
|
||||
DEFAULT_TARGET_AARCH64_FALSE=
|
||||
fi
|
||||
|
||||
if test "$targ_obj" = "arm"; then
|
||||
DEFAULT_TARGET_ARM_TRUE=
|
||||
DEFAULT_TARGET_ARM_FALSE='#'
|
||||
|
|
@ -7777,6 +7787,10 @@ if test -z "${PLUGINS_TRUE}" && test -z "${PLUGINS_FALSE}"; then
|
|||
as_fn_error "conditional \"PLUGINS\" was never defined.
|
||||
Usually this means the macro was only invoked conditionally." "$LINENO" 5
|
||||
fi
|
||||
if test -z "${DEFAULT_TARGET_AARCH64_TRUE}" && test -z "${DEFAULT_TARGET_AARCH64_FALSE}"; then
|
||||
as_fn_error "conditional \"DEFAULT_TARGET_AARCH64\" was never defined.
|
||||
Usually this means the macro was only invoked conditionally." "$LINENO" 5
|
||||
fi
|
||||
if test -z "${DEFAULT_TARGET_ARM_TRUE}" && test -z "${DEFAULT_TARGET_ARM_FALSE}"; then
|
||||
as_fn_error "conditional \"DEFAULT_TARGET_ARM\" was never defined.
|
||||
Usually this means the macro was only invoked conditionally." "$LINENO" 5
|
||||
|
|
|
|||
|
|
@ -199,6 +199,7 @@ for targ in $target $canon_targets; do
|
|||
default_big_endian=$targ_big_endian
|
||||
default_osabi=$targ_osabi
|
||||
|
||||
AM_CONDITIONAL(DEFAULT_TARGET_AARCH64, test "$targ_obj" = "aarch64")
|
||||
AM_CONDITIONAL(DEFAULT_TARGET_ARM, test "$targ_obj" = "arm")
|
||||
AM_CONDITIONAL(DEFAULT_TARGET_I386, test "$targ_obj" = "i386")
|
||||
AM_CONDITIONAL(DEFAULT_TARGET_POWERPC, test "$targ_obj" = "powerpc")
|
||||
|
|
|
|||
|
|
@ -144,6 +144,14 @@ arm*-*-*)
|
|||
targ_big_endian=false
|
||||
targ_extra_big_endian=true
|
||||
;;
|
||||
aarch64*-*)
|
||||
targ_obj=aarch64
|
||||
targ_machine=EM_AARCH64
|
||||
targ_size=64
|
||||
targ_extra_size=32
|
||||
targ_big_endian=false
|
||||
targ_extra_big_endian=true
|
||||
;;
|
||||
mips*el*-*-*|mips*le*-*-*)
|
||||
targ_obj=mips
|
||||
targ_machine=EM_MIPS_RS3_LE
|
||||
|
|
|
|||
Loading…
Reference in New Issue