gas/
* config/tc-ppc.c (pre_defined_registers): Add "f32" to "f63",
"f.32" to "f.63", "vs0" to "vs63" and "vs.0" to "vs.63".
(parse_cpu): Extend -mpower7 to accept power7 and isel instructions.
gas/testsuite/
* gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests.
* gas/ppc/e500mc.s: Likewise.
* gas/ppc/power6.d ("cdtbcd", "cbcdtd", "addg6s"): Add tests.
* gas/ppc/power6.s: Likewise.
* gas/ppc/power7.d ("lfdpx", "mffgpr", "mftgpr"): Remove invalid tests.
("wait", "waitsrv", "waitimpl", "divwe", "divwe.", "divweo", "divweo.",
"divweu", "divweu.", "divweuo", "divweuo.", "bpermd", "popcntw",
"popcntd", "ldbrx", "stdbrx", "lfiwzx", "lfiwzx", "fcfids", "fcfids.",
"fcfidus", "fcfidus.", "fctiwu", "fctiwu.", "fctiwuz", "fctiwuz.",
"fctidu", "fctidu.", "fctiduz", "fctiduz.", "fcfidu", "fcfidu.",
"ftdiv", "ftdiv", "ftsqrt", "ftsqrt", "dcbtt", "dcbtstt", "dcffix",
"dcffix.", "lbarx", "lbarx", "lbarx", "lharx", "lharx", "lharx",
"stbcx.", "sthcx.", "fre", "fre.", "fres", "fres.", "frsqrte",
"frsqrte.", "frsqrtes", "frsqrtes.", "isel"): Add tests.
* gas/ppc/power7.s: Likewise.
* gas/ppc/vsx.d: New test.
* gas/ppc/vsx.s: Likewise.
* gas/ppc/ppc.exp: Run it.
include/opcode/
* ppc.h (PPC_OPCODE_POWER7): New.
opcodes/
* ppc-dis.c (powerpc_init_dialect): Extend -Mpower7 to disassemble
the power7 and the isel instructions.
* ppc-opc.c (insert_xc6, extract_xc6): New static functions.
(insert_dm, extract_dm): Likewise.
(XB6): Update comment to include XX2 form.
(WC, XC6, SHW, DMEX, UIM, XX2, XX3RC, XX4, XX2_MASK, XX2UIM_MASK,
XX2BF_MASK, XX3BF_MASK, XX3SHW_MASK, XX4_MASK, XWC_MASK, POWER7): New.
(RemoveXX3DM): Delete.
(powerpc_opcodes): <"lfdp", "lfdpx", "mcrxr", "mftb", "mffgpr",
"mftgpr">: Deprecate for POWER7.
<"fres", "fres.", "frsqrtes", "frsqrtes.", "fre", "fre.", "frsqrte",
"frsqrte.">: Deprecate the three operand form and enable the two
operand form for POWER7 and later.
<"wait">: Extend to accept optional parameter. Enable for POWER7.
<"waitsrv", "waitimpl">: Add extended opcodes.
<"ldbrx", "stdbrx">: Enable for POWER7.
<"cdtbcd", "cbcdtd", "addg6s">: Add POWER6 opcodes.
<"bpermd", "dcbtstt", "dcbtt", "dcffix.", "dcffix", "divde.", "divde",
"divdeo.", "divdeo", "divdeu.", "divdeu", "divdeuo.", "divdeuo",
"divwe.", "divwe", "divweo.", "divweo", "divweu.", "divweu", "divweuo.",
"divweuo", "fcfids.", "fcfids", "fcfidu.", "fcfidu", "fcfidus.",
"fcfidus", "fctidu.", "fctidu", "fctiduz.", "fctiduz", "fctiwu.",
"fctiwu", "fctiwuz.", "fctiwuz", "ftdiv", "ftsqrt", "lbarx", "lfiwzx",
"lharx", "popcntd", "popcntw", "stbcx.", "sthcx.">: Add POWER7 opcodes.
<"lxsdux", "lxsdx", "lxvdsx", "lxvw4ux", "lxvw4x", "stxsdux", "stxsdx",
"stxvw4ux", "stxvw4x", "xsabsdp", "xsadddp", "xscmpodp", "xscmpudp",
"xscpsgndp", "xscvdpsp", "xscvdpsxds", "xscvdpsxws", "xscvdpuxds",
"xscvdpuxws", "xscvspdp", "xscvsxddp", "xscvuxddp", "xsdivdp",
"xsmaddadp", "xsmaddmdp", "xsmaxdp", "xsmindp", "xsmsubadp",
"xsmsubmdp", "xsmuldp", "xsnabsdp", "xsnegdp", "xsnmaddadp",
"xsnmaddmdp", "xsnmsubadp", "xsnmsubmdp", "xsrdpi", "xsrdpic",
"xsrdpim", "xsrdpip", "xsrdpiz", "xsredp", "xsrsqrtedp", "xssqrtdp",
"xssubdp", "xstdivdp", "xstsqrtdp", "xvabsdp", "xvabssp", "xvadddp",
"xvaddsp", "xvcmpeqdp.", "xvcmpeqdp", "xvcmpeqsp.", "xvcmpeqsp",
"xvcmpgedp.", "xvcmpgedp", "xvcmpgesp.", "xvcmpgesp", "xvcmpgtdp.",
"xvcmpgtdp", "xvcmpgtsp.", "xvcmpgtsp", "xvcpsgnsp", "xvcvdpsp",
"xvcvdpsxds", "xvcvdpsxws", "xvcvdpuxds", "xvcvdpuxws", "xvcvspdp",
"xvcvspsxds", "xvcvspsxws", "xvcvspuxds", "xvcvspuxws", "xvcvsxddp",
"xvcvsxdsp", "xvcvsxwdp", "xvcvsxwsp", "xvcvuxddp", "xvcvuxdsp",
"xvcvuxwdp", "xvcvuxwsp", "xvdivdp", "xvdivsp", "xvmaddadp",
"xvmaddasp", "xvmaddmdp", "xvmaddmsp", "xvmaxdp", "xvmaxsp",
"xvmindp", "xvminsp", "xvmovsp", "xvmsubadp", "xvmsubasp", "xvmsubmdp",
"xvmsubmsp", "xvmuldp", "xvmulsp", "xvnabsdp", "xvnabssp", "xvnegdp",
"xvnegsp", "xvnmaddadp", "xvnmaddasp", "xvnmaddmdp", "xvnmaddmsp",
"xvnmsubadp", "xvnmsubasp", "xvnmsubmdp", "xvnmsubmsp", "xvrdpi",
"xvrdpic", "xvrdpim", "xvrdpip", "xvrdpiz", "xvredp", "xvresp",
"xvrspi", "xvrspic", "xvrspim", "xvrspip", "xvrspiz", "xvrsqrtedp",
"xvrsqrtesp", "xvsqrtdp", "xvsqrtsp", "xvsubdp", "xvsubsp", "xvtdivdp",
"xvtdivsp", "xvtsqrtdp", "xvtsqrtsp", "xxland", "xxlandc", "xxlnor",
"xxlor", "xxlxor", "xxmrghw", "xxmrglw", "xxsel", "xxsldwi", "xxspltd",
"xxspltw", "xxswapd">: Add VSX opcodes.
This commit is contained in:
Peter Bergner
parent
83390453c3
commit
066be9f7bd
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@ -1,3 +1,9 @@
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2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
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* config/tc-ppc.c (pre_defined_registers): Add "f32" to "f63",
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"f.32" to "f.63", "vs0" to "vs63" and "vs.0" to "vs.63".
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(parse_cpu): Extend -mpower7 to accept power7 and isel instructions.
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2009-02-25 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (fits_in_imm4): Removed.
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@ -358,9 +358,42 @@ static const struct pd_reg pre_defined_registers[] =
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{ "f.3", 3 },
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{ "f.30", 30 },
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{ "f.31", 31 },
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{ "f.32", 32 }, /* Extended floating point scalar registers (ISA 2.06). */
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{ "f.33", 33 },
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{ "f.34", 34 },
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{ "f.35", 35 },
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{ "f.36", 36 },
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{ "f.37", 37 },
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{ "f.38", 38 },
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{ "f.39", 39 },
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{ "f.4", 4 },
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{ "f.40", 40 },
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{ "f.41", 41 },
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{ "f.42", 42 },
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{ "f.43", 43 },
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{ "f.44", 44 },
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{ "f.45", 45 },
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{ "f.46", 46 },
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{ "f.47", 47 },
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{ "f.48", 48 },
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{ "f.49", 49 },
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{ "f.5", 5 },
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{ "f.50", 50 },
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{ "f.51", 51 },
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{ "f.52", 52 },
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{ "f.53", 53 },
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{ "f.54", 54 },
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{ "f.55", 55 },
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{ "f.56", 56 },
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{ "f.57", 57 },
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{ "f.58", 58 },
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{ "f.59", 59 },
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{ "f.6", 6 },
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{ "f.60", 60 },
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{ "f.61", 61 },
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{ "f.62", 62 },
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{ "f.63", 63 },
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{ "f.7", 7 },
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{ "f.8", 8 },
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{ "f.9", 9 },
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@ -391,9 +424,42 @@ static const struct pd_reg pre_defined_registers[] =
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{ "f3", 3 },
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{ "f30", 30 },
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{ "f31", 31 },
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{ "f32", 32 }, /* Extended floating point scalar registers (ISA 2.06). */
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{ "f33", 33 },
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{ "f34", 34 },
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{ "f35", 35 },
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{ "f36", 36 },
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{ "f37", 37 },
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{ "f38", 38 },
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{ "f39", 39 },
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{ "f4", 4 },
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{ "f40", 40 },
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{ "f41", 41 },
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{ "f42", 42 },
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{ "f43", 43 },
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{ "f44", 44 },
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{ "f45", 45 },
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{ "f46", 46 },
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{ "f47", 47 },
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{ "f48", 48 },
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{ "f49", 49 },
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{ "f5", 5 },
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{ "f50", 50 },
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{ "f51", 51 },
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{ "f52", 52 },
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{ "f53", 53 },
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{ "f54", 54 },
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{ "f55", 55 },
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{ "f56", 56 },
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{ "f57", 57 },
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{ "f58", 58 },
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{ "f59", 59 },
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{ "f6", 6 },
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{ "f60", 60 },
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{ "f61", 61 },
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{ "f62", 62 },
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{ "f63", 63 },
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{ "f7", 7 },
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{ "f8", 8 },
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{ "f9", 9 },
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@ -501,7 +567,7 @@ static const struct pd_reg pre_defined_registers[] =
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{ "srr0", 26 }, /* Machine Status Save/Restore Register 0 */
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{ "srr1", 27 }, /* Machine Status Save/Restore Register 1 */
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{ "v.0", 0 }, /* Vector registers */
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{ "v.0", 0 }, /* Vector (Altivec/VMX) registers */
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{ "v.1", 1 },
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{ "v.10", 10 },
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{ "v.11", 11 },
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@ -567,6 +633,136 @@ static const struct pd_reg pre_defined_registers[] =
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{ "v8", 8 },
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{ "v9", 9 },
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{ "vs.0", 0 }, /* Vector Scalar (VSX) registers (ISA 2.06). */
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{ "vs.1", 1 },
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{ "vs.10", 10 },
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{ "vs.11", 11 },
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{ "vs.12", 12 },
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{ "vs.13", 13 },
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{ "vs.14", 14 },
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{ "vs.15", 15 },
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{ "vs.16", 16 },
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{ "vs.17", 17 },
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{ "vs.18", 18 },
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{ "vs.19", 19 },
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{ "vs.2", 2 },
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{ "vs.20", 20 },
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{ "vs.21", 21 },
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{ "vs.22", 22 },
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{ "vs.23", 23 },
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{ "vs.24", 24 },
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{ "vs.25", 25 },
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{ "vs.26", 26 },
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{ "vs.27", 27 },
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{ "vs.28", 28 },
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{ "vs.29", 29 },
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{ "vs.3", 3 },
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{ "vs.30", 30 },
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{ "vs.31", 31 },
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{ "vs.32", 32 },
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{ "vs.33", 33 },
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{ "vs.34", 34 },
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{ "vs.35", 35 },
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{ "vs.36", 36 },
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{ "vs.37", 37 },
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{ "vs.38", 38 },
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{ "vs.39", 39 },
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{ "vs.4", 4 },
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{ "vs.40", 40 },
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{ "vs.41", 41 },
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{ "vs.42", 42 },
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{ "vs.43", 43 },
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{ "vs.44", 44 },
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{ "vs.45", 45 },
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{ "vs.46", 46 },
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{ "vs.47", 47 },
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{ "vs.48", 48 },
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{ "vs.49", 49 },
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{ "vs.5", 5 },
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{ "vs.50", 50 },
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{ "vs.51", 51 },
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{ "vs.52", 52 },
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{ "vs.53", 53 },
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{ "vs.54", 54 },
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{ "vs.55", 55 },
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{ "vs.56", 56 },
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{ "vs.57", 57 },
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{ "vs.58", 58 },
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{ "vs.59", 59 },
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{ "vs.6", 6 },
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{ "vs.60", 60 },
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{ "vs.61", 61 },
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{ "vs.62", 62 },
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{ "vs.63", 63 },
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{ "vs.7", 7 },
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{ "vs.8", 8 },
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{ "vs.9", 9 },
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{ "vs0", 0 },
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{ "vs1", 1 },
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{ "vs10", 10 },
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{ "vs11", 11 },
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{ "vs12", 12 },
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{ "vs13", 13 },
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{ "vs14", 14 },
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{ "vs15", 15 },
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{ "vs16", 16 },
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{ "vs17", 17 },
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{ "vs18", 18 },
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{ "vs19", 19 },
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{ "vs2", 2 },
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{ "vs20", 20 },
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{ "vs21", 21 },
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{ "vs22", 22 },
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{ "vs23", 23 },
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{ "vs24", 24 },
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{ "vs25", 25 },
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{ "vs26", 26 },
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{ "vs27", 27 },
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{ "vs28", 28 },
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{ "vs29", 29 },
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{ "vs3", 3 },
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{ "vs30", 30 },
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{ "vs31", 31 },
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{ "vs32", 32 },
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{ "vs33", 33 },
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{ "vs34", 34 },
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{ "vs35", 35 },
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{ "vs36", 36 },
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{ "vs37", 37 },
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{ "vs38", 38 },
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{ "vs39", 39 },
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{ "vs4", 4 },
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{ "vs40", 40 },
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{ "vs41", 41 },
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{ "vs42", 42 },
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{ "vs43", 43 },
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{ "vs44", 44 },
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{ "vs45", 45 },
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{ "vs46", 46 },
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{ "vs47", 47 },
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{ "vs48", 48 },
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{ "vs49", 49 },
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{ "vs5", 5 },
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{ "vs50", 50 },
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{ "vs51", 51 },
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{ "vs52", 52 },
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{ "vs53", 53 },
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{ "vs54", 54 },
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{ "vs55", 55 },
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{ "vs56", 56 },
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{ "vs57", 57 },
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{ "vs58", 58 },
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{ "vs59", 59 },
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{ "vs6", 6 },
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{ "vs60", 60 },
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{ "vs61", 61 },
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{ "vs62", 62 },
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{ "vs63", 63 },
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{ "vs7", 7 },
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{ "vs8", 8 },
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{ "vs9", 9 },
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{ "xer", 1 },
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};
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@ -940,8 +1136,9 @@ parse_cpu (const char *arg)
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else if (strcmp (arg, "power7") == 0)
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{
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ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
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| PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
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| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
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| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX);
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}
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else if (strcmp (arg, "cell") == 0)
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@ -1,3 +1,24 @@
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2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
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* gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests.
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* gas/ppc/e500mc.s: Likewise.
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* gas/ppc/power6.d ("cdtbcd", "cbcdtd", "addg6s"): Add tests.
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* gas/ppc/power6.s: Likewise.
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* gas/ppc/power7.d ("lfdpx", "mffgpr", "mftgpr"): Remove invalid tests.
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("wait", "waitsrv", "waitimpl", "divwe", "divwe.", "divweo", "divweo.",
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"divweu", "divweu.", "divweuo", "divweuo.", "bpermd", "popcntw",
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"popcntd", "ldbrx", "stdbrx", "lfiwzx", "lfiwzx", "fcfids", "fcfids.",
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"fcfidus", "fcfidus.", "fctiwu", "fctiwu.", "fctiwuz", "fctiwuz.",
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"fctidu", "fctidu.", "fctiduz", "fctiduz.", "fcfidu", "fcfidu.",
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"ftdiv", "ftdiv", "ftsqrt", "ftsqrt", "dcbtt", "dcbtstt", "dcffix",
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"dcffix.", "lbarx", "lbarx", "lbarx", "lharx", "lharx", "lharx",
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"stbcx.", "sthcx.", "fre", "fre.", "fres", "fres.", "frsqrte",
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"frsqrte.", "frsqrtes", "frsqrtes.", "isel"): Add tests.
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* gas/ppc/power7.s: Likewise.
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* gas/ppc/vsx.d: New test.
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* gas/ppc/vsx.s: Likewise.
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* gas/ppc/ppc.exp: Run it.
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2009-02-23 Mark Mitchell <mark@codesourcery.com>
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* gas/arm/thumb2_bad_reg.s: Update to allow R13 as second argument
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@ -6,7 +6,7 @@
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Disassembly of section \.text:
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0+0000000 <start>:
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0+00 <start>:
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0: 4c 00 00 4e rfdi
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4: 4c 00 00 cc rfgi
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8: 4c 1f f9 8c dnh 0,1023
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@ -14,38 +14,43 @@ Disassembly of section \.text:
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10: 7c 09 57 be icbiep r9,r10
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14: 7c 00 69 dc msgclr r13
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18: 7c 00 71 9c msgsnd r14
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1c: 7c 00 00 7c wait
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20: 7f 9c e3 78 mdors
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24: 7c 00 02 1c ehpriv
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28: 7c 18 cb c6 dsn r24,r25
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2c: 7c 22 18 be lbepx r1,r2,r3
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30: 7c 85 32 3e lhepx r4,r5,r6
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34: 7c e8 48 3e lwepx r7,r8,r9
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38: 7d 4b 60 3a ldepx r10,r11,r12
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3c: 7d ae 7c be lfdepx f13,r14,r15
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40: 7e 11 91 be stbepx r16,r17,r18
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44: 7e 74 ab 3e sthepx r19,r20,r21
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48: 7e d7 c1 3e stwepx r22,r23,r24
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4c: 7f 3a d9 3a stdepx r25,r26,r27
|
||||
50: 7f 9d f5 be stfdepx f28,r29,r30
|
||||
54: 7c 01 14 06 lbdx r0,r1,r2
|
||||
58: 7d 8d 74 46 lhdx r12,r13,r14
|
||||
5c: 7c 64 2c 86 lwdx r3,r4,r5
|
||||
60: 7f 5b e6 46 lfddx f26,r27,r28
|
||||
64: 7d f0 8c c6 lddx r15,r16,r17
|
||||
68: 7c c7 45 06 stbdx r6,r7,r8
|
||||
6c: 7e 53 a5 46 sthdx r18,r19,r20
|
||||
70: 7d 2a 5d 86 stwdx r9,r10,r11
|
||||
74: 7f be ff 46 stfddx f29,r30,r31
|
||||
78: 7e b6 bd c6 stddx r21,r22,r23
|
||||
7c: 7c 20 0d ec dcbal r0,r1
|
||||
80: 7c 26 3f ec dcbzl r6,r7
|
||||
84: 7c 1f 00 7e dcbstep r31,r0
|
||||
88: 7c 01 10 fe dcbfep r1,r2
|
||||
8c: 7c 64 29 fe dcbtstep r3,r4,r5
|
||||
90: 7c c7 42 7e dcbtep r6,r7,r8
|
||||
94: 7c 0b 67 fe dcbzep r11,r12
|
||||
98: 7c 00 06 26 tlbilx 0,0,r0
|
||||
9c: 7c 20 06 26 tlbilx 1,0,r0
|
||||
a0: 7c 62 1e 26 tlbilx 3,r2,r3
|
||||
a4: 7c 64 2e 26 tlbilx 3,r4,r5
|
||||
1c: 7c 00 00 7c wait
|
||||
20: 7c 00 00 7c wait
|
||||
24: 7c 20 00 7c waitrsv
|
||||
28: 7c 20 00 7c waitrsv
|
||||
2c: 7c 40 00 7c waitimpl
|
||||
30: 7c 40 00 7c waitimpl
|
||||
34: 7f 9c e3 78 mdors
|
||||
38: 7c 00 02 1c ehpriv
|
||||
3c: 7c 18 cb c6 dsn r24,r25
|
||||
40: 7c 22 18 be lbepx r1,r2,r3
|
||||
44: 7c 85 32 3e lhepx r4,r5,r6
|
||||
48: 7c e8 48 3e lwepx r7,r8,r9
|
||||
4c: 7d 4b 60 3a ldepx r10,r11,r12
|
||||
50: 7d ae 7c be lfdepx f13,r14,r15
|
||||
54: 7e 11 91 be stbepx r16,r17,r18
|
||||
58: 7e 74 ab 3e sthepx r19,r20,r21
|
||||
5c: 7e d7 c1 3e stwepx r22,r23,r24
|
||||
60: 7f 3a d9 3a stdepx r25,r26,r27
|
||||
64: 7f 9d f5 be stfdepx f28,r29,r30
|
||||
68: 7c 01 14 06 lbdx r0,r1,r2
|
||||
6c: 7d 8d 74 46 lhdx r12,r13,r14
|
||||
70: 7c 64 2c 86 lwdx r3,r4,r5
|
||||
74: 7f 5b e6 46 lfddx f26,r27,r28
|
||||
78: 7d f0 8c c6 lddx r15,r16,r17
|
||||
7c: 7c c7 45 06 stbdx r6,r7,r8
|
||||
80: 7e 53 a5 46 sthdx r18,r19,r20
|
||||
84: 7d 2a 5d 86 stwdx r9,r10,r11
|
||||
88: 7f be ff 46 stfddx f29,r30,r31
|
||||
8c: 7e b6 bd c6 stddx r21,r22,r23
|
||||
90: 7c 20 0d ec dcbal r0,r1
|
||||
94: 7c 26 3f ec dcbzl r6,r7
|
||||
98: 7c 1f 00 7e dcbstep r31,r0
|
||||
9c: 7c 01 10 fe dcbfep r1,r2
|
||||
a0: 7c 64 29 fe dcbtstep r3,r4,r5
|
||||
a4: 7c c7 42 7e dcbtep r6,r7,r8
|
||||
a8: 7c 0b 67 fe dcbzep r11,r12
|
||||
ac: 7c 00 06 26 tlbilx 0,0,r0
|
||||
b0: 7c 20 06 26 tlbilx 1,0,r0
|
||||
b4: 7c 62 1e 26 tlbilx 3,r2,r3
|
||||
b8: 7c 64 2e 26 tlbilx 3,r4,r5
|
||||
|
|
|
|||
|
|
@ -9,6 +9,11 @@ start:
|
|||
msgclr 13
|
||||
msgsnd 14
|
||||
wait
|
||||
wait 0
|
||||
waitrsv
|
||||
wait 1
|
||||
waitimpl
|
||||
wait 2
|
||||
mdors
|
||||
ehpriv
|
||||
dsn 24, 25
|
||||
|
|
|
|||
|
|
@ -66,3 +66,6 @@ Disassembly of section \.text:
|
|||
e0: ff 00 f1 0d mtfsfi. 6,15
|
||||
e4: ff 01 01 0c mtfsfi 6,0,1
|
||||
e8: ff 01 f1 0d mtfsfi. 6,15,1
|
||||
ec: 7d 6a 02 74 cbcdtd r10,r11
|
||||
f0: 7d 6a 02 34 cdtbcd r10,r11
|
||||
f4: 7d 4b 60 94 addg6s r10,r11,r12
|
||||
|
|
|
|||
|
|
@ -61,3 +61,6 @@ start:
|
|||
mtfsfi. 6,15,0
|
||||
mtfsfi 6,0,1
|
||||
mtfsfi. 6,15,1
|
||||
cbcdtd 10,11
|
||||
cdtbcd 10,11
|
||||
addg6s 10,11,12
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
#as: -a32 -mpower7
|
||||
#as: -mpower7
|
||||
#objdump: -dr -Mpower7
|
||||
#name: POWER7 tests (includes DFP, Altivec and VSX)
|
||||
|
||||
.*: +file format elf32-powerpc.*
|
||||
.*: +file format elf(32)?(64)?-powerpc.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
|
|
@ -33,25 +33,81 @@ Disassembly of section \.text:
|
|||
5c: f1 6c 67 87 xvmovdp vs43,vs44
|
||||
60: f0 64 2f 80 xvcpsgndp vs3,vs4,vs5
|
||||
64: f1 6c 6f 87 xvcpsgndp vs43,vs44,vs45
|
||||
68: 4c 00 03 24 doze
|
||||
6c: 4c 00 03 64 nap
|
||||
70: 4c 00 03 a4 sleep
|
||||
74: 4c 00 03 e4 rvwinkle
|
||||
78: 7c 83 01 34 prtyw r3,r4
|
||||
7c: 7d cd 01 74 prtyd r13,r14
|
||||
80: 7d 5c 02 a6 mfcfar r10
|
||||
84: 7d 7c 03 a6 mtcfar r11
|
||||
88: 7c 83 2b f8 cmpb r3,r4,r5
|
||||
8c: 7c c0 3c be mffgpr f6,r7
|
||||
90: 7d 00 4d be mftgpr r8,f9
|
||||
94: 7d 4b 66 2a lwzcix r10,r11,r12
|
||||
98: 7d ae 7e 2e lfdpx f13,r14,r15
|
||||
9c: ee 11 90 04 dadd f16,f17,f18
|
||||
a0: fe 96 c0 04 daddq f20,f22,f24
|
||||
a4: 7c 60 06 6c dss 3
|
||||
a8: 7e 00 06 6c dssall
|
||||
ac: 7c 25 22 ac dst r5,r4,1
|
||||
b0: 7e 08 3a ac dstt r8,r7,0
|
||||
b4: 7c 65 32 ec dstst r5,r6,3
|
||||
b8: 7e 44 2a ec dststt r4,r5,2
|
||||
bc: 4e 80 00 20 blr
|
||||
68: 7c 00 00 7c wait
|
||||
6c: 7c 00 00 7c wait
|
||||
70: 7c 20 00 7c waitrsv
|
||||
74: 7c 20 00 7c waitrsv
|
||||
78: 7c 40 00 7c waitimpl
|
||||
7c: 7c 40 00 7c waitimpl
|
||||
80: 4c 00 03 24 doze
|
||||
84: 4c 00 03 64 nap
|
||||
88: 4c 00 03 a4 sleep
|
||||
8c: 4c 00 03 e4 rvwinkle
|
||||
90: 7c 83 01 34 prtyw r3,r4
|
||||
94: 7d cd 01 74 prtyd r13,r14
|
||||
98: 7d 5c 02 a6 mfcfar r10
|
||||
9c: 7d 7c 03 a6 mtcfar r11
|
||||
a0: 7c 83 2b f8 cmpb r3,r4,r5
|
||||
a4: 7d 4b 66 2a lwzcix r10,r11,r12
|
||||
a8: ee 11 90 04 dadd f16,f17,f18
|
||||
ac: fe 96 c0 04 daddq f20,f22,f24
|
||||
b0: 7c 60 06 6c dss 3
|
||||
b4: 7e 00 06 6c dssall
|
||||
b8: 7c 25 22 ac dst r5,r4,1
|
||||
bc: 7e 08 3a ac dstt r8,r7,0
|
||||
c0: 7c 65 32 ec dstst r5,r6,3
|
||||
c4: 7e 44 2a ec dststt r4,r5,2
|
||||
c8: 7d 4b 63 56 divwe r10,r11,r12
|
||||
cc: 7d 6c 6b 57 divwe\. r11,r12,r13
|
||||
d0: 7d 8d 77 56 divweo r12,r13,r14
|
||||
d4: 7d ae 7f 57 divweo\. r13,r14,r15
|
||||
d8: 7d 4b 63 16 divweu r10,r11,r12
|
||||
dc: 7d 6c 6b 17 divweu\. r11,r12,r13
|
||||
e0: 7d 8d 77 16 divweuo r12,r13,r14
|
||||
e4: 7d ae 7f 17 divweuo\. r13,r14,r15
|
||||
e8: 7e 27 d9 f8 bpermd r7,r17,r27
|
||||
ec: 7e 8a 02 f4 popcntw r10,r20
|
||||
f0: 7e 8a 03 f4 popcntd r10,r20
|
||||
f4: 7e 95 b4 28 ldbrx r20,r21,r22
|
||||
f8: 7e 95 b5 28 stdbrx r20,r21,r22
|
||||
fc: 7d 40 56 ee lfiwzx f10,0,r10
|
||||
100: 7d 49 56 ee lfiwzx f10,r9,r10
|
||||
104: ec 80 2e 9c fcfids f4,f5
|
||||
108: ec 80 2e 9d fcfids\. f4,f5
|
||||
10c: ec 80 2f 9c fcfidus f4,f5
|
||||
110: ec 80 2f 9d fcfidus\. f4,f5
|
||||
114: fc 80 29 1c fctiwu f4,f5
|
||||
118: fc 80 29 1d fctiwu\. f4,f5
|
||||
11c: fc 80 29 1e fctiwuz f4,f5
|
||||
120: fc 80 29 1f fctiwuz\. f4,f5
|
||||
124: fc 80 2f 5c fctidu f4,f5
|
||||
128: fc 80 2f 5d fctidu\. f4,f5
|
||||
12c: fc 80 2f 5e fctiduz f4,f5
|
||||
130: fc 80 2f 5f fctiduz\. f4,f5
|
||||
134: fc 80 2f 9c fcfidu f4,f5
|
||||
138: fc 80 2f 9d fcfidu\. f4,f5
|
||||
13c: fc 0a 59 00 ftdiv cr0,f10,f11
|
||||
140: ff 8a 59 00 ftdiv cr7,f10,f11
|
||||
144: fc 00 51 40 ftsqrt cr0,f10
|
||||
148: ff 80 51 40 ftsqrt cr7,f10
|
||||
14c: 7e 08 4a 2c dcbtt r8,r9
|
||||
150: 7e 08 49 ec dcbtstt r8,r9
|
||||
154: ed 40 66 44 dcffix f10,f12
|
||||
158: ee 80 b6 45 dcffix\. f20,f22
|
||||
15c: 7d 4b 60 68 lbarx r10,r11,r12
|
||||
160: 7d 4b 60 68 lbarx r10,r11,r12
|
||||
164: 7d 4b 60 69 lbarx r10,r11,r12,1
|
||||
168: 7e 95 b0 e8 lharx r20,r21,r22
|
||||
16c: 7e 95 b0 e8 lharx r20,r21,r22
|
||||
170: 7e 95 b0 e9 lharx r20,r21,r22,1
|
||||
174: 7d 4b 65 6d stbcx\. r10,r11,r12
|
||||
178: 7d 4b 65 ad sthcx\. r10,r11,r12
|
||||
17c: fd c0 78 30 fre f14,f15
|
||||
180: fd c0 78 31 fre\. f14,f15
|
||||
184: ed c0 78 30 fres f14,f15
|
||||
188: ed c0 78 31 fres\. f14,f15
|
||||
18c: fd c0 78 34 frsqrte f14,f15
|
||||
190: fd c0 78 35 frsqrte\. f14,f15
|
||||
194: ed c0 78 34 frsqrtes f14,f15
|
||||
198: ed c0 78 35 frsqrtes\. f14,f15
|
||||
19c: 7c 43 27 1e isel r2,r3,r4,28
|
||||
|
|
|
|||
|
|
@ -1,9 +1,4 @@
|
|||
.file "power7.c"
|
||||
.section ".text"
|
||||
.align 2
|
||||
.p2align 4,,15
|
||||
.globl power7
|
||||
.type power7, @function
|
||||
power7:
|
||||
lxvd2x 3,4,5
|
||||
lxvd2ux 3,4,5
|
||||
|
|
@ -31,6 +26,12 @@ power7:
|
|||
xvcpsgndp 43,44,44
|
||||
xvcpsgndp 3,4,5
|
||||
xvcpsgndp 43,44,45
|
||||
wait
|
||||
wait 0
|
||||
waitrsv
|
||||
wait 1
|
||||
waitimpl
|
||||
wait 2
|
||||
doze
|
||||
nap
|
||||
sleep
|
||||
|
|
@ -40,10 +41,7 @@ power7:
|
|||
mfcfar 10
|
||||
mtcfar 11
|
||||
cmpb 3,4,5
|
||||
mffgpr 6,7
|
||||
mftgpr 8,9
|
||||
lwzcix 10,11,12
|
||||
lfdpx 13,14,15
|
||||
dadd 16,17,18
|
||||
daddq 20,22,24
|
||||
dss 3
|
||||
|
|
@ -52,7 +50,57 @@ power7:
|
|||
dstt 8,7,0
|
||||
dstst 5,6,3
|
||||
dststt 4,5,2
|
||||
blr
|
||||
.size power7,.-power7
|
||||
.ident "GCC: (GNU) 4.1.2 20070115 (prerelease) (SUSE Linux)"
|
||||
.section .note.GNU-stack,"",@progbits
|
||||
divwe 10,11,12
|
||||
divwe. 11,12,13
|
||||
divweo 12,13,14
|
||||
divweo. 13,14,15
|
||||
divweu 10,11,12
|
||||
divweu. 11,12,13
|
||||
divweuo 12,13,14
|
||||
divweuo. 13,14,15
|
||||
bpermd 7,17,27
|
||||
popcntw 10,20
|
||||
popcntd 10,20
|
||||
ldbrx 20,21,22
|
||||
stdbrx 20,21,22
|
||||
lfiwzx 10,0,10
|
||||
lfiwzx 10,9,10
|
||||
fcfids 4,5
|
||||
fcfids. 4,5
|
||||
fcfidus 4,5
|
||||
fcfidus. 4,5
|
||||
fctiwu 4,5
|
||||
fctiwu. 4,5
|
||||
fctiwuz 4,5
|
||||
fctiwuz. 4,5
|
||||
fctidu 4,5
|
||||
fctidu. 4,5
|
||||
fctiduz 4,5
|
||||
fctiduz. 4,5
|
||||
fcfidu 4,5
|
||||
fcfidu. 4,5
|
||||
ftdiv 0,10,11
|
||||
ftdiv 7,10,11
|
||||
ftsqrt 0,10
|
||||
ftsqrt 7,10
|
||||
dcbtt 8,9
|
||||
dcbtstt 8,9
|
||||
dcffix 10,12
|
||||
dcffix. 20,22
|
||||
lbarx 10,11,12
|
||||
lbarx 10,11,12,0
|
||||
lbarx 10,11,12,1
|
||||
lharx 20,21,22
|
||||
lharx 20,21,22,0
|
||||
lharx 20,21,22,1
|
||||
stbcx. 10,11,12
|
||||
sthcx. 10,11,12
|
||||
fre 14,15
|
||||
fre. 14,15
|
||||
fres 14,15
|
||||
fres. 14,15
|
||||
frsqrte 14,15
|
||||
frsqrte. 14,15
|
||||
frsqrtes 14,15
|
||||
frsqrtes. 14,15
|
||||
isel 2,3,4,28
|
||||
|
|
|
|||
|
|
@ -47,5 +47,6 @@ if { [istarget powerpc*-*-*] } then {
|
|||
run_dump_test "power4_32"
|
||||
run_dump_test "power6"
|
||||
run_dump_test "power7"
|
||||
run_dump_test "vsx"
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,174 @@
|
|||
#as: -mvsx
|
||||
#objdump: -d -Mvsx
|
||||
#name: VSX tests
|
||||
|
||||
.*: +file format elf(32)?(64)?-powerpc.*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+00 <start>:
|
||||
0: 7d 0a a4 99 lxsdx vs40,r10,r20
|
||||
4: 7d 0a a4 d9 lxsdux vs40,r10,r20
|
||||
8: 7d 0a a6 99 lxvd2x vs40,r10,r20
|
||||
c: 7d 0a a6 d9 lxvd2ux vs40,r10,r20
|
||||
10: 7d 0a a2 99 lxvdsx vs40,r10,r20
|
||||
14: 7d 0a a6 19 lxvw4x vs40,r10,r20
|
||||
18: 7d 0a a6 59 lxvw4ux vs40,r10,r20
|
||||
1c: 7d 0a a5 99 stxsdx vs40,r10,r20
|
||||
20: 7d 0a a5 d9 stxsdux vs40,r10,r20
|
||||
24: 7d 0a a7 99 stxvd2x vs40,r10,r20
|
||||
28: 7d 0a a7 d9 stxvd2ux vs40,r10,r20
|
||||
2c: 7d 0a a7 19 stxvw4x vs40,r10,r20
|
||||
30: 7d 0a a7 59 stxvw4ux vs40,r10,r20
|
||||
34: f1 00 e5 67 xsabsdp vs40,vs60
|
||||
38: f1 12 e1 07 xsadddp vs40,vs50,vs60
|
||||
3c: f0 92 e1 5e xscmpodp cr1,vs50,vs60
|
||||
40: f0 92 e1 1e xscmpudp cr1,vs50,vs60
|
||||
44: f1 12 e5 87 xscpsgndp vs40,vs50,vs60
|
||||
48: f1 00 e4 27 xscvdpsp vs40,vs60
|
||||
4c: f1 00 e5 63 xscvdpsxds vs40,vs60
|
||||
50: f1 00 e1 63 xscvdpsxws vs40,vs60
|
||||
54: f1 00 e5 23 xscvdpuxds vs40,vs60
|
||||
58: f1 00 e1 23 xscvdpuxws vs40,vs60
|
||||
5c: f1 00 e5 27 xscvspdp vs40,vs60
|
||||
60: f1 00 e5 e3 xscvsxddp vs40,vs60
|
||||
64: f1 00 e5 a3 xscvuxddp vs40,vs60
|
||||
68: f1 12 e1 c7 xsdivdp vs40,vs50,vs60
|
||||
6c: f1 12 e1 0f xsmaddadp vs40,vs50,vs60
|
||||
70: f1 12 e1 4f xsmaddmdp vs40,vs50,vs60
|
||||
74: f1 12 e5 07 xsmaxdp vs40,vs50,vs60
|
||||
78: f1 12 e5 47 xsmindp vs40,vs50,vs60
|
||||
7c: f1 12 e1 8f xsmsubadp vs40,vs50,vs60
|
||||
80: f1 12 e1 cf xsmsubmdp vs40,vs50,vs60
|
||||
84: f1 12 e1 87 xsmuldp vs40,vs50,vs60
|
||||
88: f1 00 e5 a7 xsnabsdp vs40,vs60
|
||||
8c: f1 00 e5 e7 xsnegdp vs40,vs60
|
||||
90: f1 12 e5 0f xsnmaddadp vs40,vs50,vs60
|
||||
94: f1 12 e5 4f xsnmaddmdp vs40,vs50,vs60
|
||||
98: f1 12 e5 8f xsnmsubadp vs40,vs50,vs60
|
||||
9c: f1 12 e5 cf xsnmsubmdp vs40,vs50,vs60
|
||||
a0: f1 00 e1 27 xsrdpi vs40,vs60
|
||||
a4: f1 00 e1 af xsrdpic vs40,vs60
|
||||
a8: f1 00 e1 e7 xsrdpim vs40,vs60
|
||||
ac: f1 00 e1 a7 xsrdpip vs40,vs60
|
||||
b0: f1 00 e1 67 xsrdpiz vs40,vs60
|
||||
b4: f1 00 e1 6b xsredp vs40,vs60
|
||||
b8: f1 00 e1 2b xsrsqrtedp vs40,vs60
|
||||
bc: f1 00 e1 2f xssqrtdp vs40,vs60
|
||||
c0: f1 12 e1 47 xssubdp vs40,vs50,vs60
|
||||
c4: f0 92 e1 ee xstdivdp cr1,vs50,vs60
|
||||
c8: f0 80 e1 aa xstsqrtdp cr1,vs60
|
||||
cc: f1 00 e7 67 xvabsdp vs40,vs60
|
||||
d0: f1 00 e6 67 xvabssp vs40,vs60
|
||||
d4: f1 12 e3 07 xvadddp vs40,vs50,vs60
|
||||
d8: f1 12 e2 07 xvaddsp vs40,vs50,vs60
|
||||
dc: f1 12 e3 1f xvcmpeqdp vs40,vs50,vs60
|
||||
e0: f1 12 e7 1f xvcmpeqdp. vs40,vs50,vs60
|
||||
e4: f1 12 e2 1f xvcmpeqsp vs40,vs50,vs60
|
||||
e8: f1 12 e6 1f xvcmpeqsp. vs40,vs50,vs60
|
||||
ec: f1 12 e3 9f xvcmpgedp vs40,vs50,vs60
|
||||
f0: f1 12 e7 9f xvcmpgedp. vs40,vs50,vs60
|
||||
f4: f1 12 e2 9f xvcmpgesp vs40,vs50,vs60
|
||||
f8: f1 12 e6 9f xvcmpgesp. vs40,vs50,vs60
|
||||
fc: f1 12 e3 5f xvcmpgtdp vs40,vs50,vs60
|
||||
100: f1 12 e7 5f xvcmpgtdp. vs40,vs50,vs60
|
||||
104: f1 12 e2 5f xvcmpgtsp vs40,vs50,vs60
|
||||
108: f1 12 e6 5f xvcmpgtsp. vs40,vs50,vs60
|
||||
10c: f1 12 e7 87 xvcpsgndp vs40,vs50,vs60
|
||||
110: f1 1c e7 87 xvmovdp vs40,vs60
|
||||
114: f1 1c e7 87 xvmovdp vs40,vs60
|
||||
118: f1 12 e6 87 xvcpsgnsp vs40,vs50,vs60
|
||||
11c: f1 1c e6 87 xvmovsp vs40,vs60
|
||||
120: f1 1c e6 87 xvmovsp vs40,vs60
|
||||
124: f1 00 e6 27 xvcvdpsp vs40,vs60
|
||||
128: f1 00 e7 63 xvcvdpsxds vs40,vs60
|
||||
12c: f1 00 e3 63 xvcvdpsxws vs40,vs60
|
||||
130: f1 00 e7 23 xvcvdpuxds vs40,vs60
|
||||
134: f1 00 e3 23 xvcvdpuxws vs40,vs60
|
||||
138: f1 00 e7 27 xvcvspdp vs40,vs60
|
||||
13c: f1 00 e6 63 xvcvspsxds vs40,vs60
|
||||
140: f1 00 e2 63 xvcvspsxws vs40,vs60
|
||||
144: f1 00 e6 23 xvcvspuxds vs40,vs60
|
||||
148: f1 00 e2 23 xvcvspuxws vs40,vs60
|
||||
14c: f1 00 e7 e3 xvcvsxddp vs40,vs60
|
||||
150: f1 00 e6 e3 xvcvsxdsp vs40,vs60
|
||||
154: f1 00 e3 e3 xvcvsxwdp vs40,vs60
|
||||
158: f1 00 e2 e3 xvcvsxwsp vs40,vs60
|
||||
15c: f1 00 e7 a3 xvcvuxddp vs40,vs60
|
||||
160: f1 00 e6 a3 xvcvuxdsp vs40,vs60
|
||||
164: f1 00 e3 a3 xvcvuxwdp vs40,vs60
|
||||
168: f1 00 e2 a3 xvcvuxwsp vs40,vs60
|
||||
16c: f1 12 e3 c7 xvdivdp vs40,vs50,vs60
|
||||
170: f1 12 e2 c7 xvdivsp vs40,vs50,vs60
|
||||
174: f1 12 e3 0f xvmaddadp vs40,vs50,vs60
|
||||
178: f1 12 e3 4f xvmaddmdp vs40,vs50,vs60
|
||||
17c: f1 12 e2 0f xvmaddasp vs40,vs50,vs60
|
||||
180: f1 12 e2 4f xvmaddmsp vs40,vs50,vs60
|
||||
184: f1 12 e7 07 xvmaxdp vs40,vs50,vs60
|
||||
188: f1 12 e6 07 xvmaxsp vs40,vs50,vs60
|
||||
18c: f1 12 e7 47 xvmindp vs40,vs50,vs60
|
||||
190: f1 12 e6 47 xvminsp vs40,vs50,vs60
|
||||
194: f1 12 e3 8f xvmsubadp vs40,vs50,vs60
|
||||
198: f1 12 e3 cf xvmsubmdp vs40,vs50,vs60
|
||||
19c: f1 12 e2 8f xvmsubasp vs40,vs50,vs60
|
||||
1a0: f1 12 e2 cf xvmsubmsp vs40,vs50,vs60
|
||||
1a4: f1 12 e3 87 xvmuldp vs40,vs50,vs60
|
||||
1a8: f1 12 e2 87 xvmulsp vs40,vs50,vs60
|
||||
1ac: f1 00 e7 a7 xvnabsdp vs40,vs60
|
||||
1b0: f1 00 e6 a7 xvnabssp vs40,vs60
|
||||
1b4: f1 00 e7 e7 xvnegdp vs40,vs60
|
||||
1b8: f1 00 e6 e7 xvnegsp vs40,vs60
|
||||
1bc: f1 12 e7 0f xvnmaddadp vs40,vs50,vs60
|
||||
1c0: f1 12 e7 4f xvnmaddmdp vs40,vs50,vs60
|
||||
1c4: f1 12 e6 0f xvnmaddasp vs40,vs50,vs60
|
||||
1c8: f1 12 e6 4f xvnmaddmsp vs40,vs50,vs60
|
||||
1cc: f1 12 e7 8f xvnmsubadp vs40,vs50,vs60
|
||||
1d0: f1 12 e7 cf xvnmsubmdp vs40,vs50,vs60
|
||||
1d4: f1 12 e6 8f xvnmsubasp vs40,vs50,vs60
|
||||
1d8: f1 12 e6 cf xvnmsubmsp vs40,vs50,vs60
|
||||
1dc: f1 00 e3 27 xvrdpi vs40,vs60
|
||||
1e0: f1 00 e3 af xvrdpic vs40,vs60
|
||||
1e4: f1 00 e3 e7 xvrdpim vs40,vs60
|
||||
1e8: f1 00 e3 a7 xvrdpip vs40,vs60
|
||||
1ec: f1 00 e3 67 xvrdpiz vs40,vs60
|
||||
1f0: f1 00 e3 6b xvredp vs40,vs60
|
||||
1f4: f1 00 e2 6b xvresp vs40,vs60
|
||||
1f8: f1 00 e2 27 xvrspi vs40,vs60
|
||||
1fc: f1 00 e2 af xvrspic vs40,vs60
|
||||
200: f1 00 e2 e7 xvrspim vs40,vs60
|
||||
204: f1 00 e2 a7 xvrspip vs40,vs60
|
||||
208: f1 00 e2 67 xvrspiz vs40,vs60
|
||||
20c: f1 00 e3 2b xvrsqrtedp vs40,vs60
|
||||
210: f1 00 e2 2b xvrsqrtesp vs40,vs60
|
||||
214: f1 00 e3 2f xvsqrtdp vs40,vs60
|
||||
218: f1 00 e2 2f xvsqrtsp vs40,vs60
|
||||
21c: f1 12 e3 47 xvsubdp vs40,vs50,vs60
|
||||
220: f1 12 e2 47 xvsubsp vs40,vs50,vs60
|
||||
224: f0 92 e3 ee xvtdivdp cr1,vs50,vs60
|
||||
228: f0 92 e2 ee xvtdivsp cr1,vs50,vs60
|
||||
22c: f0 80 e3 aa xvtsqrtdp cr1,vs60
|
||||
230: f0 80 e2 aa xvtsqrtsp cr1,vs60
|
||||
234: f1 12 e4 17 xxland vs40,vs50,vs60
|
||||
238: f1 12 e4 57 xxlandc vs40,vs50,vs60
|
||||
23c: f1 12 e5 17 xxlnor vs40,vs50,vs60
|
||||
240: f1 12 e4 97 xxlor vs40,vs50,vs60
|
||||
244: f1 12 e4 d7 xxlxor vs40,vs50,vs60
|
||||
248: f1 12 e0 97 xxmrghw vs40,vs50,vs60
|
||||
24c: f1 12 e1 97 xxmrglw vs40,vs50,vs60
|
||||
250: f1 12 e0 57 xxmrghd vs40,vs50,vs60
|
||||
254: f1 12 e1 57 xxpermdi vs40,vs50,vs60,1
|
||||
258: f1 12 e2 57 xxpermdi vs40,vs50,vs60,2
|
||||
25c: f1 12 e3 57 xxmrgld vs40,vs50,vs60
|
||||
260: f1 12 90 57 xxspltd vs40,vs50,0
|
||||
264: f1 12 90 57 xxspltd vs40,vs50,0
|
||||
268: f1 12 93 57 xxspltd vs40,vs50,1
|
||||
26c: f1 12 93 57 xxspltd vs40,vs50,1
|
||||
270: f1 12 e0 57 xxmrghd vs40,vs50,vs60
|
||||
274: f1 12 e0 57 xxmrghd vs40,vs50,vs60
|
||||
278: f1 12 e3 57 xxmrgld vs40,vs50,vs60
|
||||
27c: f1 12 92 57 xxswapd vs40,vs50
|
||||
280: f1 12 92 57 xxswapd vs40,vs50
|
||||
284: f1 12 e7 bf xxsel vs40,vs50,vs60,vs62
|
||||
288: f1 12 e2 17 xxsldwi vs40,vs50,vs60,2
|
||||
28c: f1 02 e2 93 xxspltw vs40,vs60,2
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
.section ".text"
|
||||
start:
|
||||
lxsdx 40,10,20
|
||||
lxsdux 40,10,20
|
||||
lxvd2x 40,10,20
|
||||
lxvd2ux 40,10,20
|
||||
lxvdsx 40,10,20
|
||||
lxvw4x 40,10,20
|
||||
lxvw4ux 40,10,20
|
||||
stxsdx 40,10,20
|
||||
stxsdux 40,10,20
|
||||
stxvd2x 40,10,20
|
||||
stxvd2ux 40,10,20
|
||||
stxvw4x 40,10,20
|
||||
stxvw4ux 40,10,20
|
||||
xsabsdp 40,60
|
||||
xsadddp 40,50,60
|
||||
xscmpodp 1,50,60
|
||||
xscmpudp 1,50,60
|
||||
xscpsgndp 40,50,60
|
||||
xscvdpsp 40,60
|
||||
xscvdpsxds 40,60
|
||||
xscvdpsxws 40,60
|
||||
xscvdpuxds 40,60
|
||||
xscvdpuxws 40,60
|
||||
xscvspdp 40,60
|
||||
xscvsxddp 40,60
|
||||
xscvuxddp 40,60
|
||||
xsdivdp 40,50,60
|
||||
xsmaddadp 40,50,60
|
||||
xsmaddmdp 40,50,60
|
||||
xsmaxdp 40,50,60
|
||||
xsmindp 40,50,60
|
||||
xsmsubadp 40,50,60
|
||||
xsmsubmdp 40,50,60
|
||||
xsmuldp 40,50,60
|
||||
xsnabsdp 40,60
|
||||
xsnegdp 40,60
|
||||
xsnmaddadp 40,50,60
|
||||
xsnmaddmdp 40,50,60
|
||||
xsnmsubadp 40,50,60
|
||||
xsnmsubmdp 40,50,60
|
||||
xsrdpi 40,60
|
||||
xsrdpic 40,60
|
||||
xsrdpim 40,60
|
||||
xsrdpip 40,60
|
||||
xsrdpiz 40,60
|
||||
xsredp 40,60
|
||||
xsrsqrtedp 40,60
|
||||
xssqrtdp 40,60
|
||||
xssubdp 40,50,60
|
||||
xstdivdp 1,50,60
|
||||
xstsqrtdp 1,60
|
||||
xvabsdp 40,60
|
||||
xvabssp 40,60
|
||||
xvadddp 40,50,60
|
||||
xvaddsp 40,50,60
|
||||
xvcmpeqdp 40,50,60
|
||||
xvcmpeqdp. 40,50,60
|
||||
xvcmpeqsp 40,50,60
|
||||
xvcmpeqsp. 40,50,60
|
||||
xvcmpgedp 40,50,60
|
||||
xvcmpgedp. 40,50,60
|
||||
xvcmpgesp 40,50,60
|
||||
xvcmpgesp. 40,50,60
|
||||
xvcmpgtdp 40,50,60
|
||||
xvcmpgtdp. 40,50,60
|
||||
xvcmpgtsp 40,50,60
|
||||
xvcmpgtsp. 40,50,60
|
||||
xvcpsgndp 40,50,60
|
||||
xvmovdp 40,60
|
||||
xvcpsgndp 40,60,60
|
||||
xvcpsgnsp 40,50,60
|
||||
xvmovsp 40,60
|
||||
xvcpsgnsp 40,60,60
|
||||
xvcvdpsp 40,60
|
||||
xvcvdpsxds 40,60
|
||||
xvcvdpsxws 40,60
|
||||
xvcvdpuxds 40,60
|
||||
xvcvdpuxws 40,60
|
||||
xvcvspdp 40,60
|
||||
xvcvspsxds 40,60
|
||||
xvcvspsxws 40,60
|
||||
xvcvspuxds 40,60
|
||||
xvcvspuxws 40,60
|
||||
xvcvsxddp 40,60
|
||||
xvcvsxdsp 40,60
|
||||
xvcvsxwdp 40,60
|
||||
xvcvsxwsp 40,60
|
||||
xvcvuxddp 40,60
|
||||
xvcvuxdsp 40,60
|
||||
xvcvuxwdp 40,60
|
||||
xvcvuxwsp 40,60
|
||||
xvdivdp 40,50,60
|
||||
xvdivsp 40,50,60
|
||||
xvmaddadp 40,50,60
|
||||
xvmaddmdp 40,50,60
|
||||
xvmaddasp 40,50,60
|
||||
xvmaddmsp 40,50,60
|
||||
xvmaxdp 40,50,60
|
||||
xvmaxsp 40,50,60
|
||||
xvmindp 40,50,60
|
||||
xvminsp 40,50,60
|
||||
xvmsubadp 40,50,60
|
||||
xvmsubmdp 40,50,60
|
||||
xvmsubasp 40,50,60
|
||||
xvmsubmsp 40,50,60
|
||||
xvmuldp 40,50,60
|
||||
xvmulsp 40,50,60
|
||||
xvnabsdp 40,60
|
||||
xvnabssp 40,60
|
||||
xvnegdp 40,60
|
||||
xvnegsp 40,60
|
||||
xvnmaddadp 40,50,60
|
||||
xvnmaddmdp 40,50,60
|
||||
xvnmaddasp 40,50,60
|
||||
xvnmaddmsp 40,50,60
|
||||
xvnmsubadp 40,50,60
|
||||
xvnmsubmdp 40,50,60
|
||||
xvnmsubasp 40,50,60
|
||||
xvnmsubmsp 40,50,60
|
||||
xvrdpi 40,60
|
||||
xvrdpic 40,60
|
||||
xvrdpim 40,60
|
||||
xvrdpip 40,60
|
||||
xvrdpiz 40,60
|
||||
xvredp 40,60
|
||||
xvresp 40,60
|
||||
xvrspi 40,60
|
||||
xvrspic 40,60
|
||||
xvrspim 40,60
|
||||
xvrspip 40,60
|
||||
xvrspiz 40,60
|
||||
xvrsqrtedp 40,60
|
||||
xvrsqrtesp 40,60
|
||||
xvsqrtdp 40,60
|
||||
xvsqrtsp 40,60
|
||||
xvsubdp 40,50,60
|
||||
xvsubsp 40,50,60
|
||||
xvtdivdp 1,50,60
|
||||
xvtdivsp 1,50,60
|
||||
xvtsqrtdp 1,60
|
||||
xvtsqrtsp 1,60
|
||||
xxland 40,50,60
|
||||
xxlandc 40,50,60
|
||||
xxlnor 40,50,60
|
||||
xxlor 40,50,60
|
||||
xxlxor 40,50,60
|
||||
xxmrghw 40,50,60
|
||||
xxmrglw 40,50,60
|
||||
xxpermdi 40,50,60,0b00
|
||||
xxpermdi 40,50,60,0b01
|
||||
xxpermdi 40,50,60,0b10
|
||||
xxpermdi 40,50,60,0b11
|
||||
xxspltd 40,50,0
|
||||
xxpermdi 40,50,50,0b00
|
||||
xxspltd 40,50,1
|
||||
xxpermdi 40,50,50,0b11
|
||||
xxmrghd 40,50,60
|
||||
xxpermdi 40,50,60,0b00
|
||||
xxmrgld 40,50,60
|
||||
xxpermdi 40,50,50,0b10
|
||||
xxswapd 40,50
|
||||
xxsel 40,50,60,62
|
||||
xxsldwi 40,50,60,2
|
||||
xxspltw 40,60,2
|
||||
|
|
@ -1,3 +1,7 @@
|
|||
2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
|
||||
|
||||
* ppc.h (PPC_OPCODE_POWER7): New.
|
||||
|
||||
2009-02-06 Doug Evans <dje@google.com>
|
||||
|
||||
* i386.h: Add comment regarding sse* insns and prefixes.
|
||||
|
|
|
|||
|
|
@ -114,6 +114,9 @@ extern const int powerpc_num_opcodes;
|
|||
/* Opcode is only supported by Power4 architecture. */
|
||||
#define PPC_OPCODE_POWER4 0x4000
|
||||
|
||||
/* Opcode is only supported by Power7 architecture. */
|
||||
#define PPC_OPCODE_POWER7 0x8000
|
||||
|
||||
/* Opcode is only supported by POWERPC Classic architecture. */
|
||||
#define PPC_OPCODE_CLASSIC 0x10000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,57 @@
|
|||
2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
|
||||
|
||||
* ppc-dis.c (powerpc_init_dialect): Extend -Mpower7 to disassemble
|
||||
the power7 and the isel instructions.
|
||||
* ppc-opc.c (insert_xc6, extract_xc6): New static functions.
|
||||
(insert_dm, extract_dm): Likewise.
|
||||
(XB6): Update comment to include XX2 form.
|
||||
(WC, XC6, SHW, DMEX, UIM, XX2, XX3RC, XX4, XX2_MASK, XX2UIM_MASK,
|
||||
XX2BF_MASK, XX3BF_MASK, XX3SHW_MASK, XX4_MASK, XWC_MASK, POWER7): New.
|
||||
(RemoveXX3DM): Delete.
|
||||
(powerpc_opcodes): <"lfdp", "lfdpx", "mcrxr", "mftb", "mffgpr",
|
||||
"mftgpr">: Deprecate for POWER7.
|
||||
<"fres", "fres.", "frsqrtes", "frsqrtes.", "fre", "fre.", "frsqrte",
|
||||
"frsqrte.">: Deprecate the three operand form and enable the two
|
||||
operand form for POWER7 and later.
|
||||
<"wait">: Extend to accept optional parameter. Enable for POWER7.
|
||||
<"waitsrv", "waitimpl">: Add extended opcodes.
|
||||
<"ldbrx", "stdbrx">: Enable for POWER7.
|
||||
<"cdtbcd", "cbcdtd", "addg6s">: Add POWER6 opcodes.
|
||||
<"bpermd", "dcbtstt", "dcbtt", "dcffix.", "dcffix", "divde.", "divde",
|
||||
"divdeo.", "divdeo", "divdeu.", "divdeu", "divdeuo.", "divdeuo",
|
||||
"divwe.", "divwe", "divweo.", "divweo", "divweu.", "divweu", "divweuo.",
|
||||
"divweuo", "fcfids.", "fcfids", "fcfidu.", "fcfidu", "fcfidus.",
|
||||
"fcfidus", "fctidu.", "fctidu", "fctiduz.", "fctiduz", "fctiwu.",
|
||||
"fctiwu", "fctiwuz.", "fctiwuz", "ftdiv", "ftsqrt", "lbarx", "lfiwzx",
|
||||
"lharx", "popcntd", "popcntw", "stbcx.", "sthcx.">: Add POWER7 opcodes.
|
||||
<"lxsdux", "lxsdx", "lxvdsx", "lxvw4ux", "lxvw4x", "stxsdux", "stxsdx",
|
||||
"stxvw4ux", "stxvw4x", "xsabsdp", "xsadddp", "xscmpodp", "xscmpudp",
|
||||
"xscpsgndp", "xscvdpsp", "xscvdpsxds", "xscvdpsxws", "xscvdpuxds",
|
||||
"xscvdpuxws", "xscvspdp", "xscvsxddp", "xscvuxddp", "xsdivdp",
|
||||
"xsmaddadp", "xsmaddmdp", "xsmaxdp", "xsmindp", "xsmsubadp",
|
||||
"xsmsubmdp", "xsmuldp", "xsnabsdp", "xsnegdp", "xsnmaddadp",
|
||||
"xsnmaddmdp", "xsnmsubadp", "xsnmsubmdp", "xsrdpi", "xsrdpic",
|
||||
"xsrdpim", "xsrdpip", "xsrdpiz", "xsredp", "xsrsqrtedp", "xssqrtdp",
|
||||
"xssubdp", "xstdivdp", "xstsqrtdp", "xvabsdp", "xvabssp", "xvadddp",
|
||||
"xvaddsp", "xvcmpeqdp.", "xvcmpeqdp", "xvcmpeqsp.", "xvcmpeqsp",
|
||||
"xvcmpgedp.", "xvcmpgedp", "xvcmpgesp.", "xvcmpgesp", "xvcmpgtdp.",
|
||||
"xvcmpgtdp", "xvcmpgtsp.", "xvcmpgtsp", "xvcpsgnsp", "xvcvdpsp",
|
||||
"xvcvdpsxds", "xvcvdpsxws", "xvcvdpuxds", "xvcvdpuxws", "xvcvspdp",
|
||||
"xvcvspsxds", "xvcvspsxws", "xvcvspuxds", "xvcvspuxws", "xvcvsxddp",
|
||||
"xvcvsxdsp", "xvcvsxwdp", "xvcvsxwsp", "xvcvuxddp", "xvcvuxdsp",
|
||||
"xvcvuxwdp", "xvcvuxwsp", "xvdivdp", "xvdivsp", "xvmaddadp",
|
||||
"xvmaddasp", "xvmaddmdp", "xvmaddmsp", "xvmaxdp", "xvmaxsp",
|
||||
"xvmindp", "xvminsp", "xvmovsp", "xvmsubadp", "xvmsubasp", "xvmsubmdp",
|
||||
"xvmsubmsp", "xvmuldp", "xvmulsp", "xvnabsdp", "xvnabssp", "xvnegdp",
|
||||
"xvnegsp", "xvnmaddadp", "xvnmaddasp", "xvnmaddmdp", "xvnmaddmsp",
|
||||
"xvnmsubadp", "xvnmsubasp", "xvnmsubmdp", "xvnmsubmsp", "xvrdpi",
|
||||
"xvrdpic", "xvrdpim", "xvrdpip", "xvrdpiz", "xvredp", "xvresp",
|
||||
"xvrspi", "xvrspic", "xvrspim", "xvrspip", "xvrspiz", "xvrsqrtedp",
|
||||
"xvrsqrtesp", "xvsqrtdp", "xvsqrtsp", "xvsubdp", "xvsubsp", "xvtdivdp",
|
||||
"xvtdivsp", "xvtsqrtdp", "xvtsqrtsp", "xxland", "xxlandc", "xxlnor",
|
||||
"xxlor", "xxlxor", "xxmrghw", "xxmrglw", "xxsel", "xxsldwi", "xxspltd",
|
||||
"xxspltw", "xxswapd">: Add VSX opcodes.
|
||||
|
||||
2009-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEX_IMM4.
|
||||
|
|
|
|||
|
|
@ -112,8 +112,9 @@ powerpc_init_dialect (struct disassemble_info *info)
|
|||
|
||||
if (info->disassembler_options
|
||||
&& strstr (info->disassembler_options, "power7") != NULL)
|
||||
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
|
||||
| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX;
|
||||
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
|
||||
| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
|
||||
| PPC_OPCODE_ISEL | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX;
|
||||
|
||||
if (info->disassembler_options
|
||||
&& strstr (info->disassembler_options, "vsx") != NULL)
|
||||
|
|
|
|||
|
|
@ -81,6 +81,10 @@ static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
|
|||
static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
|
||||
static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
|
||||
static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
|
||||
static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
|
||||
static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
|
||||
static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
|
||||
static long extract_dm (unsigned long, ppc_cpu_t, int *);
|
||||
|
||||
/* The operands table.
|
||||
|
||||
|
|
@ -310,8 +314,9 @@ const struct powerpc_operand powerpc_operands[] =
|
|||
#define LIA LI + 1
|
||||
{ 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
|
||||
|
||||
/* The LS field in an X (sync) form instruction. */
|
||||
/* The LS or WC field in an X (sync or wait) form instruction. */
|
||||
#define LS LIA + 1
|
||||
#define WC LS
|
||||
{ 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
|
||||
|
||||
/* The ME field in an M form instruction. */
|
||||
|
|
@ -607,7 +612,7 @@ const struct powerpc_operand powerpc_operands[] =
|
|||
#define XA6 XT6 + 1
|
||||
{ 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
|
||||
|
||||
/* The XB field in an XX3 form instruction. This is split. */
|
||||
/* The XB field in an XX2 or XX3 form instruction. This is split. */
|
||||
#define XB6 XA6 + 1
|
||||
{ 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
|
||||
|
||||
|
|
@ -617,9 +622,22 @@ const struct powerpc_operand powerpc_operands[] =
|
|||
#define XB6S XB6 + 1
|
||||
{ 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
|
||||
|
||||
/* The DM field in an XX3 form instruction. */
|
||||
#define DM XB6S + 1
|
||||
/* The XC field in an XX4 form instruction. This is split. */
|
||||
#define XC6 XB6S + 1
|
||||
{ 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
|
||||
|
||||
/* The DM or SHW field in an XX3 form instruction. */
|
||||
#define DM XC6 + 1
|
||||
#define SHW DM
|
||||
{ 0x3, 8, NULL, NULL, 0 },
|
||||
|
||||
/* The DM field in an extended mnemonic XX3 form instruction. */
|
||||
#define DMEX DM + 1
|
||||
{ 0x3, 8, insert_dm, extract_dm, 0 },
|
||||
|
||||
/* The UIM field in an XX2 form instruction. */
|
||||
#define UIM DMEX + 1
|
||||
{ 0x3, 16, NULL, NULL, 0 },
|
||||
};
|
||||
|
||||
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
|
||||
|
|
@ -1395,6 +1413,49 @@ extract_xb6s (unsigned long insn,
|
|||
*invalid = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* The XC field in an XX4 form instruction. This is split. */
|
||||
|
||||
static unsigned long
|
||||
insert_xc6 (unsigned long insn,
|
||||
long value,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
const char **errmsg ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
|
||||
}
|
||||
|
||||
static long
|
||||
extract_xc6 (unsigned long insn,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
int *invalid ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
insert_dm (unsigned long insn,
|
||||
long value,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
const char **errmsg)
|
||||
{
|
||||
if (value != 0 && value != 1)
|
||||
*errmsg = _("invalid constant");
|
||||
return insn | (((value) ? 3 : 0) << 8);
|
||||
}
|
||||
|
||||
static long
|
||||
extract_dm (unsigned long insn,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
int *invalid)
|
||||
{
|
||||
long value;
|
||||
|
||||
value = (insn >> 8) & 3;
|
||||
if (value != 0 && value != 3)
|
||||
*invalid = 1;
|
||||
return (value) ? 1 : 0;
|
||||
}
|
||||
|
||||
/* Macros used to form opcodes. */
|
||||
|
||||
|
|
@ -1536,11 +1597,17 @@ extract_xb6s (unsigned long insn,
|
|||
/* An X form instruction. */
|
||||
#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
|
||||
|
||||
/* An XX2 form instruction. */
|
||||
#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
|
||||
|
||||
/* An XX3 form instruction. */
|
||||
#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
|
||||
|
||||
#define XX3DM(op, xop, dm) (XX3 (op, ((unsigned long)(xop) & 0x1f)) \
|
||||
| ((((unsigned long)(dm)) & 0x3) << 8))
|
||||
/* An XX3 form instruction with the RC bit specified. */
|
||||
#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
|
||||
|
||||
/* An XX4 form instruction. */
|
||||
#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
|
||||
|
||||
/* A Z form instruction. */
|
||||
#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
|
||||
|
|
@ -1557,11 +1624,30 @@ extract_xb6s (unsigned long insn,
|
|||
/* The mask for an XX1 form instruction. */
|
||||
#define XX1_MASK X (0x3f, 0x3ff)
|
||||
|
||||
/* The mask for an XX2 form instruction. */
|
||||
#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
|
||||
|
||||
/* The mask for an XX2 form instruction with the UIM bits specified. */
|
||||
#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
|
||||
|
||||
/* The mask for an XX2 form instruction with the BF bits specified. */
|
||||
#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
|
||||
|
||||
/* The mask for an XX3 form instruction. */
|
||||
#define XX3_MASK XX3 (0x3f, 0xff)
|
||||
|
||||
/* The mask for an XX3 form instruction with the DM bits specified. */
|
||||
/* The mask for an XX3 form instruction with the BF bits specified. */
|
||||
#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
|
||||
|
||||
/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
|
||||
#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
|
||||
#define XX3SHW_MASK XX3DM_MASK
|
||||
|
||||
/* The mask for an XX4 form instruction. */
|
||||
#define XX4_MASK XX4 (0x3f, 0x3)
|
||||
|
||||
/* An X form wait instruction with everything filled in except the WC field. */
|
||||
#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
|
||||
|
||||
/* The mask for a Z form instruction. */
|
||||
#define Z_MASK ZRC (0x3f, 0x1ff, 1)
|
||||
|
|
@ -1803,6 +1889,7 @@ extract_xb6s (unsigned long insn,
|
|||
#define POWER4 PPC_OPCODE_POWER4
|
||||
#define POWER5 PPC_OPCODE_POWER5
|
||||
#define POWER6 PPC_OPCODE_POWER6
|
||||
#define POWER7 PPC_OPCODE_POWER7
|
||||
#define CELL PPC_OPCODE_CELL
|
||||
#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
|
||||
#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
|
||||
|
|
@ -3425,6 +3512,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"lvewx", X(31,71), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
|
||||
|
||||
{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"isel", XISEL(31,15), XISEL_MASK, PPCISEL, PPCNONE, {RT, RA, RB, CRB}},
|
||||
|
|
@ -3434,6 +3523,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
|
||||
{"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
|
||||
|
||||
{"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
|
||||
|
||||
{"ldux", X(31,53), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
|
||||
|
||||
{"dcbst", X(31,54), XRT_MASK, PPC, PPCNONE, {RA, RB}},
|
||||
|
|
@ -3447,7 +3538,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
|
||||
{"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
|
||||
|
||||
{"wait", X(31,62), 0xffffffff, E500MC, PPCNONE, {0}},
|
||||
{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC, PPCNONE, {0}},
|
||||
{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC, PPCNONE, {0}},
|
||||
{"wait", X(31,62), XWC_MASK, POWER7|E500MC, PPCNONE, {WC}},
|
||||
|
||||
{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
|
||||
|
||||
|
|
@ -3501,6 +3594,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
|
||||
|
||||
{"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
|
||||
|
||||
{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
|
||||
|
||||
{"lbzux", X(31,119), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
|
||||
|
|
@ -3636,6 +3731,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"mtsrin", X(31,242), XRA_MASK, PPC32, PPCNONE, {RS, RB}},
|
||||
{"mtsri", X(31,242), XRA_MASK, POWER32, PPCNONE, {RS, RB}},
|
||||
|
||||
{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
|
||||
{"dcbtst", X(31,246), X_MASK, PPC, POWER4, {CT, RA, RB}},
|
||||
{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
|
||||
|
||||
|
|
@ -3644,6 +3740,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
|
||||
{"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
|
||||
|
||||
{"bpermd", X(31,252), X_MASK, POWER7, PPCNONE, {RA, RS, RB}},
|
||||
|
||||
{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"mfdcrx", X(31,259), X_MASK, BOOKE, PPCNONE, {RS, RA}},
|
||||
|
|
@ -3668,11 +3766,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}},
|
||||
{"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
|
||||
{"dcbt", X(31,278), X_MASK, PPC, POWER4, {CT, RA, RB}},
|
||||
{"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
|
||||
|
||||
{"lhzx", X(31,279), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
|
||||
|
||||
{"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
|
||||
|
||||
{"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
|
||||
{"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
|
||||
|
||||
|
|
@ -3687,6 +3788,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"lhzux", X(31,311), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
|
||||
|
||||
{"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
|
||||
|
||||
{"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
|
||||
{"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
|
||||
|
||||
|
|
@ -3731,6 +3834,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
|
||||
{"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
|
||||
|
||||
{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}},
|
||||
|
||||
{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}},
|
||||
|
|
@ -3937,7 +4042,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
|
||||
{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
|
||||
{"mftb", X(31,371), X_MASK, CLASSIC, PPCNONE, {RT, TBR}},
|
||||
{"mftb", X(31,371), X_MASK, CLASSIC, POWER7, {RT, TBR}},
|
||||
|
||||
{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
|
||||
|
||||
|
|
@ -3945,11 +4050,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
|
||||
|
||||
{"popcntw", X(31,378), XRB_MASK, POWER7, PPCNONE, {RA, RS}},
|
||||
|
||||
{"mtdcrx", X(31,387), X_MASK, BOOKE, PPCNONE, {RA, RS}},
|
||||
|
||||
{"dcblc", X(31,390), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
|
||||
{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
|
||||
|
||||
{"divdeu", XO(31,393,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divweu", XO(31,395,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divweu.", XO(31,395,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"dcblce", X(31,398), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
|
||||
|
||||
{"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
|
||||
|
|
@ -3963,6 +4075,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}},
|
||||
|
||||
{"divde", XO(31,425,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divde.", XO(31,425,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divwe", XO(31,427,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divwe.", XO(31,427,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
|
||||
|
||||
{"ecowx", X(31,438), X_MASK, PPC, PPCNONE, {RT, RA, RB}},
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||||
|
|
@ -4204,9 +4321,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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|||
|
||||
{"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}},
|
||||
|
||||
{"popcntd", X(31,506), XRB_MASK, POWER7, PPCNONE, {RA, RS}},
|
||||
|
||||
{"cmpb", X(31,508), X_MASK, POWER6, PPCNONE, {RA, RS, RB}},
|
||||
|
||||
{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, PPCNONE, {BF}},
|
||||
{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, POWER7, {BF}},
|
||||
|
||||
{"lbdx", X(31,515), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
|
||||
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||||
|
|
@ -4229,7 +4348,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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|||
|
||||
{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}},
|
||||
|
||||
{"ldbrx", X(31,532), X_MASK, CELL, PPCNONE, {RT, RA0, RB}},
|
||||
{"ldbrx", X(31,532), X_MASK, CELL|POWER7, PPCNONE, {RT, RA0, RB}},
|
||||
|
||||
{"lswx", X(31,533), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
|
||||
{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
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||||
|
|
@ -4273,6 +4392,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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|
||||
{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
|
||||
|
||||
{"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
|
||||
|
||||
{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, PPCNONE, {RT, SR}},
|
||||
|
||||
{"lswi", X(31,597), X_MASK, PPCCOM, PPCNONE, {RT, RA0, NB}},
|
||||
|
|
@ -4287,7 +4408,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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|||
{"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}},
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||||
|
||||
{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
|
||||
{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, PPCNONE, {FRT, RB}},
|
||||
{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
|
||||
|
||||
{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
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|
@ -4299,6 +4420,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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|||
{"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
|
||||
{"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"lxsdux", X(31,620), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
|
||||
|
||||
{"mfsri", X(31,627), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"dclst", X(31,630), XRB_MASK, PWRCOM, PPCNONE, {RS, RA}},
|
||||
|
|
@ -4322,7 +4445,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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|||
|
||||
{"mfsrin", X(31,659), XRA_MASK, PPC32, PPCNONE, {RT, RB}},
|
||||
|
||||
{"stdbrx", X(31,660), X_MASK, CELL, PPCNONE, {RS, RA0, RB}},
|
||||
{"stdbrx", X(31,660), X_MASK, CELL|POWER7, PPCNONE, {RS, RA0, RB}},
|
||||
|
||||
{"stswx", X(31,661), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
|
||||
{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
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||||
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|
@ -4343,6 +4466,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
|
||||
{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
|
||||
|
||||
{"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
|
||||
|
||||
{"stfsux", X(31,695), X_MASK, COM, PPCNONE, {FRS, RAS, RB}},
|
||||
|
||||
{"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
|
||||
|
|
@ -4352,6 +4477,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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|||
|
||||
{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
|
||||
|
||||
{"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
|
||||
|
||||
{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
|
||||
{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
|
||||
{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
|
||||
|
|
@ -4365,6 +4492,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"stswi", X(31,725), X_MASK, PPCCOM, PPCNONE, {RS, RA0, NB}},
|
||||
{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
|
||||
|
||||
{"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
|
||||
|
||||
{"stfdx", X(31,727), X_MASK, COM, PPCNONE, {FRS, RA0, RB}},
|
||||
|
||||
{"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
|
||||
|
|
@ -4374,12 +4503,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
|
||||
|
||||
{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
|
||||
{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, PPCNONE, {RT, FRB}},
|
||||
{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
|
||||
|
||||
{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
|
||||
|
||||
{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
|
||||
|
||||
{"stxsdux", X(31,748), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
|
||||
|
||||
{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
|
||||
{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
|
||||
{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
|
||||
|
|
@ -4417,6 +4548,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
|
||||
{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
|
||||
|
||||
{"tlbivax", X(31,786), XRT_MASK, BOOKE, PPCNONE, {RA, RB}},
|
||||
{"tlbilx", X(31,787), X_MASK, E500MC, PPCNONE, {T, RA0, RB}},
|
||||
{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, PPCNONE, {0}},
|
||||
|
|
@ -4428,7 +4561,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
|
||||
|
||||
{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
|
||||
{"lfdpx", X(31,791), X_MASK, POWER6, PPCNONE, {FRT, RA, RB}},
|
||||
{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRT, RA, RB}},
|
||||
|
||||
{"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
|
||||
{"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
|
||||
|
|
@ -4442,6 +4575,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
|
||||
|
||||
{"lxvw4ux", X(31,812), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
|
||||
|
||||
{"rac", X(31,818), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
|
||||
|
|
@ -4482,9 +4617,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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|||
|
||||
{"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
|
||||
|
||||
{"lfiwzx", X(31,887), X_MASK, POWER7, PPCNONE, {FRT, RA0, RB}},
|
||||
|
||||
{"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
|
||||
{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
|
||||
|
||||
{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divweuo", XO(31,395,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
|
||||
|
||||
{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}},
|
||||
{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}},
|
||||
|
||||
|
|
@ -4512,6 +4656,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
|
||||
|
||||
{"divdeo", XO(31,425,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divweo", XO(31,427,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
{"divweo.", XO(31,427,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"stxvw4ux", X(31,940), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
|
||||
|
||||
{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
|
||||
{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
|
||||
{"tlbre", X(31,946), X_MASK, PPC403|BOOKE, PPCNONE, {RSO, RAOPT, SHO}},
|
||||
|
|
@ -4654,7 +4805,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
|
||||
|
||||
{"lfdp", OP(57), OP_MASK, POWER6, PPCNONE, {FRT, D, RA0}},
|
||||
{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}},
|
||||
|
||||
{"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
|
||||
{"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}},
|
||||
|
|
@ -4678,14 +4829,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}},
|
||||
{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"fres", A(59,24,0), AFRALFRC_MASK, PPC, PPCNONE, {FRT, FRB, A_L}},
|
||||
{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, PPCNONE, {FRT, FRB, A_L}},
|
||||
{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
|
||||
{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
|
||||
{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}},
|
||||
{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}},
|
||||
|
||||
{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, PPCNONE, {FRT, FRB, A_L}},
|
||||
{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, PPCNONE, {FRT, FRB, A_L}},
|
||||
{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
|
||||
{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
|
||||
{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"fmsubs", A(59,28,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
|
||||
{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
|
||||
|
|
@ -4751,21 +4906,166 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
|
||||
{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
|
||||
{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
|
||||
|
||||
{"fcfids", XRC(59,846,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
|
||||
{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
|
||||
|
||||
{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
|
||||
|
||||
{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
|
||||
|
||||
{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}},
|
||||
{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}},
|
||||
{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}},
|
||||
{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
|
||||
{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}},
|
||||
{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
|
||||
{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
|
||||
{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
|
||||
{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
|
||||
{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
|
||||
{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
|
||||
{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}},
|
||||
{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
|
||||
{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
|
||||
{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
|
||||
{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
|
||||
{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
|
||||
{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
|
||||
|
||||
{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
|
||||
|
||||
|
|
@ -4822,16 +5122,20 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"fsel", A(63,23,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
|
||||
{"fsel.", A(63,23,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
|
||||
|
||||
{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, PPCNONE, {FRT, FRB, A_L}},
|
||||
{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, PPCNONE, {FRT, FRB, A_L}},
|
||||
{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
|
||||
{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
|
||||
{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}},
|
||||
{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
|
||||
{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}},
|
||||
{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
|
||||
|
||||
{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, PPCNONE, {FRT, FRB, A_L}},
|
||||
{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, PPCNONE, {FRT, FRB, A_L}},
|
||||
{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
|
||||
{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
|
||||
{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
|
||||
{"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
|
||||
|
|
@ -4887,6 +5191,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
|
||||
{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
|
||||
|
||||
{"ftdiv", X(63,128), X_MASK|(3<<21), POWER7, PPCNONE, {BF, FRA, FRB}},
|
||||
|
||||
{"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
|
||||
|
||||
{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6, {BFF, U}},
|
||||
|
|
@ -4897,6 +5203,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
|
||||
{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}},
|
||||
|
||||
{"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
|
||||
{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}},
|
||||
{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}},
|
||||
|
|
@ -4967,6 +5280,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
|
||||
{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
|
||||
|
||||
{"fctidu", XRC(63,942,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
|
||||
{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
|
||||
};
|
||||
|
||||
const int powerpc_num_opcodes =
|
||||
|
|
|
|||
Loading…
Reference in New Issue