Rework the alignment check for BFD_RELOC_MIPS_18_PCREL_S3.
gas/ * config/tc-mips.c (md_apply_fix): Apply alignment check to the symbol and offset rather than *valP for BFD_RELOC_MIPS_18_PCREL_S3. Also update the error message for BFD_RELOC_MIPS_19_PCREL_S2. gas/testsuite/ * gas/mips/r6-64.s: Remove .align directives from LDPC instructions and add further tests for LDPC. * gas/mips/r6-64-n32.d: remove the NOPs from LDPC expected output and update for new tests. * gas/mips/r6-64-n64.d: Likewise. * gas/mips/ldpc-unalign.l: New file. * gas/mips/ldpc-unalign.s: Likewise. * gas/mips/mips.exp: Run ldpc-unalign test.
This commit is contained in:
Matthew Fortune
parent
13e322759b
commit
0866e94c87
@ -1,3 +1,10 @@
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2014-12-19 Matthew Fortune <matthew.fortune@imgtec.com>
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* config/tc-mips.c (md_apply_fix): Apply alignment check
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to the symbol and offset rather than *valP for
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BFD_RELOC_MIPS_18_PCREL_S3. Also update the error message
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for BFD_RELOC_MIPS_19_PCREL_S2.
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2014-12-14 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (flag_compress_debug): Default to compress
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@ -15009,10 +15009,14 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
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break;
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case BFD_RELOC_MIPS_18_PCREL_S3:
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if ((*valP & 0x7) != 0)
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if ((S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
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as_bad_where (fixP->fx_file, fixP->fx_line,
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_("PC-relative access to misaligned address (%lx)"),
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(long) *valP);
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_("PC-relative access using misaligned symbol (%lx)"),
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(long) S_GET_VALUE (fixP->fx_addsy));
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if ((fixP->fx_offset & 0x7) != 0)
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as_bad_where (fixP->fx_file, fixP->fx_line,
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_("PC-relative access using misaligned offset (%lx)"),
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(long) fixP->fx_offset);
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gas_assert (!fixP->fx_done);
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break;
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@ -15021,7 +15025,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
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if ((*valP & 0x3) != 0)
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as_bad_where (fixP->fx_file, fixP->fx_line,
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_("PC-relative access to misaligned address (%lx)"),
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(long) *valP);
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(long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
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gas_assert (!fixP->fx_done);
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break;
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@ -1,3 +1,14 @@
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2014-12-19 Matthew Fortune <matthew.fortune@imgtec.com>
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* gas/mips/r6-64.s: Remove .align directives from LDPC
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instructions and add further tests for LDPC.
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* gas/mips/r6-64-n32.d: remove the NOPs from LDPC expected
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output and update for new tests.
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* gas/mips/r6-64-n64.d: Likewise.
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* gas/mips/ldpc-unalign.l: New file.
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* gas/mips/ldpc-unalign.s: Likewise.
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* gas/mips/mips.exp: Run ldpc-unalign test.
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2014-12-19 Matthew Fortune <matthew.fortune@imgtec.com>
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* gas/mips/octeon3.d: Switch to use numeric register names.
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9
gas/testsuite/gas/mips/ldpc-unalign.l
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9
gas/testsuite/gas/mips/ldpc-unalign.l
Normal file
@ -0,0 +1,9 @@
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.*: Assembler messages:
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.*:2: Error: PC-relative access using misaligned offset \(4\)
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.*:3: Error: PC-relative access using misaligned offset \(4\)
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.*:4: Error: PC-relative access using misaligned symbol \(1c\)
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.*:5: Error: PC-relative access using misaligned symbol \(1c\)
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.*:6: Error: PC-relative access using misaligned symbol \(1c\)
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.*:6: Error: PC-relative access using misaligned offset \(4\)
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.*:7: Error: PC-relative access using misaligned symbol \(1c\)
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.*:7: Error: PC-relative access using misaligned offset \(4\)
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18
gas/testsuite/gas/mips/ldpc-unalign.s
Normal file
18
gas/testsuite/gas/mips/ldpc-unalign.s
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@ -0,0 +1,18 @@
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.text
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ldpc $4, 1f+4
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ldpc $4, 1f+4
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ldpc $4, 2f
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ldpc $4, 2f
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ldpc $4, 2f+4
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ldpc $4, 2f+4
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.align 3
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1:
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nop
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2:
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nop
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nop
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nop
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.align 2
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.space 8
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@ -1450,6 +1450,7 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test_arches "r6-n64" [mips_arch_list_matching mips64r6]
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run_dump_test_arches "r6-64-n32" [mips_arch_list_matching mips64r6]
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run_dump_test_arches "r6-64-n64" [mips_arch_list_matching mips64r6]
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run_list_test_arches "ldpc-unalign" "-64" [mips_arch_list_matching mips64r6]
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}
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run_list_test_arches "r6-removed" "-32" [mips_arch_list_matching mips32r6]
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run_list_test_arches "r6-64-removed" [mips_arch_list_matching mips64r6]
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@ -44,18 +44,21 @@ Disassembly of section .text:
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[ ]*78: R_MIPS_PC19_S2 L0.+0xffffc
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0+007c <[^>]*> ec940000 lwupc a0,fff0007c <[^>]*>
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0+0080 <[^>]*> ec93ffff lwupc a0,0010007c <[^>]*>
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0+0084 <[^>]*> 00000000 nop
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0+0084 <[^>]*> ec980000 ldpc a0,00000080 <[^>]*>
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[ ]*84: R_MIPS_PC18_S3 \.L1.1
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0+0088 <[^>]*> ec980000 ldpc a0,00000088 <[^>]*>
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[ ]*88: R_MIPS_PC18_S3 \.L1.1
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0+008c <[^>]*> 00000000 nop
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0+0090 <[^>]*> ec980000 ldpc a0,00000090 <[^>]*>
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[ ]*90: R_MIPS_PC18_S3 L0.-0x100000
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0+0094 <[^>]*> 00000000 nop
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[ ]*90: R_MIPS_PC18_S3 \.L3.1-0x100000
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0+0094 <[^>]*> ec980000 ldpc a0,00000090 <[^>]*>
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[ ]*94: R_MIPS_PC18_S3 \.L3.1-0x100000
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0+0098 <[^>]*> ec980000 ldpc a0,00000098 <[^>]*>
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[ ]*98: R_MIPS_PC18_S3 L0.+0xffff8
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0+009c <[^>]*> 00000000 nop
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[ ]*98: R_MIPS_PC18_S3 \.L3.2\+0xffff8
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0+009c <[^>]*> ec980000 ldpc a0,00000098 <[^>]*>
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[ ]*9c: R_MIPS_PC18_S3 \.L3.2\+0xffff8
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0+00a0 <[^>]*> ec9a0000 ldpc a0,fff000a0 <[^>]*>
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0+00a4 <[^>]*> 00000000 nop
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0+00a4 <[^>]*> ec9a0000 ldpc a0,fff000a0 <[^>]*>
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0+00a8 <[^>]*> ec99ffff ldpc a0,001000a0 <[^>]*>
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0+00ac <[^>]*> 00000000 nop
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0+00ac <[^>]*> ec99ffff ldpc a0,001000a0 <[^>]*>
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\.\.\.
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@ -50,24 +50,33 @@ Disassembly of section .text:
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[ ]*78: R_MIPS_NONE \*ABS\*\+0xffffc
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0+007c <[^>]*> ec940000 lwupc a0,f+ff0007c <[^>]*>
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0+0080 <[^>]*> ec93ffff lwupc a0,0+010007c <[^>]*>
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0+0084 <[^>]*> 00000000 nop
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0+0084 <[^>]*> ec980000 ldpc a0,0+0000080 <[^>]*>
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[ ]*84: R_MIPS_PC18_S3 .L1.1
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[ ]*84: R_MIPS_NONE \*ABS\*
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[ ]*84: R_MIPS_NONE \*ABS\*
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0+0088 <[^>]*> ec980000 ldpc a0,0+0000088 <[^>]*>
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[ ]*88: R_MIPS_PC18_S3 \.L1.1
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[ ]*88: R_MIPS_PC18_S3 .L1.1
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[ ]*88: R_MIPS_NONE \*ABS\*
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[ ]*88: R_MIPS_NONE \*ABS\*
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0+008c <[^>]*> 00000000 nop
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0+0090 <[^>]*> ec980000 ldpc a0,0+0000090 <[^>]*>
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[ ]*90: R_MIPS_PC18_S3 L0.-0x100000
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[ ]*90: R_MIPS_PC18_S3 .L3.1-0x100000
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[ ]*90: R_MIPS_NONE \*ABS\*-0x100000
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[ ]*90: R_MIPS_NONE \*ABS\*-0x100000
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0+0094 <[^>]*> 00000000 nop
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0+0094 <[^>]*> ec980000 ldpc a0,0+0000090 <[^>]*>
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[ ]*94: R_MIPS_PC18_S3 .L3.1-0x100000
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[ ]*94: R_MIPS_NONE \*ABS\*-0x100000
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[ ]*94: R_MIPS_NONE \*ABS\*-0x100000
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0+0098 <[^>]*> ec980000 ldpc a0,0+0000098 <[^>]*>
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[ ]*98: R_MIPS_PC18_S3 L0.\+0xffff8
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[ ]*98: R_MIPS_PC18_S3 .L3.2\+0xffff8
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[ ]*98: R_MIPS_NONE \*ABS\*\+0xffff8
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[ ]*98: R_MIPS_NONE \*ABS\*\+0xffff8
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0+009c <[^>]*> 00000000 nop
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0+009c <[^>]*> ec980000 ldpc a0,0+0000098 <[^>]*>
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[ ]*9c: R_MIPS_PC18_S3 .L3.2\+0xffff8
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[ ]*9c: R_MIPS_NONE \*ABS\*\+0xffff8
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[ ]*9c: R_MIPS_NONE \*ABS\*\+0xffff8
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0+00a0 <[^>]*> ec9a0000 ldpc a0,f+ff000a0 <[^>]*>
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0+00a4 <[^>]*> 00000000 nop
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0+00a4 <[^>]*> ec9a0000 ldpc a0,f+ff000a0 <[^>]*>
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0+00a8 <[^>]*> ec99ffff ldpc a0,0+01000a0 <[^>]*>
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0+00ac <[^>]*> 00000000 nop
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0+00ac <[^>]*> ec99ffff ldpc a0,0+01000a0 <[^>]*>
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\.\.\.
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@ -40,19 +40,24 @@
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lwu $4, (-262144 << 2)($pc)
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lwu $4, (262143 << 2)($pc)
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.align 3
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ldpc $4, 1f
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.align 3
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ldpc $4, .+(-131072 << 3)
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.align 3
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ldpc $4, .+(131071 << 3)
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.align 3
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ldpc $4, 1f
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.align 3
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3:
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ldpc $4, 3b+(-131072 << 3)
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ldpc $4, 3b+(-131072 << 3)
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.align 3
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3:
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ldpc $4, 3b+(131071 << 3)
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ldpc $4, 3b+(131071 << 3)
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ld $4, (-131072 << 3)($pc)
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.align 3
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ld $4, (-131072 << 3)($pc)
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ld $4, (131071 << 3)($pc)
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ld $4, (131071 << 3)($pc)
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.align 3
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1:
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nop
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nop
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.align 2
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