2011-03-08 Maxim Grigoriev <maxim2405@gmail.com>
* xtensa-tdep.c (xtensa_read_register): New function. (xtensa_write_register): New function. (xtensa_find_register_by_name): New function. (xtensa_windowed_frame_cache): Update comments in type description. (xtensa_frame_cache): Likewise. (xtensa_window_interrupt_insn): New function. (xtensa_frame_cache): Add analysis for Xtensa Window Exception frames. (xtensa_insn_kind): Add new instructions. (rwx_special_register): New function. (call0_classify_opcode): Add new instructions to the analysis. (a0_saved, a7_saved, a11_saved): New variables. (a0_was_saved, a7_was_saved, a11_was_saved): New variables. (execute_l32e): New function. (execute_s32e): New function. (xtensa_exception_handler_t): New type. (execute_code): New function. (xtensa_window_interrupt_frame_cache): New function to conduct frame analysis for Xtensa Window Exception handlers.
This commit is contained in:
Maxim Grigoriev
parent
ecb351e919
commit
08b9c608aa
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@ -1,3 +1,24 @@
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2011-03-08 Maxim Grigoriev <maxim2405@gmail.com>
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* xtensa-tdep.c (xtensa_read_register): New function.
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(xtensa_write_register): New function.
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(xtensa_find_register_by_name): New function.
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(xtensa_windowed_frame_cache): Update comments in type description.
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(xtensa_frame_cache): Likewise.
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(xtensa_window_interrupt_insn): New function.
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(xtensa_frame_cache): Add analysis for Xtensa Window Exception frames.
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(xtensa_insn_kind): Add new instructions.
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(rwx_special_register): New function.
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(call0_classify_opcode): Add new instructions to the analysis.
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(a0_saved, a7_saved, a11_saved): New variables.
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(a0_was_saved, a7_was_saved, a11_was_saved): New variables.
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(execute_l32e): New function.
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(execute_s32e): New function.
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(xtensa_exception_handler_t): New type.
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(execute_code): New function.
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(xtensa_window_interrupt_frame_cache): New function to conduct frame
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analysis for Xtensa Window Exception handlers.
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2011-03-08 Maxim Grigoriev <maxim2405@gmail.com>
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* xtensa-tdep.c (TX_PS): New.
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@ -161,6 +161,21 @@ areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
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return (areg > 15) ? -1 : areg;
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}
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static inline unsigned long
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xtensa_read_register (int regnum)
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{
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ULONGEST value;
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regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
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return (unsigned long) value;
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}
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static inline void
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xtensa_write_register (int regnum, ULONGEST value)
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{
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regcache_raw_write_unsigned (get_current_regcache (), regnum, value);
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}
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/* Return the window size of the previous call to the function from which we
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have just returned.
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@ -210,6 +225,22 @@ extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
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/* REGISTER INFORMATION */
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/* Find register by name. */
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static int
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xtensa_find_register_by_name (struct gdbarch *gdbarch, char *name)
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{
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int i;
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for (i = 0; i < gdbarch_num_regs (gdbarch)
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+ gdbarch_num_pseudo_regs (gdbarch);
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i++)
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if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0)
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return i;
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return -1;
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}
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/* Returns the name of a register. */
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static const char *
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xtensa_register_name (struct gdbarch *gdbarch, int regnum)
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@ -907,14 +938,13 @@ typedef struct xtensa_windowed_frame_cache
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{
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int wb; /* WINDOWBASE of the previous frame. */
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int callsize; /* Call size of this frame. */
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int ws; /* WINDOWSTART of the previous frame. It
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keeps track of life windows only. If there
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is no bit set for the window, that means it
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had been already spilled because of window
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overflow. */
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int ws; /* WINDOWSTART of the previous frame. It keeps track of
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life windows only. If there is no bit set for the
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window, that means it had been already spilled
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because of window overflow. */
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/* Spilled A-registers from the previous frame.
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AREGS[i] == -1, if corresponding AR is alive. */
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/* Addresses of spilled A-registers.
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AREGS[i] == -1, if corresponding AR is alive. */
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CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
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} xtensa_windowed_frame_cache_t;
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@ -968,10 +998,10 @@ typedef struct xtensa_call0_frame_cache
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typedef struct xtensa_frame_cache
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{
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CORE_ADDR base; /* Stack pointer of this frame. */
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CORE_ADDR pc; /* PC at the entry point to the function. */
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CORE_ADDR ra; /* The raw return address (without CALLINC). */
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CORE_ADDR ps; /* The PS register of this frame. */
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CORE_ADDR prev_sp; /* Stack Pointer of the previous frame. */
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CORE_ADDR pc; /* PC of this frame at the function entry point. */
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CORE_ADDR ra; /* The raw return address of this frame. */
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CORE_ADDR ps; /* The PS register of the previous (older) frame. */
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CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
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int call0; /* It's a call0 framework (else windowed). */
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union
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{
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@ -1064,6 +1094,38 @@ xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
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return frame_id_build (fp + SP_ALIGNMENT, pc);
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}
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/* Returns true, if instruction to execute next is unique to Xtensa Window
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Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
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static int
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xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
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{
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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unsigned int insn = read_memory_integer (pc, 4, byte_order);
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unsigned int code;
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if (byte_order == BFD_ENDIAN_BIG)
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{
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/* Check, if this is L32E or S32E. */
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code = insn & 0xf000ff00;
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if ((code == 0x00009000) || (code == 0x00009400))
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return 1;
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/* Check, if this is RFWU or RFWO. */
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code = insn & 0xffffff00;
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return ((code == 0x00430000) || (code == 0x00530000));
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}
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else
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{
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/* Check, if this is L32E or S32E. */
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code = insn & 0x00ff000f;
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if ((code == 0x090000) || (code == 0x490000))
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return 1;
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/* Check, if this is RFWU or RFWO. */
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code = insn & 0x00ffffff;
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return ((code == 0x00003400) || (code == 0x00003500));
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}
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}
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/* Returns the best guess about which register is a frame pointer
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for the function containing CURRENT_PC. */
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@ -1195,6 +1257,11 @@ call0_frame_cache (struct frame_info *this_frame,
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xtensa_frame_cache_t *cache,
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CORE_ADDR pc, CORE_ADDR litbase);
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static void
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xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
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xtensa_frame_cache_t *cache,
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CORE_ADDR pc);
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static struct xtensa_frame_cache *
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xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
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{
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@ -1302,9 +1369,8 @@ xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
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}
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if ((cache->prev_sp == 0) && ( ra != 0 ))
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/* If RA is equal to 0 this frame is an outermost frame.
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Leave cache->prev_sp unchanged marking the boundary of the
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frame stack. */
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/* If RA is equal to 0 this frame is an outermost frame. Leave
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cache->prev_sp unchanged marking the boundary of the frame stack. */
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{
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if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
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{
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@ -1321,11 +1387,18 @@ xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
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(gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
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cache->wd.wb);
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cache->prev_sp = get_frame_register_unsigned (this_frame,
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regnum);
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cache->prev_sp = xtensa_read_register (regnum);
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}
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}
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}
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else if (xtensa_window_interrupt_insn (gdbarch, pc))
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{
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/* Execution stopped inside Xtensa Window Interrupt Handler. */
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xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
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/* Everything was set already, including cache->base. */
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return cache;
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}
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else /* Call0 framework. */
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{
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unsigned int litbase_regnum = gdbarch_tdep (gdbarch)->litbase_regnum;
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@ -1941,11 +2014,33 @@ typedef enum {
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c0opc_mov, /* Moving a register to a register. */
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c0opc_movi, /* Moving an immediate to a register. */
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c0opc_l32r, /* Loading a literal. */
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c0opc_s32i, /* Storing word at fixed offset from a base
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register. */
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c0opc_s32i, /* Storing word at fixed offset from a base register. */
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c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
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c0opc_l32e, /* L32E instruction. */
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c0opc_s32e, /* S32E instruction. */
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c0opc_rfwo, /* RFWO instruction. */
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c0opc_rfwu, /* RFWU instruction. */
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c0opc_NrOf /* Number of opcode classifications. */
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} xtensa_insn_kind;
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/* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
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static int
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rwx_special_register (const char *opcname)
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{
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char ch = *opcname++;
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if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
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return 0;
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if (*opcname++ != 's')
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return 0;
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if (*opcname++ != 'r')
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return 0;
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if (*opcname++ != '.')
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return 0;
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return 1;
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}
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/* Classify an opcode based on what it means for Call0 prologue analysis. */
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@ -1970,6 +2065,10 @@ call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
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opclass = c0opc_break;
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else if (strcasecmp (opcname, "entry") == 0)
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opclass = c0opc_entry;
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else if (strcasecmp (opcname, "rfwo") == 0)
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opclass = c0opc_rfwo;
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else if (strcasecmp (opcname, "rfwu") == 0)
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opclass = c0opc_rfwu;
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else if (xtensa_opcode_is_branch (isa, opc) > 0
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|| xtensa_opcode_is_jump (isa, opc) > 0
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|| xtensa_opcode_is_loop (isa, opc) > 0
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@ -1999,6 +2098,12 @@ call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
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else if (strcasecmp (opcname, "s32i") == 0
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|| strcasecmp (opcname, "s32i.n") == 0)
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opclass = c0opc_s32i;
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else if (strcasecmp (opcname, "l32e") == 0)
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opclass = c0opc_l32e;
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else if (strcasecmp (opcname, "s32e") == 0)
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opclass = c0opc_s32e;
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else if (rwx_special_register (opcname))
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opclass = c0opc_rwxsr;
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return opclass;
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}
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@ -2028,7 +2133,7 @@ call0_track_op (struct gdbarch *gdbarch,
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break;
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case c0opc_add:
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/* 3 operands: dst, src1, src2. */
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gdb_assert (nods == 3);
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gdb_assert (nods == 3);
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if (src[odv[1]].fr_reg == C0_CONST)
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{
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dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
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@ -2458,6 +2563,258 @@ analysis failed in this frame. GDB command execution stopped."));
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cache->c0.c0_fp = fp;
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}
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static CORE_ADDR a0_saved;
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static CORE_ADDR a7_saved;
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static CORE_ADDR a11_saved;
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static int a0_was_saved;
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static int a7_was_saved;
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static int a11_was_saved;
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/* Simulate L32E insn: AT <-- ref (AS + offset). */
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static void
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execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
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{
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int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
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int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
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CORE_ADDR addr = xtensa_read_register (asreg) + offset;
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unsigned int spilled_value
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= read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch));
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if ((at == 0) && !a0_was_saved)
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{
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a0_saved = xtensa_read_register (atreg);
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a0_was_saved = 1;
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}
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else if ((at == 7) && !a7_was_saved)
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{
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a7_saved = xtensa_read_register (atreg);
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a7_was_saved = 1;
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}
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else if ((at == 11) && !a11_was_saved)
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{
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a11_saved = xtensa_read_register (atreg);
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a11_was_saved = 1;
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}
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xtensa_write_register (atreg, spilled_value);
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}
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/* Simulate S32E insn: AT --> ref (AS + offset). */
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static void
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execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
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{
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int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
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int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
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CORE_ADDR addr = xtensa_read_register (asreg) + offset;
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ULONGEST spilled_value = xtensa_read_register (atreg);
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write_memory_unsigned_integer (addr, 4,
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gdbarch_byte_order (gdbarch),
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spilled_value);
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}
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#define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
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typedef enum {
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xtWindowOverflow,
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xtWindowUnderflow,
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xtNoExceptionHandler
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} xtensa_exception_handler_t;
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/* Execute insn stream from current PC until hitting RFWU or RFWO.
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Return type of Xtensa Window Interrupt Handler on success. */
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static xtensa_exception_handler_t
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execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
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{
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xtensa_isa isa;
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xtensa_insnbuf ins, slot;
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char ibuf[XTENSA_ISA_BSZ];
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CORE_ADDR ia, bt, ba;
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xtensa_format ifmt;
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int ilen, islots, is;
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xtensa_opcode opc;
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int insn_num = 0;
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int fail = 0;
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void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
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int at, as, offset;
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int num_operands;
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/* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
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int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
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isa = xtensa_default_isa;
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gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
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ins = xtensa_insnbuf_alloc (isa);
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slot = xtensa_insnbuf_alloc (isa);
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ba = 0;
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ia = current_pc;
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bt = ia;
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a0_was_saved = 0;
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a7_was_saved = 0;
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a11_was_saved = 0;
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while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
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{
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if (ia + xtensa_isa_maxlength (isa) > bt)
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{
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ba = ia;
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bt = (ba + XTENSA_ISA_BSZ);
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if (target_read_memory (ba, ibuf, bt - ba) != 0)
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return xtNoExceptionHandler;
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}
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xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
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ifmt = xtensa_format_decode (isa, ins);
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if (ifmt == XTENSA_UNDEFINED)
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return xtNoExceptionHandler;
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ilen = xtensa_format_length (isa, ifmt);
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if (ilen == XTENSA_UNDEFINED)
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return xtNoExceptionHandler;
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islots = xtensa_format_num_slots (isa, ifmt);
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if (islots == XTENSA_UNDEFINED)
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return xtNoExceptionHandler;
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for (is = 0; is < islots; ++is)
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{
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if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
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return xtNoExceptionHandler;
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opc = xtensa_opcode_decode (isa, ifmt, is, slot);
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if (opc == XTENSA_UNDEFINED)
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return xtNoExceptionHandler;
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switch (call0_classify_opcode (isa, opc))
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{
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case c0opc_illegal:
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case c0opc_flow:
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case c0opc_entry:
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case c0opc_break:
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/* We expect none of them here. */
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return xtNoExceptionHandler;
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case c0opc_l32e:
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func = execute_l32e;
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break;
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case c0opc_s32e:
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func = execute_s32e;
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break;
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case c0opc_rfwo: /* RFWO. */
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/* Here, we return from WindowOverflow handler and,
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if we stopped at the very beginning, which means
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A0 was saved, we have to restore it now. */
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if (a0_was_saved)
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{
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int arreg = arreg_number (gdbarch,
|
||||
gdbarch_tdep (gdbarch)->a0_base,
|
||||
wb);
|
||||
xtensa_write_register (arreg, a0_saved);
|
||||
}
|
||||
return xtWindowOverflow;
|
||||
case c0opc_rfwu: /* RFWU. */
|
||||
/* Here, we return from WindowUnderflow handler.
|
||||
Let's see if either A7 or A11 has to be restored. */
|
||||
if (WindowUnderflow12)
|
||||
{
|
||||
if (a11_was_saved)
|
||||
{
|
||||
int arreg = arreg_number (gdbarch,
|
||||
gdbarch_tdep (gdbarch)->a0_base + 11,
|
||||
wb);
|
||||
xtensa_write_register (arreg, a11_saved);
|
||||
}
|
||||
}
|
||||
else if (a7_was_saved)
|
||||
{
|
||||
int arreg = arreg_number (gdbarch,
|
||||
gdbarch_tdep (gdbarch)->a0_base + 7,
|
||||
wb);
|
||||
xtensa_write_register (arreg, a7_saved);
|
||||
}
|
||||
return xtWindowUnderflow;
|
||||
default: /* Simply skip this insns. */
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Decode arguments for L32E / S32E and simulate their execution. */
|
||||
if ( xtensa_opcode_num_operands (isa, opc) != 3 )
|
||||
return xtNoExceptionHandler;
|
||||
if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
|
||||
return xtNoExceptionHandler;
|
||||
if (xtensa_operand_decode (isa, opc, 0, &at))
|
||||
return xtNoExceptionHandler;
|
||||
if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
|
||||
return xtNoExceptionHandler;
|
||||
if (xtensa_operand_decode (isa, opc, 1, &as))
|
||||
return xtNoExceptionHandler;
|
||||
if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
|
||||
return xtNoExceptionHandler;
|
||||
if (xtensa_operand_decode (isa, opc, 2, &offset))
|
||||
return xtNoExceptionHandler;
|
||||
|
||||
(*func) (gdbarch, at, as, offset, wb);
|
||||
}
|
||||
|
||||
ia += ilen;
|
||||
}
|
||||
return xtNoExceptionHandler;
|
||||
}
|
||||
|
||||
/* Handle Window Overflow / Underflow exception frames. */
|
||||
|
||||
static void
|
||||
xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
|
||||
xtensa_frame_cache_t *cache,
|
||||
CORE_ADDR pc)
|
||||
{
|
||||
struct gdbarch *gdbarch = get_frame_arch (this_frame);
|
||||
CORE_ADDR ps, wb, ws, ra;
|
||||
int epc1_regnum, i, regnum;
|
||||
xtensa_exception_handler_t eh_type;
|
||||
|
||||
/* Read PS, WB, and WS from the hardware. Note that PS register
|
||||
must be present, if Windowed ABI is supported. */
|
||||
ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch));
|
||||
wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum);
|
||||
ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum);
|
||||
|
||||
/* Execute all the remaining instructions from Window Interrupt Handler
|
||||
by simulating them on the remote protocol level. On return, set the
|
||||
type of Xtensa Window Interrupt Handler, or report an error. */
|
||||
eh_type = execute_code (gdbarch, pc, wb);
|
||||
if (eh_type == xtNoExceptionHandler)
|
||||
error (_("\
|
||||
Unable to decode Xtensa Window Interrupt Handler's code."));
|
||||
|
||||
cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
|
||||
cache->call0 = 0; /* It's Windowed ABI. */
|
||||
|
||||
/* All registers for the cached frame will be alive. */
|
||||
for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
|
||||
cache->wd.aregs[i] = -1;
|
||||
|
||||
if (eh_type == xtWindowOverflow)
|
||||
cache->wd.ws = ws ^ (1 << wb);
|
||||
else /* eh_type == xtWindowUnderflow. */
|
||||
cache->wd.ws = ws | (1 << wb);
|
||||
|
||||
cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
|
||||
regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base,
|
||||
cache->wd.wb);
|
||||
ra = xtensa_read_register (regnum);
|
||||
cache->wd.callsize = WINSIZE (ra);
|
||||
cache->prev_sp = xtensa_read_register (regnum + 1);
|
||||
/* Set regnum to a frame pointer of the frame being cached. */
|
||||
regnum = xtensa_scan_prologue (gdbarch, pc);
|
||||
regnum = arreg_number (gdbarch,
|
||||
gdbarch_tdep (gdbarch)->a0_base + regnum,
|
||||
cache->wd.wb);
|
||||
cache->base = get_frame_register_unsigned (this_frame, regnum);
|
||||
|
||||
/* Read PC of interrupted function from EPC1 register. */
|
||||
epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
|
||||
if (epc1_regnum < 0)
|
||||
error(_("Unable to read Xtensa register EPC1"));
|
||||
cache->ra = xtensa_read_register (epc1_regnum);
|
||||
cache->pc = get_frame_func (this_frame);
|
||||
}
|
||||
|
||||
|
||||
/* Skip function prologue.
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue