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Fix inifnite loop problem with M32R port

This commit is contained in:
Nick Clifton 2004-04-13 16:47:58 +00:00
parent 58e23df49e
commit 097dba1357
6 changed files with 55 additions and 7 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2004-04-13 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* config/tc-m32r.c (md_assemble): Fixed infinite loop bug
in parallel.
2004-04-11 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> 2004-04-11 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
* Makefile.am: Remove mips from aout targets. * Makefile.am: Remove mips from aout targets.

34
gas/config/tc-m32r.c
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@ -1382,6 +1382,14 @@ md_assemble (str)
prev_insn.insn is NULL when we're on a 32 bit boundary. */ prev_insn.insn is NULL when we're on a 32 bit boundary. */
on_32bit_boundary_p = prev_insn.insn == NULL; on_32bit_boundary_p = prev_insn.insn == NULL;
/* Change a frag to, if each insn to swap is in a different frag.
It must keep only one instruction in a frag. */
if (parallel() && on_32bit_boundary_p)
{
frag_wane (frag_now);
frag_new (0);
}
/* Look to see if this instruction can be combined with the /* Look to see if this instruction can be combined with the
previous instruction to make one, parallel, 32 bit instruction. previous instruction to make one, parallel, 32 bit instruction.
If the previous instruction (potentially) changed the flow of If the previous instruction (potentially) changed the flow of
@ -1442,13 +1450,25 @@ md_assemble (str)
else if (insn.frag->fr_opcode == insn.addr) else if (insn.frag->fr_opcode == insn.addr)
insn.frag->fr_opcode = prev_insn.addr; insn.frag->fr_opcode = prev_insn.addr;
/* Update the addresses in any fixups. /* Change a frag to, if each insn is in a different frag.
Note that we don't have to handle the case where each insn is in It must keep only one instruction in a frag. */
a different frag as we ensure they're in the same frag above. */ if (prev_insn.frag != insn.frag)
for (i = 0; i < prev_insn.num_fixups; ++i) {
prev_insn.fixups[i]->fx_where += 2; for (i = 0; i < prev_insn.num_fixups; ++i)
for (i = 0; i < insn.num_fixups; ++i) prev_insn.fixups[i]->fx_frag = insn.frag;
insn.fixups[i]->fx_where -= 2; for (i = 0; i < insn.num_fixups; ++i)
insn.fixups[i]->fx_frag = prev_insn.frag;
}
else
{
/* Update the addresses in any fixups.
Note that we don't have to handle the case where each insn is in
a different frag as we ensure they're in the same frag above. */
for (i = 0; i < prev_insn.num_fixups; ++i)
prev_insn.fixups[i]->fx_where += 2;
for (i = 0; i < insn.num_fixups; ++i)
insn.fixups[i]->fx_where -= 2;
}
} }
/* Keep track of whether we've seen a pair of 16 bit insns. /* Keep track of whether we've seen a pair of 16 bit insns.

5
gas/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2004-04-13 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* gas/m32r/parallel-2.s, gas/m32r/parallel-2.d: Add a new test
case for parallel code.
2004-04-01 Asgari Jinia <asgarij@kpitcummins.com> 2004-04-01 Asgari Jinia <asgarij@kpitcummins.com>
* gas/sh/renesas-1.s, gas/sh/renesas-1.d: New test for -renesas * gas/sh/renesas-1.s, gas/sh/renesas-1.d: New test for -renesas

1
gas/testsuite/gas/m32r/m32r2.exp
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@ -2,4 +2,5 @@
if [istarget m32r*-*-*] { if [istarget m32r*-*-*] {
run_dump_test "m32r2" run_dump_test "m32r2"
run_dump_test "parallel-2"
} }

10
gas/testsuite/gas/m32r/parallel-2.d Normal file
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@ -0,0 +1,10 @@
#as: -m32r2 -O
#objdump: -dr
.*: +file format .*
Disassembly of section .text:
0+0000 <test>:
0: 04 a5 24 46 add r4,r5 -> st r4,@r6
4: 7c ff c6 04 bc 0 <test> \|\| addi r6,[#]4

7
gas/testsuite/gas/m32r/parallel-2.s Normal file
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@ -0,0 +1,7 @@
.text
test:
add r4,r5
st r4,@(r6)
addi r6,#4
.debugsym .LM568
bc.s test