include:
* opcode/arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, and ARM_ARCH_V6ZKT2. opcodes: * arm-dis.c (arm_opcodes): Document %E and %V. Add entries for v6T2 ARM instructions: bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx. (print_insn_arm): Add support for %E and %V.
This commit is contained in:
Zack Weinberg
parent
f1210edfba
commit
0a003adc41
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@ -1,3 +1,9 @@
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2005-03-12 Zack Weinberg <zack@codesourcery.com>
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* opcode/arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
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Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
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and ARM_ARCH_V6ZKT2.
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2005-03-09 Mark Mitchell <mark@codesourcery.com>
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* libiberty.h (gettimeofday): Declare.
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@ -58,7 +64,7 @@
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* dis-asm.h: Add prototype for print_insn_maxq_little.
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2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
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* opcode/crx.h (enum argtype): Rename types, remove unused types.
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2004-10-27 Richard Earnshaw <rearnsha@arm.com>
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@ -71,7 +77,7 @@
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(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
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(enum operand_type): Rearrange operands, edit comments.
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replace us<N> with ui<N> for unsigned immediate.
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replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
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replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
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displacements (respectively).
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replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
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(instruction type): Add NO_TYPE_INS.
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@ -25,15 +25,16 @@
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#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
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#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
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#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
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#define ARM_EXT_V4T 0x00000040 /* Thumb v1. */
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#define ARM_EXT_V4T 0x00000040 /* Thumb. */
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#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
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#define ARM_EXT_V5T 0x00000100 /* Thumb v2. */
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#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
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#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
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#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
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#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
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#define ARM_EXT_V6 0x00001000 /* ARM V6. */
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#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
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#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */
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#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
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/* Co-processor space extensions. */
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#define ARM_CEXT_XSCALE 0x00800000 /* Allow MIA etc. */
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@ -65,6 +66,10 @@
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#define ARM_ARCH_V6K (ARM_ARCH_V6 | ARM_EXT_V6K)
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#define ARM_ARCH_V6Z (ARM_ARCH_V6 | ARM_EXT_V6Z)
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#define ARM_ARCH_V6ZK (ARM_ARCH_V6 | ARM_EXT_V6K | ARM_EXT_V6Z)
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#define ARM_ARCH_V6T2 (ARM_ARCH_V6 | ARM_EXT_V6T2)
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#define ARM_ARCH_V6KT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6K)
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#define ARM_ARCH_V6ZT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6Z)
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#define ARM_ARCH_V6ZKT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)
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/* Processors with specific extensions in the co-processor space. */
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#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_CEXT_XSCALE)
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@ -1,3 +1,10 @@
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2005-03-12 Zack Weinberg <zack@codesourcery.com>
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* arm-dis.c (arm_opcodes): Document %E and %V.
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Add entries for v6T2 ARM instructions:
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bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
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(print_insn_arm): Add support for %E and %V.
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2005-03-10 Jeff Baker <jbaker@qnx.com>
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Alan Modra <amodra@bigpond.net.au>
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@ -5,7 +12,7 @@
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(powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
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(SPRG_MASK): Delete.
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(XSPRG_MASK): Mask off extra bits now part of sprg field.
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(powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
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(powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
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mfsprg4..7 after msprg and consolidate.
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2005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
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@ -81,6 +81,8 @@
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%m print register mask for ldm/stm instruction
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%C print the PSR sub type.
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%F print the COUNT field of a LFM/SFM instruction.
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%E print the LSB and WIDTH fields of a BFI or BFC instruction.
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%V print the 16-bit immediate field of a MOVT or MOVW instruction.
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IWMMXT specific format options:
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%<bitfield>g print as an iWMMXt 64-bit register
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%<bitfield>G print as an iWMMXt general purpose or control register
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@ -118,6 +120,17 @@ static const struct arm_opcode arm_opcodes[] =
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{ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
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{ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
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/* ARM V6T2 instructions. */
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{ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
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{ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
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{ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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{ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"},
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{ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"},
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{ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
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{ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
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{ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
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{ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
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/* ARM V6Z instructions. */
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{ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smi%c\t%e"},
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@ -622,6 +635,13 @@ static const struct thumb_opcode thumb_opcodes[] =
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{
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/* Thumb instructions. */
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/* ARM V6K no-argument instructions. */
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{ARM_EXT_V6K, 0xbf00, 0xffff, "nop"},
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{ARM_EXT_V6K, 0xbf10, 0xffff, "yield"},
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{ARM_EXT_V6K, 0xbf20, 0xffff, "wfe"},
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{ARM_EXT_V6K, 0xbf30, 0xffff, "wfi"},
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{ARM_EXT_V6K, 0xbf40, 0xffff, "sev"},
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/* ARM V6. */
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{ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"},
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{ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"},
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@ -929,7 +949,13 @@ print_insn_arm (pc, info, given)
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&& info->mach != bfd_mach_arm_iWMMXt)
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insn = insn + IWMMXT_INSN_COUNT;
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if ((given & insn->mask) == insn->value)
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if ((given & insn->mask) == insn->value
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/* Special case: an instruction with all bits set in the condition field
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(0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
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or by the catchall at the end of the table. */
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&& ((given & 0xF0000000) != 0xF0000000
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|| (insn->mask & 0xF0000000) == 0xF0000000
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|| (insn->mask == 0 && insn->value == 0)))
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{
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char * c;
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@ -1613,6 +1639,32 @@ print_insn_arm (pc, info, given)
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}
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break;
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case 'E':
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/* LSB and WIDTH fields of BFI or BFC. The machine-
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language instruction encodes LSB and MSB. */
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{
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long msb = (given & 0x001f0000) >> 16;
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long lsb = (given & 0x00000f80) >> 7;
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long width = msb - lsb + 1;
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if (width > 0)
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func (stream, "#%lu, #%lu", lsb, width);
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else
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func (stream, "(invalid: %lu:%lu)", lsb, msb);
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}
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break;
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case 'V':
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/* 16-bit unsigned immediate from a MOVT or MOVW
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instruction, encoded in bits 0:11 and 15:19. */
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{
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long hi = (given & 0x000f0000) >> 4;
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long lo = (given & 0x00000fff);
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long imm16 = hi | lo;
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func (stream, "#%lu\t; 0x%lx", imm16, imm16);
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}
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break;
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default:
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abort ();
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}
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