gdb/riscv: Remove redundant code, and catch more errors when accessing MISA
When reading the MISA register, the RISC-V specification says that, if MISA can't be found then a default value of 0 should be assumed. As such, this patch ensures that GDB ignores errors when accessing both the new and old locations for the MISA register. Additionally, this patch removes an unneeded flag parameter which didn't provide any additional functionality beyond checking the MISA for the default value of 0. gdb/ChangeLog: * riscv-tdep.c (riscv_read_misa_reg): Update comment, remove READ_P parameter, catch and ignore register access errors from either the old or new MISA location. (riscv_has_feature): Update call to riscv_read_misa_reg.
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@ -1,3 +1,10 @@
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2018-10-26 Andrew Burgess <andrew.burgess@embecosm.com>
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* riscv-tdep.c (riscv_read_misa_reg): Update comment, remove
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READ_P parameter, catch and ignore register access errors from
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either the old or new MISA location.
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(riscv_has_feature): Update call to riscv_read_misa_reg.
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2018-10-25 Andrew Burgess <andrew.burgess@embecosm.com>
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2018-10-25 Andrew Burgess <andrew.burgess@embecosm.com>
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* python/py-function.c (convert_values_to_python): Return
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* python/py-function.c (convert_values_to_python): Return
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@ -290,34 +290,44 @@ static unsigned int riscv_debug_infcall = 0;
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static unsigned int riscv_debug_unwinder = 0;
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static unsigned int riscv_debug_unwinder = 0;
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/* Read the MISA register from the target. The register will only be read
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/* Read the MISA register from the target. There are a couple of locations
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once, and the value read will be cached. If the register can't be read
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that the register might be found, these are all tried. If the MISA
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from the target then a default value (0) will be returned. If the
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register can't be found at all then the default value of 0 is returned,
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pointer READ_P is not null, then the bool pointed to is updated to
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this is inline with the RISC-V specification. */
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indicate if the value returned was read from the target (true) or is the
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default (false). */
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static uint32_t
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static uint32_t
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riscv_read_misa_reg (bool *read_p)
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riscv_read_misa_reg ()
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{
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{
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uint32_t value = 0;
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uint32_t value = 0;
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if (target_has_registers)
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if (target_has_registers)
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{
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{
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/* Old cores might have MISA located at a different offset. */
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static int misa_regs[] =
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{ RISCV_CSR_MISA_REGNUM, RISCV_CSR_LEGACY_MISA_REGNUM };
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struct frame_info *frame = get_current_frame ();
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struct frame_info *frame = get_current_frame ();
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for (int i = 0; i < ARRAY_SIZE (misa_regs); ++i)
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{
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bool success = false;
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TRY
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TRY
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{
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{
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value = get_frame_register_unsigned (frame,
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value = get_frame_register_unsigned (frame, misa_regs[i]);
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RISCV_CSR_MISA_REGNUM);
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success = true;
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}
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}
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CATCH (ex, RETURN_MASK_ERROR)
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CATCH (ex, RETURN_MASK_ERROR)
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{
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{
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/* Old cores might have MISA located at a different offset. */
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/* Ignore errors, it is acceptable for a target to not
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value = get_frame_register_unsigned (frame,
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provide a MISA register, in which case the default value
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RISCV_CSR_LEGACY_MISA_REGNUM);
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of 0 should be used. */
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}
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}
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END_CATCH
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END_CATCH
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if (success)
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break;
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}
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}
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}
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return value;
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return value;
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@ -330,13 +340,10 @@ riscv_read_misa_reg (bool *read_p)
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static bool
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static bool
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riscv_has_feature (struct gdbarch *gdbarch, char feature)
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riscv_has_feature (struct gdbarch *gdbarch, char feature)
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{
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{
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bool have_read_misa = false;
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uint32_t misa;
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gdb_assert (feature >= 'A' && feature <= 'Z');
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gdb_assert (feature >= 'A' && feature <= 'Z');
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misa = riscv_read_misa_reg (&have_read_misa);
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uint32_t misa = riscv_read_misa_reg ();
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if (!have_read_misa || misa == 0)
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if (misa == 0)
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misa = gdbarch_tdep (gdbarch)->core_features;
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misa = gdbarch_tdep (gdbarch)->core_features;
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return (misa & (1 << (feature - 'A'))) != 0;
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return (misa & (1 << (feature - 'A'))) != 0;
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