gas/
2007-03-15 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am: Run "make dep-am". * Makefile.in: Regenerated. * config/tc-i386.c: Include "opcodes/i386-opc.h" instead of "opcode/i386.h". (md_begin): Check reg_name != NULL for the last entry in i386_regtab. * config/tc-i386.h: Move many entries to opcode/i386.h and opcodes/i386-opc.h. * configure.in (need_opcodes): Set true for i386. * configure: Regenerated. include/opcode/ 2007-03-15 H.J. Lu <hongjiu.lu@intel.com> * i386.h: Add entries from config/tc-i386.h and move tables to opcodes/i386-opc.h. opcodes/ 2007-03-15 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am (CFILES): Add i386-opc.c. (ALL_MACHINES): Add i386-opc.lo. Run "make dep-am". * Makefile.in: Regenerated. * configure.in: Add i386-opc.lo for bfd_i386_arch. * configure: Regenerated. * i386-dis.c: Include "opcode/i386.h". (MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition. (FWAIT_OPCODE): Remove definition. (UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition. (MAX_OPERANDS): Remove definition. * i386-opc.c: New file. * i386-opc.h: Likewise.
This commit is contained in:
parent
187b3d5d7f
commit
0b1cf022c8
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@ -1,3 +1,19 @@
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2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
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* Makefile.am: Run "make dep-am".
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* Makefile.in: Regenerated.
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* config/tc-i386.c: Include "opcodes/i386-opc.h" instead of
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"opcode/i386.h".
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(md_begin): Check reg_name != NULL for the last entry in
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i386_regtab.
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* config/tc-i386.h: Move many entries to opcode/i386.h and
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opcodes/i386-opc.h.
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* configure.in (need_opcodes): Set true for i386.
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* configure: Regenerated.
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2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
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* Makefile.am (REPORT_BUGS_TO): Removed.
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@ -1119,20 +1119,20 @@ DEPTC_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
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DEPTC_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
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$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
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subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
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$(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h \
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$(INCDIR)/elf/reloc-macros.h
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$(INCDIR)/elf/dwarf2.h $(srcdir)/../opcodes/i386-opc.h \
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$(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
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DEPTC_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
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$(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
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$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
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subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
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$(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h \
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$(INCDIR)/elf/reloc-macros.h
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$(INCDIR)/elf/dwarf2.h $(srcdir)/../opcodes/i386-opc.h \
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$(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
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DEPTC_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
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$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
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$(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h dwarf2dbg.h \
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$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
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dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
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$(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
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dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(srcdir)/../opcodes/i386-opc.h \
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$(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
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DEPTC_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
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$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
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$(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
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@ -888,22 +888,22 @@ DEPTC_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
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DEPTC_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
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$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
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subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
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$(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h \
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$(INCDIR)/elf/reloc-macros.h
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$(INCDIR)/elf/dwarf2.h $(srcdir)/../opcodes/i386-opc.h \
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$(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
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DEPTC_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
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$(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
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$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
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subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
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$(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h \
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$(INCDIR)/elf/reloc-macros.h
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$(INCDIR)/elf/dwarf2.h $(srcdir)/../opcodes/i386-opc.h \
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$(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
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DEPTC_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
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$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
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$(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h dwarf2dbg.h \
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$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
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dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
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$(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
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dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(srcdir)/../opcodes/i386-opc.h \
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$(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
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DEPTC_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
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$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
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@ -32,7 +32,7 @@
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#include "subsegs.h"
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#include "dwarf2dbg.h"
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#include "dw2gencfi.h"
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#include "opcode/i386.h"
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#include "opcodes/i386-opc.h"
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#include "elf/x86-64.h"
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#ifndef REGISTER_WARNINGS
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{
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const reg_entry *regtab;
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for (regtab = i386_regtab;
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regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
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regtab++)
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for (regtab = i386_regtab; regtab->reg_name != NULL; regtab++)
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{
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hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
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if (hash_err)
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@ -96,10 +96,6 @@ extern const char extra_symbol_chars[];
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extern const char *i386_comment_chars;
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#define tc_comment_chars i386_comment_chars
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#define MAX_OPERANDS 4 /* max operands per insn */
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#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp, insertq, extrq) */
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#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
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/* Prefixes will be emitted in the order defined below.
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WAIT_PREFIX must be the first prefix since FWAIT is really is an
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instruction, and so must come before any prefixes.
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@ -118,21 +114,6 @@ extern const char *i386_comment_chars;
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#define IMMEDIATE_PREFIX '$'
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#define ABSOLUTE_PREFIX '*'
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#define TWO_BYTE_OPCODE_ESCAPE 0x0f
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#define NOP_OPCODE (char) 0x90
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/* register numbers */
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#define EBP_REG_NUM 5
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#define ESP_REG_NUM 4
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/* modrm_byte.regmem for twobyte escape */
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#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
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/* index_base_byte.index for no index register addressing */
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#define NO_INDEX_REGISTER ESP_REG_NUM
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/* index_base_byte.base for no base register addressing */
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#define NO_BASE_REGISTER EBP_REG_NUM
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#define NO_BASE_REGISTER_16 6
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/* these are the instruction mnemonic suffixes. */
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#define WORD_MNEM_SUFFIX 'w'
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#define BYTE_MNEM_SUFFIX 'b'
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/* Intel Syntax */
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#define LONG_DOUBLE_MNEM_SUFFIX 'x'
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/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
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#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
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#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
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#define END_OF_INSN '\0'
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typedef struct
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{
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/* instruction name sans width suffix ("mov" for movl insns) */
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char *name;
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/* how many operands */
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unsigned int operands;
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/* base_opcode is the fundamental opcode byte without optional
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prefix(es). */
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unsigned int base_opcode;
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#define Opcode_D 0x2 /* Direction bit:
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set if Reg --> Regmem;
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unset if Regmem --> Reg. */
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#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
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#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
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/* extension_opcode is the 3 bit extension for group <n> insns.
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This field is also used to store the 8-bit opcode suffix for the
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AMD 3DNow! instructions.
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If this template has no extension opcode (the usual case) use None */
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unsigned int extension_opcode;
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#define None 0xffff /* If no extension_opcode is possible. */
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/* cpu feature flags */
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unsigned int cpu_flags;
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#define Cpu186 0x1 /* i186 or better required */
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#define Cpu286 0x2 /* i286 or better required */
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#define Cpu386 0x4 /* i386 or better required */
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#define Cpu486 0x8 /* i486 or better required */
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#define Cpu586 0x10 /* i585 or better required */
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#define Cpu686 0x20 /* i686 or better required */
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#define CpuP4 0x40 /* Pentium4 or better required */
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#define CpuK6 0x80 /* AMD K6 or better required*/
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#define CpuSledgehammer 0x100 /* Sledgehammer or better required */
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#define CpuMMX 0x200 /* MMX support required */
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#define CpuMMX2 0x400 /* extended MMX support (with SSE or 3DNow!Ext) required */
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#define CpuSSE 0x800 /* Streaming SIMD extensions required */
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#define CpuSSE2 0x1000 /* Streaming SIMD extensions 2 required */
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#define Cpu3dnow 0x2000 /* 3dnow! support required */
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#define Cpu3dnowA 0x4000 /* 3dnow!Extensions support required */
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#define CpuSSE3 0x8000 /* Streaming SIMD extensions 3 required */
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#define CpuPadLock 0x10000 /* VIA PadLock required */
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#define CpuSVME 0x20000 /* AMD Secure Virtual Machine Ext-s required */
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#define CpuVMX 0x40000 /* VMX Instructions required */
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#define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */
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#define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */
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#define CpuABM 0x200000 /* ABM New Instructions required */
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/* These flags are set by gas depending on the flag_code. */
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#define Cpu64 0x4000000 /* 64bit support required */
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#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
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/* The default value for unknown CPUs - enable all features to avoid problems. */
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#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
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|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a)
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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the same instruction */
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unsigned int opcode_modifier;
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/* opcode_modifier bits: */
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#define D 0x1 /* has direction bit. */
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#define W 0x2 /* set if operands can be words or dwords
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encoded the canonical way */
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#define Modrm 0x4 /* insn has a modrm byte. */
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#define ShortForm 0x10 /* register is in low 3 bits of opcode */
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#define Jump 0x40 /* special case for jump insns. */
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#define JumpDword 0x80 /* call and jump */
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#define JumpByte 0x100 /* loop and jecxz */
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#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
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#define FloatMF 0x400 /* FP insn memory format bit, sized by 0x4 */
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#define FloatR 0x800 /* src/dest swap for floats. */
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#define FloatD 0x1000 /* has float insn direction bit. */
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#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
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#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
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#define Size64 0x8000 /* needs size prefix if in 64-bit mode */
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#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
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#define DefaultSize 0x20000 /* default insn size depends on mode */
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#define No_bSuf 0x40000 /* b suffix on instruction illegal */
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#define No_wSuf 0x80000 /* w suffix on instruction illegal */
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#define No_lSuf 0x100000 /* l suffix on instruction illegal */
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#define No_sSuf 0x200000 /* s suffix on instruction illegal */
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#define No_qSuf 0x400000 /* q suffix on instruction illegal */
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#define No_xSuf 0x800000 /* x suffix on instruction illegal */
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#define FWait 0x1000000 /* instruction needs FWAIT */
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#define IsString 0x2000000 /* quick test for string instructions */
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#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
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#define IsPrefix 0x8000000 /* opcode is a prefix */
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#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
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#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
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#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
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#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
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/* operand_types[i] describes the type of operand i. This is made
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by OR'ing together all of the possible type masks. (e.g.
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'operand_types[i] = Reg|Imm' specifies that operand i can be
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either a register or an immediate operand. */
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unsigned int operand_types[MAX_OPERANDS];
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/* operand_types[i] bits */
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/* register */
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#define Reg8 0x1 /* 8 bit reg */
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#define Reg16 0x2 /* 16 bit reg */
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#define Reg32 0x4 /* 32 bit reg */
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#define Reg64 0x8 /* 64 bit reg */
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/* immediate */
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#define Imm8 0x10 /* 8 bit immediate */
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#define Imm8S 0x20 /* 8 bit immediate sign extended */
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#define Imm16 0x40 /* 16 bit immediate */
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#define Imm32 0x80 /* 32 bit immediate */
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#define Imm32S 0x100 /* 32 bit immediate sign extended */
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#define Imm64 0x200 /* 64 bit immediate */
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#define Imm1 0x400 /* 1 bit immediate */
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/* memory */
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#define BaseIndex 0x800
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/* Disp8,16,32 are used in different ways, depending on the
|
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instruction. For jumps, they specify the size of the PC relative
|
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displacement, for baseindex type instructions, they specify the
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size of the offset relative to the base register, and for memory
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offset instructions such as `mov 1234,%al' they specify the size of
|
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the offset relative to the segment base. */
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#define Disp8 0x1000 /* 8 bit displacement */
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#define Disp16 0x2000 /* 16 bit displacement */
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#define Disp32 0x4000 /* 32 bit displacement */
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#define Disp32S 0x8000 /* 32 bit signed displacement */
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#define Disp64 0x10000 /* 64 bit displacement */
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/* specials */
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#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
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#define ShiftCount 0x40000 /* register to hold shift count = cl */
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#define Control 0x80000 /* Control register */
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#define Debug 0x100000 /* Debug register */
|
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#define Test 0x200000 /* Test register */
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#define FloatReg 0x400000 /* Float register */
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#define FloatAcc 0x800000 /* Float stack top %st(0) */
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#define SReg2 0x1000000 /* 2 bit segment register */
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#define SReg3 0x2000000 /* 3 bit segment register */
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#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
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#define JumpAbsolute 0x8000000
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#define RegMMX 0x10000000 /* MMX register */
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#define RegXMM 0x20000000 /* XMM registers in PIII */
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#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
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/* InvMem is for instructions with a modrm byte that only allow a
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general register encoding in the i.tm.mode and i.tm.regmem fields,
|
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eg. control reg moves. They really ought to support a memory form,
|
||||
but don't, so we add an InvMem flag to the register operand to
|
||||
indicate that it should be encoded in the i.tm.regmem field. */
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#define InvMem 0x80000000
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#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
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#define WordReg (Reg16|Reg32|Reg64)
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#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
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#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
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#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
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#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
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#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
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/* The following aliases are defined because the opcode table
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carefully specifies the allowed memory types for each instruction.
|
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At the moment we can only tell a memory reference size by the
|
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instruction suffix, so there's not much point in defining Mem8,
|
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Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
|
||||
the suffix directly to check memory operands. */
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#define LLongMem AnyMem /* 64 bits (or more) */
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#define LongMem AnyMem /* 32 bit memory ref */
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||||
#define ShortMem AnyMem /* 16 bit memory ref */
|
||||
#define WordMem AnyMem /* 16, 32 or 64 bit memory ref */
|
||||
#define ByteMem AnyMem /* 8 bit memory ref */
|
||||
}
|
||||
template;
|
||||
|
||||
/*
|
||||
'templates' is for grouping together 'template' structures for opcodes
|
||||
of the same name. This is only used for storing the insns in the grand
|
||||
|
@ -328,32 +132,15 @@ template;
|
|||
The templates themselves start at START and range up to (but not including)
|
||||
END.
|
||||
*/
|
||||
struct template;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
const template *start;
|
||||
const template *end;
|
||||
const struct template *start;
|
||||
const struct template *end;
|
||||
}
|
||||
templates;
|
||||
|
||||
/* these are for register name --> number & type hash lookup */
|
||||
typedef struct
|
||||
{
|
||||
char *reg_name;
|
||||
unsigned int reg_type;
|
||||
unsigned int reg_flags;
|
||||
#define RegRex 0x1 /* Extended register. */
|
||||
#define RegRex64 0x2 /* Extended 8 bit register. */
|
||||
unsigned int reg_num;
|
||||
}
|
||||
reg_entry;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
char *seg_name;
|
||||
unsigned int seg_prefix;
|
||||
}
|
||||
seg_entry;
|
||||
|
||||
/* 386 operand encoding bytes: see 386 book for details of this. */
|
||||
typedef struct
|
||||
{
|
||||
|
@ -365,16 +152,6 @@ modrm_byte;
|
|||
|
||||
/* x86-64 extension prefix. */
|
||||
typedef int rex_byte;
|
||||
#define REX_OPCODE 0x40
|
||||
|
||||
/* Indicates 64 bit operand size. */
|
||||
#define REX_MODE64 8
|
||||
/* High extension to reg field of modrm byte. */
|
||||
#define REX_EXTX 4
|
||||
/* High extension to SIB index field. */
|
||||
#define REX_EXTY 2
|
||||
/* High extension to base field of modrm or SIB, or reg field of opcode. */
|
||||
#define REX_EXTZ 1
|
||||
|
||||
/* 386 opcode byte to code indirect addressing. */
|
||||
typedef struct
|
||||
|
|
|
@ -4732,7 +4732,7 @@ _ACEOF
|
|||
|
||||
# Do we need the opcodes library?
|
||||
case ${cpu_type} in
|
||||
vax | i386 | tic30)
|
||||
vax | tic30)
|
||||
;;
|
||||
|
||||
*)
|
||||
|
|
|
@ -258,7 +258,7 @@ changequote([,])dnl
|
|||
|
||||
# Do we need the opcodes library?
|
||||
case ${cpu_type} in
|
||||
vax | i386 | tic30)
|
||||
vax | tic30)
|
||||
;;
|
||||
|
||||
*)
|
||||
|
|
|
@ -1,3 +1,8 @@
|
|||
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386.h: Add entries from config/tc-i386.h and move tables
|
||||
to opcodes/i386-opc.h.
|
||||
|
||||
2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386.h (FloatDR): Removed.
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,3 +1,22 @@
|
|||
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* Makefile.am (CFILES): Add i386-opc.c.
|
||||
(ALL_MACHINES): Add i386-opc.lo.
|
||||
Run "make dep-am".
|
||||
* Makefile.in: Regenerated.
|
||||
|
||||
* configure.in: Add i386-opc.lo for bfd_i386_arch.
|
||||
* configure: Regenerated.
|
||||
|
||||
* i386-dis.c: Include "opcode/i386.h".
|
||||
(MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition.
|
||||
(FWAIT_OPCODE): Remove definition.
|
||||
(UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition.
|
||||
(MAX_OPERANDS): Remove definition.
|
||||
|
||||
* i386-opc.c: New file.
|
||||
* i386-opc.h: Likewise.
|
||||
|
||||
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* Makefile.in: Regenerated.
|
||||
|
|
|
@ -93,6 +93,7 @@ CFILES = \
|
|||
i370-dis.c \
|
||||
i370-opc.c \
|
||||
i386-dis.c \
|
||||
i386-opc.c \
|
||||
i860-dis.c \
|
||||
i960-dis.c \
|
||||
ia64-dis.c \
|
||||
|
@ -238,6 +239,7 @@ ALL_MACHINES = \
|
|||
h8500-dis.lo \
|
||||
hppa-dis.lo \
|
||||
i386-dis.lo \
|
||||
i386-opc.lo \
|
||||
i370-dis.lo \
|
||||
i370-opc.lo \
|
||||
i860-dis.lo \
|
||||
|
@ -777,7 +779,9 @@ i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
|
|||
$(INCDIR)/opcode/i370.h
|
||||
i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
|
||||
$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
|
||||
$(INCDIR)/ansidecl.h opintl.h
|
||||
$(INCDIR)/ansidecl.h opintl.h $(INCDIR)/opcode/i386.h
|
||||
i386-opc.lo: i386-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
|
||||
i386-opc.h $(INCDIR)/opcode/i386.h
|
||||
i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
|
||||
$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/i860.h
|
||||
i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
|
||||
|
|
|
@ -307,6 +307,7 @@ CFILES = \
|
|||
i370-dis.c \
|
||||
i370-opc.c \
|
||||
i386-dis.c \
|
||||
i386-opc.c \
|
||||
i860-dis.c \
|
||||
i960-dis.c \
|
||||
ia64-dis.c \
|
||||
|
@ -452,6 +453,7 @@ ALL_MACHINES = \
|
|||
h8500-dis.lo \
|
||||
hppa-dis.lo \
|
||||
i386-dis.lo \
|
||||
i386-opc.lo \
|
||||
i370-dis.lo \
|
||||
i370-opc.lo \
|
||||
i860-dis.lo \
|
||||
|
@ -1314,7 +1316,9 @@ i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
|
|||
$(INCDIR)/opcode/i370.h
|
||||
i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
|
||||
$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
|
||||
$(INCDIR)/ansidecl.h opintl.h
|
||||
$(INCDIR)/ansidecl.h opintl.h $(INCDIR)/opcode/i386.h
|
||||
i386-opc.lo: i386-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
|
||||
i386-opc.h $(INCDIR)/opcode/i386.h
|
||||
i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
|
||||
$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/i860.h
|
||||
i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
|
||||
|
|
|
@ -6541,7 +6541,7 @@ if test x${all_targets} = xfalse ; then
|
|||
bfd_h8500_arch) ta="$ta h8500-dis.lo" ;;
|
||||
bfd_hppa_arch) ta="$ta hppa-dis.lo" ;;
|
||||
bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;;
|
||||
bfd_i386_arch) ta="$ta i386-dis.lo" ;;
|
||||
bfd_i386_arch) ta="$ta i386-dis.lo i386-opc.lo" ;;
|
||||
bfd_i860_arch) ta="$ta i860-dis.lo" ;;
|
||||
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
|
||||
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
|
||||
|
|
|
@ -170,7 +170,7 @@ if test x${all_targets} = xfalse ; then
|
|||
bfd_h8500_arch) ta="$ta h8500-dis.lo" ;;
|
||||
bfd_hppa_arch) ta="$ta hppa-dis.lo" ;;
|
||||
bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;;
|
||||
bfd_i386_arch) ta="$ta i386-dis.lo" ;;
|
||||
bfd_i386_arch) ta="$ta i386-dis.lo i386-opc.lo" ;;
|
||||
bfd_i860_arch) ta="$ta i860-dis.lo" ;;
|
||||
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
|
||||
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
|
||||
|
|
|
@ -34,17 +34,10 @@
|
|||
#include "dis-asm.h"
|
||||
#include "sysdep.h"
|
||||
#include "opintl.h"
|
||||
|
||||
#define MAXLEN 15
|
||||
#include "opcode/i386.h"
|
||||
|
||||
#include <setjmp.h>
|
||||
|
||||
#ifndef UNIXWARE_COMPAT
|
||||
/* Set non-zero for broken, compatible instructions. Set to zero for
|
||||
non-broken opcodes. */
|
||||
#define UNIXWARE_COMPAT 1
|
||||
#endif
|
||||
|
||||
static int fetch_data (struct disassemble_info *, bfd_byte *);
|
||||
static void ckprefix (void);
|
||||
static const char *prefix_name (int, int);
|
||||
|
@ -109,16 +102,12 @@ static void CMPXCHG8B_Fixup (int, int);
|
|||
struct dis_private {
|
||||
/* Points to first byte not fetched. */
|
||||
bfd_byte *max_fetched;
|
||||
bfd_byte the_buffer[MAXLEN];
|
||||
bfd_byte the_buffer[MAX_MNEM_SIZE];
|
||||
bfd_vma insn_start;
|
||||
int orig_sizeflag;
|
||||
jmp_buf bailout;
|
||||
};
|
||||
|
||||
/* The opcode for the fwait instruction, which we treat as a prefix
|
||||
when we can. */
|
||||
#define FWAIT_OPCODE (0x9b)
|
||||
|
||||
enum address_mode
|
||||
{
|
||||
mode_16bit,
|
||||
|
@ -183,7 +172,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
struct dis_private *priv = (struct dis_private *) info->private_data;
|
||||
bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
|
||||
|
||||
if (addr <= priv->the_buffer + MAXLEN)
|
||||
if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
|
||||
status = (*info->read_memory_func) (start,
|
||||
priv->max_fetched,
|
||||
addr - priv->max_fetched,
|
||||
|
@ -490,8 +479,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
|
||||
typedef void (*op_rtn) (int bytemode, int sizeflag);
|
||||
|
||||
#define MAX_OPERANDS 4
|
||||
|
||||
struct dis386 {
|
||||
const char *name;
|
||||
struct
|
||||
|
@ -3515,7 +3502,7 @@ static const struct dis386 float_reg[][8] = {
|
|||
{ "fmul", { STi, ST } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
#if UNIXWARE_COMPAT
|
||||
#if SYSV386_COMPAT
|
||||
{ "fsub", { STi, ST } },
|
||||
{ "fsubr", { STi, ST } },
|
||||
{ "fdiv", { STi, ST } },
|
||||
|
@ -3544,7 +3531,7 @@ static const struct dis386 float_reg[][8] = {
|
|||
{ "fmulp", { STi, ST } },
|
||||
{ "(bad)", { XX } },
|
||||
{ FGRPde_3 },
|
||||
#if UNIXWARE_COMPAT
|
||||
#if SYSV386_COMPAT
|
||||
{ "fsubp", { STi, ST } },
|
||||
{ "fsubrp", { STi, ST } },
|
||||
{ "fdivp", { STi, ST } },
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,231 @@
|
|||
/* Declarations for Intel 80386 opcode table
|
||||
Copyright 2007
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
||||
GAS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
GAS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GAS; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#include "opcode/i386.h"
|
||||
|
||||
typedef struct template
|
||||
{
|
||||
/* instruction name sans width suffix ("mov" for movl insns) */
|
||||
char *name;
|
||||
|
||||
/* how many operands */
|
||||
unsigned int operands;
|
||||
|
||||
/* base_opcode is the fundamental opcode byte without optional
|
||||
prefix(es). */
|
||||
unsigned int base_opcode;
|
||||
#define Opcode_D 0x2 /* Direction bit:
|
||||
set if Reg --> Regmem;
|
||||
unset if Regmem --> Reg. */
|
||||
#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
|
||||
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
|
||||
|
||||
/* extension_opcode is the 3 bit extension for group <n> insns.
|
||||
This field is also used to store the 8-bit opcode suffix for the
|
||||
AMD 3DNow! instructions.
|
||||
If this template has no extension opcode (the usual case) use None */
|
||||
unsigned int extension_opcode;
|
||||
#define None 0xffff /* If no extension_opcode is possible. */
|
||||
|
||||
/* cpu feature flags */
|
||||
unsigned int cpu_flags;
|
||||
#define Cpu186 0x1 /* i186 or better required */
|
||||
#define Cpu286 0x2 /* i286 or better required */
|
||||
#define Cpu386 0x4 /* i386 or better required */
|
||||
#define Cpu486 0x8 /* i486 or better required */
|
||||
#define Cpu586 0x10 /* i585 or better required */
|
||||
#define Cpu686 0x20 /* i686 or better required */
|
||||
#define CpuP4 0x40 /* Pentium4 or better required */
|
||||
#define CpuK6 0x80 /* AMD K6 or better required*/
|
||||
#define CpuSledgehammer 0x100 /* Sledgehammer or better required */
|
||||
#define CpuMMX 0x200 /* MMX support required */
|
||||
#define CpuMMX2 0x400 /* extended MMX support (with SSE or 3DNow!Ext) required */
|
||||
#define CpuSSE 0x800 /* Streaming SIMD extensions required */
|
||||
#define CpuSSE2 0x1000 /* Streaming SIMD extensions 2 required */
|
||||
#define Cpu3dnow 0x2000 /* 3dnow! support required */
|
||||
#define Cpu3dnowA 0x4000 /* 3dnow!Extensions support required */
|
||||
#define CpuSSE3 0x8000 /* Streaming SIMD extensions 3 required */
|
||||
#define CpuPadLock 0x10000 /* VIA PadLock required */
|
||||
#define CpuSVME 0x20000 /* AMD Secure Virtual Machine Ext-s required */
|
||||
#define CpuVMX 0x40000 /* VMX Instructions required */
|
||||
#define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */
|
||||
#define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */
|
||||
#define CpuABM 0x200000 /* ABM New Instructions required */
|
||||
|
||||
/* These flags are set by gas depending on the flag_code. */
|
||||
#define Cpu64 0x4000000 /* 64bit support required */
|
||||
#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
|
||||
|
||||
/* The default value for unknown CPUs - enable all features to avoid problems. */
|
||||
#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
|
||||
|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
|
||||
|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a)
|
||||
|
||||
/* the bits in opcode_modifier are used to generate the final opcode from
|
||||
the base_opcode. These bits also are used to detect alternate forms of
|
||||
the same instruction */
|
||||
unsigned int opcode_modifier;
|
||||
|
||||
/* opcode_modifier bits: */
|
||||
#define D 0x1 /* has direction bit. */
|
||||
#define W 0x2 /* set if operands can be words or dwords
|
||||
encoded the canonical way */
|
||||
#define Modrm 0x4 /* insn has a modrm byte. */
|
||||
#define ShortForm 0x10 /* register is in low 3 bits of opcode */
|
||||
#define Jump 0x40 /* special case for jump insns. */
|
||||
#define JumpDword 0x80 /* call and jump */
|
||||
#define JumpByte 0x100 /* loop and jecxz */
|
||||
#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
|
||||
#define FloatMF 0x400 /* FP insn memory format bit, sized by 0x4 */
|
||||
#define FloatR 0x800 /* src/dest swap for floats. */
|
||||
#define FloatD 0x1000 /* has float insn direction bit. */
|
||||
#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
|
||||
#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
|
||||
#define Size64 0x8000 /* needs size prefix if in 64-bit mode */
|
||||
#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
|
||||
#define DefaultSize 0x20000 /* default insn size depends on mode */
|
||||
#define No_bSuf 0x40000 /* b suffix on instruction illegal */
|
||||
#define No_wSuf 0x80000 /* w suffix on instruction illegal */
|
||||
#define No_lSuf 0x100000 /* l suffix on instruction illegal */
|
||||
#define No_sSuf 0x200000 /* s suffix on instruction illegal */
|
||||
#define No_qSuf 0x400000 /* q suffix on instruction illegal */
|
||||
#define No_xSuf 0x800000 /* x suffix on instruction illegal */
|
||||
#define FWait 0x1000000 /* instruction needs FWAIT */
|
||||
#define IsString 0x2000000 /* quick test for string instructions */
|
||||
#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
|
||||
#define IsPrefix 0x8000000 /* opcode is a prefix */
|
||||
#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
|
||||
#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
|
||||
#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
|
||||
#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
|
||||
|
||||
/* operand_types[i] describes the type of operand i. This is made
|
||||
by OR'ing together all of the possible type masks. (e.g.
|
||||
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
||||
either a register or an immediate operand. */
|
||||
unsigned int operand_types[MAX_OPERANDS];
|
||||
|
||||
/* operand_types[i] bits */
|
||||
/* register */
|
||||
#define Reg8 0x1 /* 8 bit reg */
|
||||
#define Reg16 0x2 /* 16 bit reg */
|
||||
#define Reg32 0x4 /* 32 bit reg */
|
||||
#define Reg64 0x8 /* 64 bit reg */
|
||||
/* immediate */
|
||||
#define Imm8 0x10 /* 8 bit immediate */
|
||||
#define Imm8S 0x20 /* 8 bit immediate sign extended */
|
||||
#define Imm16 0x40 /* 16 bit immediate */
|
||||
#define Imm32 0x80 /* 32 bit immediate */
|
||||
#define Imm32S 0x100 /* 32 bit immediate sign extended */
|
||||
#define Imm64 0x200 /* 64 bit immediate */
|
||||
#define Imm1 0x400 /* 1 bit immediate */
|
||||
/* memory */
|
||||
#define BaseIndex 0x800
|
||||
/* Disp8,16,32 are used in different ways, depending on the
|
||||
instruction. For jumps, they specify the size of the PC relative
|
||||
displacement, for baseindex type instructions, they specify the
|
||||
size of the offset relative to the base register, and for memory
|
||||
offset instructions such as `mov 1234,%al' they specify the size of
|
||||
the offset relative to the segment base. */
|
||||
#define Disp8 0x1000 /* 8 bit displacement */
|
||||
#define Disp16 0x2000 /* 16 bit displacement */
|
||||
#define Disp32 0x4000 /* 32 bit displacement */
|
||||
#define Disp32S 0x8000 /* 32 bit signed displacement */
|
||||
#define Disp64 0x10000 /* 64 bit displacement */
|
||||
/* specials */
|
||||
#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
|
||||
#define ShiftCount 0x40000 /* register to hold shift count = cl */
|
||||
#define Control 0x80000 /* Control register */
|
||||
#define Debug 0x100000 /* Debug register */
|
||||
#define Test 0x200000 /* Test register */
|
||||
#define FloatReg 0x400000 /* Float register */
|
||||
#define FloatAcc 0x800000 /* Float stack top %st(0) */
|
||||
#define SReg2 0x1000000 /* 2 bit segment register */
|
||||
#define SReg3 0x2000000 /* 3 bit segment register */
|
||||
#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
|
||||
#define JumpAbsolute 0x8000000
|
||||
#define RegMMX 0x10000000 /* MMX register */
|
||||
#define RegXMM 0x20000000 /* XMM registers in PIII */
|
||||
#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
|
||||
|
||||
/* InvMem is for instructions with a modrm byte that only allow a
|
||||
general register encoding in the i.tm.mode and i.tm.regmem fields,
|
||||
eg. control reg moves. They really ought to support a memory form,
|
||||
but don't, so we add an InvMem flag to the register operand to
|
||||
indicate that it should be encoded in the i.tm.regmem field. */
|
||||
#define InvMem 0x80000000
|
||||
|
||||
#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
|
||||
#define WordReg (Reg16|Reg32|Reg64)
|
||||
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
|
||||
#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
|
||||
#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
|
||||
#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
|
||||
#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
|
||||
/* The following aliases are defined because the opcode table
|
||||
carefully specifies the allowed memory types for each instruction.
|
||||
At the moment we can only tell a memory reference size by the
|
||||
instruction suffix, so there's not much point in defining Mem8,
|
||||
Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
|
||||
the suffix directly to check memory operands. */
|
||||
#define LLongMem AnyMem /* 64 bits (or more) */
|
||||
#define LongMem AnyMem /* 32 bit memory ref */
|
||||
#define ShortMem AnyMem /* 16 bit memory ref */
|
||||
#define WordMem AnyMem /* 16, 32 or 64 bit memory ref */
|
||||
#define ByteMem AnyMem /* 8 bit memory ref */
|
||||
}
|
||||
template;
|
||||
|
||||
extern const template i386_optab[];
|
||||
|
||||
/* these are for register name --> number & type hash lookup */
|
||||
typedef struct
|
||||
{
|
||||
char *reg_name;
|
||||
unsigned int reg_type;
|
||||
unsigned int reg_flags;
|
||||
#define RegRex 0x1 /* Extended register. */
|
||||
#define RegRex64 0x2 /* Extended 8 bit register. */
|
||||
unsigned int reg_num;
|
||||
}
|
||||
reg_entry;
|
||||
|
||||
/* Entries in i386_regtab. */
|
||||
#define REGNAM_AL 1
|
||||
#define REGNAM_AX 25
|
||||
#define REGNAM_EAX 41
|
||||
|
||||
extern const reg_entry i386_regtab[];
|
||||
extern const reg_entry i386_float_regtab[];
|
||||
|
||||
typedef struct
|
||||
{
|
||||
char *seg_name;
|
||||
unsigned int seg_prefix;
|
||||
}
|
||||
seg_entry;
|
||||
|
||||
extern const seg_entry cs;
|
||||
extern const seg_entry ds;
|
||||
extern const seg_entry ss;
|
||||
extern const seg_entry es;
|
||||
extern const seg_entry fs;
|
||||
extern const seg_entry gs;
|
Loading…
Reference in New Issue