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More reversion of incomplete m32r changes. Should be back to normal.

This commit is contained in:
Andrew Cagney 2003-12-07 16:13:06 +00:00
parent cd886a95bf
commit 0b2e03b491
5 changed files with 27 additions and 188 deletions
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54
sim/m32r/m32r-sim.h
View File

@ -41,29 +41,27 @@ extern int m32r_decode_gdb_ctrl_regnum (int);
FIXME: Eventually move to cgen. */
#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
extern SI a_m32r_h_gr_get (SIM_CPU *, UINT);
extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
extern USI a_m32r_h_cr_get (SIM_CPU *, UINT);
extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
#define GET_H_CR(regno) \
XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
#define SET_H_CR(regno, val) \
XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
#define GET_H_PSW() \
XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
#define SET_H_PSW(val) \
XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
#define GET_H_ACCUM() \
XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
#define SET_H_ACCUM(val) \
XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT);
extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI);
extern UQI m32rxf_h_psw_get_handler (SIM_CPU *);
extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI);
extern DI m32rxf_h_accum_get_handler (SIM_CPU *);
extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI);
extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT);
extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI);
/* Misc. profile data. */
@ -130,32 +128,6 @@ do { \
/* Additional execution support. */
/* Result of semantic function is one of
- next address, branch only
- NEW_PC_SKIP, sc/snc insn
- NEW_PC_2, 2 byte non-branch non-sc/snc insn
- NEW_PC_4, 4 byte non-branch insn
The special values have bit 1 set so it's cheap to distinguish them.
This works because all cti's are defined to zero the bottom two bits
Note that the m32rx no longer doesn't implement its semantics with
functions, so this isn't used. It's kept around should it be needed
again. */
/* FIXME: replace 0xffff0001 with 1? */
#define NEW_PC_BASE 0xffff0001
#define NEW_PC_SKIP NEW_PC_BASE
#define NEW_PC_2 (NEW_PC_BASE + 2)
#define NEW_PC_4 (NEW_PC_BASE + 4)
#define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0)
/* Modify "next pc" support to handle parallel execution.
This is for the non-pbb case. The m32rx no longer implements this.
It's kept around should it be needed again. */
#if defined (WANT_CPU_M32RXF) && ! WITH_SCACHE_PBB_M32RXF
#undef SEM_NEXT_VPC
#define SEM_NEXT_VPC(abuf, len) (NEW_PC_BASE + (len))
#undef SEM_SKIP_INSN
#define SEM_SKIP_INSN(cpu, sc, vpcvar, yes) FIXME
#endif
/* Hardware/device support.
??? Will eventually want to move device stuff to config files. */
@ -217,7 +189,7 @@ do { \
/* Start address and length of all device support. */
#define M32R_DEVICE_ADDR 0xff000000
#define M32R_DEVICE_LEN 0x01000000
#define M32R_DEVICE_LEN 0x00ffffff
/* sim_core_attach device argument. */
extern device m32r_devices;

124
sim/m32r/m32r.c
View File

@ -48,8 +48,6 @@ m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
int
m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
int mach = MACH_NUM (CPU_MACH (current_cpu));
if (rn < 16)
SETTWI (buf, a_m32r_h_gr_get (current_cpu, rn));
else
@ -66,22 +64,13 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
m32r_decode_gdb_ctrl_regnum (rn)));
break;
case PC_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, m32rbf_h_pc_get (current_cpu));
else
SETTWI (buf, m32rxf_h_pc_get (current_cpu));
SETTWI (buf, a_m32r_h_pc_get (current_cpu));
break;
case ACCL_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
else
SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
SETTWI (buf, GETLODI (a_m32r_h_accum_get (current_cpu)));
break;
case ACCH_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
else
SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
SETTWI (buf, GETHIDI (a_m32r_h_accum_get (current_cpu)));
break;
default :
return 0;
@ -95,8 +84,6 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
int
m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
int mach = MACH_NUM (CPU_MACH (current_cpu));
if (rn < 16)
a_m32r_h_gr_set (current_cpu, rn, GETTWI (buf));
else
@ -114,37 +101,20 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
GETTWI (buf));
break;
case PC_REGNUM :
if (mach == MACH_M32R)
m32rbf_h_pc_set (current_cpu, GETTWI (buf));
else
m32rxf_h_pc_set (current_cpu, GETTWI (buf));
a_m32r_h_pc_set (current_cpu, GETTWI (buf));
break;
case ACCL_REGNUM :
{
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
else
val = m32rxf_h_accum_get (current_cpu);
DI val = a_m32r_h_accum_get (current_cpu);
SETLODI (val, GETTWI (buf));
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
else
m32rxf_h_accum_set (current_cpu, val);
a_m32r_h_accum_set (current_cpu, val);
break;
}
case ACCH_REGNUM :
{
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
else
val = m32rxf_h_accum_get (current_cpu);
DI val = a_m32r_h_accum_get (current_cpu);
SETHIDI (val, GETTWI (buf));
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
else
m32rxf_h_accum_set (current_cpu, val);
a_m32r_h_accum_set (current_cpu, val);
break;
}
default :
@ -154,84 +124,6 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
return -1; /*FIXME*/
}
/* Cover fns for mach independent register accesses. */
SI
a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
return m32rbf_h_gr_get (current_cpu, regno);
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
return m32rxf_h_gr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
void
a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
m32rbf_h_gr_set (current_cpu, regno, newval);
break;
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
m32rxf_h_gr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
USI
a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
return m32rbf_h_cr_get (current_cpu, regno);
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
return m32rxf_h_cr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
void
a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
m32rbf_h_cr_set (current_cpu, regno, newval);
break;
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
m32rxf_h_cr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
USI
m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
{

10
sim/m32r/sim-if.c
View File

@ -240,16 +240,6 @@ print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
PROFILE_LABEL_WIDTH, "Parallel insns:",
sim_add_commas (buf, sizeof (buf),
CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
sim_io_printf (sd, " %-*s %s\n\n",
PROFILE_LABEL_WIDTH, "Parallel insns:",
sim_add_commas (buf, sizeof (buf),
CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
sim_io_printf (sd, " %-*s %s\n\n",
PROFILE_LABEL_WIDTH, "Parallel insns:",
sim_add_commas (buf, sizeof (buf),
CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
}
}

3
sim/m32r/sim-main.h
View File

@ -1,4 +1,3 @@
/* Main header for the m32r. */
#ifndef SIM_MAIN_H
@ -58,8 +57,6 @@ struct _sim_cpu {
go after here. Oh for a better language. */
#if defined (WANT_CPU_M32RBF)
M32RBF_CPU_DATA cpu_data;
#elif defined (WANT_CPU_M32RXF)
M32RXF_CPU_DATA cpu_data;
#endif
};

24
sim/m32r/traps.c
View File

@ -21,12 +21,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "sim-main.h"
#include "targ-vals.h"
/* The semantic code invokes this for invalid (unrecognized) instructions.
CIA is the address with the invalid insn.
VPC is the virtual pc of the following insn. */
/* The semantic code invokes this for invalid (unrecognized) instructions. */
SEM_PC
sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
void
sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia)
{
SIM_DESC sd = CPU_STATE (current_cpu);
@ -48,7 +46,6 @@ sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
else
#endif
sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
return vpc;
}
/* Process an address exception. */
@ -62,18 +59,9 @@ m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
{
a_m32r_h_cr_set (current_cpu, H_CR_BBPC,
a_m32r_h_cr_get (current_cpu, H_CR_BPC));
if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R)
{
m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
/* sm not changed */
m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
}
else
{
m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
/* sm not changed */
m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
}
a_m32r_h_bpsw_set (current_cpu, a_m32r_h_psw_get (current_cpu));
/* sm not changed */
a_m32r_h_psw_set (current_cpu, a_m32r_h_psw_get (current_cpu) & 0x80);
a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,