snapshot
This commit is contained in:
Doug Evans
parent
ef13d3e3ed
commit
0b988d39cf
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@ -60,14 +60,31 @@ PRINT_FN (vfreg);
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PARSE_FN (bc);
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PRINT_FN (bc);
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PARSE_FN (ftregbc);
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PRINT_FN (ftregbc);
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PARSE_FN (bcftreg);
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PRINT_FN (bcftreg);
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PARSE_FN (accdest);
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PRINT_FN (accdest);
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PARSE_FN (xyz);
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PARSE_FN (ireg);
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PRINT_FN (ireg);
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PARSE_FN (freg);
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PRINT_FN (freg);
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PARSE_FN (ffstreg);
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INSERT_FN (ffstreg);
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EXTRACT_FN (ffstreg);
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PRINT_FN (ffstreg);
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PARSE_FN (vi01);
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PRINT_FN (vi01);
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INSERT_FN (limm12);
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EXTRACT_FN (limm12);
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/* Various types of TXVU operands, including insn suffixes.
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Fields are:
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@ -83,40 +100,80 @@ const struct txvu_operand txvu_operands[] =
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#define UNUSED 128
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{ 0 },
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/* Upper word operands. */
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/* Destination indicator, with leading '.'. */
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#define DOTDEST (UNUSED + 1)
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#define UDOTDEST (UNUSED + 1)
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{ 4, TXVU_SHIFT_DEST, TXVU_OPERAND_SUFFIX,
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parse_dotdest, insert_dotdest, extract_dotdest, print_dotdest },
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/* ft reg */
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#define FTREG (DOTDEST + 1)
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#define UVFTREG (UDOTDEST + 1)
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{ 5, TXVU_SHIFT_FTREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* fs reg */
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#define FSREG (FTREG + 1)
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#define UVFSREG (UVFTREG + 1)
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{ 5, TXVU_SHIFT_FSREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* fd reg */
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#define FDREG (FSREG + 1)
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#define UVFDREG (UVFSREG + 1)
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{ 5, TXVU_SHIFT_FDREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* broadcast */
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#define BC (FDREG + 1)
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#define UBC (UVFDREG + 1)
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{ 2, 0, 0, parse_bc, 0, 0, print_bc },
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/* ftreg in broadcast case */
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#define FTREGBC (BC + 1)
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{ 5, TXVU_SHIFT_FTREG, 0, parse_ftregbc, 0, 0, print_ftregbc },
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#define UBCFTREG (UBC + 1)
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{ 5, TXVU_SHIFT_FTREG, 0, parse_bcftreg, 0, 0, print_bcftreg },
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/* accumulator dest */
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#define ACCDEST (FTREGBC + 1)
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#define UACCDEST (UBCFTREG + 1)
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{ 0, 0, TXVU_OPERAND_FAKE, parse_accdest, 0, 0, print_accdest },
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/* The XYZ operand is a fake one that is used to ensure only "xyz" is
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specified. It simplifies the opmula and opmsub entries. */
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#define XYZ (FDREG + 1)
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#define UXYZ (UACCDEST + 1)
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{ 0, 0, TXVU_OPERAND_FAKE, parse_xyz, 0, 0, 0 },
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/* Lower word operands. */
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/* 11 bit immediate. */
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#define LIMM11 (UXYZ + 1)
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{ 11, 0, 0, 0, 0, 0, 0 },
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/* IS register. */
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#define LISREG (LIMM11 + 1)
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{ 5, 11, 0, parse_ireg, 0, 0, print_ireg },
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/* IT register. */
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#define LITREG (LISREG + 1)
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{ 5, 16, 0, parse_ireg, 0, 0, print_ireg },
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/* FS reg, with FSF field selector. */
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#define LFSFFSREG (LITREG + 1)
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{ 5, 11, 0, parse_ffstreg, insert_ffstreg, extract_ffstreg, print_ffstreg },
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/* FS reg, no selector (choice of x,y,z,w is provided by opcode). */
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#define LFSREG (LFSFFSREG + 1)
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{ 5, 11, 0, parse_freg, 0, 0, print_freg },
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/* FT reg, with FTF field selector. */
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#define LFTFFTREG (LFSREG + 1)
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{ 5, 16, 0, parse_ffstreg, insert_ffstreg, extract_ffstreg, print_ffstreg },
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/* VI01 register. */
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#define LVI01 (LFTFFTREG + 1)
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{ 0, 0, TXVU_OPERAND_FAKE, parse_vi01, 0, 0, print_vi01 },
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/* 24 bit immediate. */
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#define LIMM24 (LVI01 + 1)
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{ 24, 0, 0, 0, 0, 0, 0 },
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/* 12 bit immediate, split into 1 and 11 bit pieces. */
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#define LIMM12 (LIMM24 + 1)
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{ 12, 0, 0, 0, insert_limm12, extract_limm12, 0 },
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/* end of list place holder */
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{ 0 }
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};
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@ -124,46 +181,77 @@ const struct txvu_operand txvu_operands[] =
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/* Macros to put a field's value into the right place. */
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/* FIXME: If assembler needs these, move to opcode/txvu.h. */
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#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
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/* value X, B bits, shift S */
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#define R(x,b,s) (((x) & ((1 << (b)) - 1)) << (s))
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/* Upper instruction Value macros. */
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/* Upper Flag bits. */
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#define UF(x) R ((x), 27, 31)
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#define VUF(x) R ((x), 5, 27)
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/* Upper REServed two bits next to flag bits. */
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#define URES(x) R ((x), 25, 3)
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/* The DEST field. */
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#define UDEST(x) R ((x), 21, 15)
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/* The FT reg field. */
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#define UFT(x) R ((x), TXVU_SHIFT_FTREG, TXVU_MASK_VFREG)
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/* The FS reg field. */
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#define UFS(x) R ((x), TXVU_SHIFT_FSREG, TXVU_MASK_VFREG)
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/* The FD reg field. */
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#define UFD(x) R ((x), TXVU_SHIFT_FDREG, TXVU_MASK_VFREG)
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/* The 4 bit opcode field. */
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#define UOP4(x) R ((x), 2, 15)
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/* The 6 bit opcode field. */
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#define UOP6(x) R ((x), 0, 63)
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/* The 9 bit opcode field. */
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#define UOP9(x) R ((x), 2, 0x1ff)
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/* The 11 bit opcode field. */
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#define UOP11(x) R ((x), 0, 0x7ff)
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/* The BroadCast field. */
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#define UBC(x) R ((x), 0, 3)
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#define VURES(x) R ((x), 2, 25)
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/* DEST field. */
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#define VUDEST(x) R ((x), 4, 21)
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/* FT reg field. */
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#define VUFT(x) R ((x), 5, TXVU_SHIFT_FTREG)
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/* FS reg field. */
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#define VUFS(x) R ((x), 5, TXVU_SHIFT_FSREG)
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/* FD reg field. */
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#define VUFD(x) R ((x), 5, TXVU_SHIFT_FDREG)
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/* 4 bit opcode field. */
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#define VUOP4(x) R ((x), 4, 2)
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/* 6 bit opcode field. */
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#define VUOP6(x) R ((x), 6, 0)
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/* 9 bit opcode field. */
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#define VUOP9(x) R ((x), 9, 2)
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/* 11 bit opcode field. */
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#define VUOP11(x) R ((x), 11, 0)
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/* BroadCast field. */
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#define VUBC(x) R ((x), 2, 0)
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/* Macros for special field values. */
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/* The upper 7 bits of the upper word. */
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#define UUBITS (UF (0) + URES (0))
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/* Mask for UBITS. */
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#define MUUBITS (UF (~0) + URES (~0))
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/* Mask for URES. */
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#define MURES URES (~0)
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/* Mask for OP4. */
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#define MUOP4 UOP4 (~0)
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/* Mask for OP6. */
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#define MUOP6 UOP6 (~0)
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/* Mask for OP9. */
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#define MUOP9 UOP9 (~0)
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/* Mask for OP11. */
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#define MUOP11 UOP11 (~0)
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/* Field masks. */
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#define MUUBITS (VUF (~0) + VURES (~0))
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#define MURES VURES (~0)
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#define MUOP4 VUOP4 (~0)
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#define MUOP6 VUOP6 (~0)
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#define MUOP9 VUOP9 (~0)
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#define MUOP11 VUOP11 (~0)
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/* Lower instruction Value macros. */
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/* 7 bit opcode. */
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#define VLOP7(x) R ((x), 7, 25)
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/* 11 bit opcode. */
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#define VLOP11(x) R ((x), 11, 0)
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/* dest field. */
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#define VLDEST(x) R ((x), 4, 21)
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/* IT reg. */
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#define VLIT(x) R ((x), 5, 16)
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/* IS reg. */
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#define VLIS(x) R ((x), 5, 11)
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/* 11 bit immediate. */
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#define VLIMM11(x) R ((x), 11, 0)
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/* FTF field. */
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#define VLFTF(x) R ((x), 2, 23)
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/* FSF field. */
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#define VLFSF(x) R ((x), 2, 21)
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/* FT reg. */
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#define VLFT(x) R ((x), 5, 16)
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/* FS reg. */
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#define VLFS(x) R ((x), 5, 11)
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/* Field masks. */
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#define MLOP7 VLOP7 (~0)
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#define MLOP11 VLOP11 (~0)
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#define MLDEST VLDEST (~0)
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#define MLIT VLIT (~0)
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#define MLIS VLIS (~0)
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#define MLIMM11 VLIMM11 (~0)
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#define MLB24 R (1, 1, 24)
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/* 12 bit immediates are split into two parts, 1 bit and 11 bits.
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The upper 1 bit is part of the `dest' field. This mask is for the
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other 3 bits of the dest field. */
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#define MLIMM12TOP R (7, 3, 22)
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/* A space, separates instruction name (mnemonic + mnemonic operands) from operands. */
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#define SP ' '
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@ -196,68 +284,69 @@ struct txvu_opcode txvu_upper_opcodes[] = {
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/* Macros appear first. */
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/* ??? Any aliases? */
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/* FIXME: When close to being finished, clean up by aligning fields. */
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/* The rest of these needn't be sorted, but it helps to find them if they are. */
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{ "abs", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x1fd) },
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{ "add", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x28) },
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{ "addi", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x22) },
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{ "addq", { DOTDEST, SP, FDREG, FSREG, 'q' }, MURES + UFT (~0) + MUOP6, UOP6 (0x20) },
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{ "add", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + UOP4 (~0), UOP4 (0) },
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{ "adda", { DOTDEST, SP, ACCDEST, FSREG, FTREG }, MURES + MUOP11, UOP11 (0x2bc) },
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{ "addai", { DOTDEST, SP, ACCDEST, FSREG, 'i' }, MURES + UFT (~0) + MUOP11, UOP11 (0x23e) },
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{ "addaq", { DOTDEST, SP, ACCDEST, FSREG, 'q' }, MURES + UFT (~0) + MUOP11, UOP11 (0x23c) },
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{ "adda", { BC, DOTDEST, SP, ACCDEST, FSREG, FTREGBC }, MURES + MUOP9, UOP9 (0xf) },
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{ "clip", { DOTDEST, SP, FSREG }, MURES + UDEST (~0) + UFT (~0) + MUOP11, UDEST (0xf) + UOP11 (0x1ff) },
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{ "ftoi0", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x17c) },
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{ "ftoi4", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x17d) },
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{ "ftoi12", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x17e) },
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{ "ftoi15", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x17f) },
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{ "itof0", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x13c) },
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{ "itof4", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x13d) },
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{ "itof12", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x13e) },
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{ "itof15", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x13f) },
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{ "madd", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x29) },
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{ "maddi", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x23) },
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{ "maddq", { DOTDEST, SP, FDREG, FSREG, 'q' }, MURES + UFT (~0) + MUOP6, UOP6 (0x21) },
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{ "madd", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + MUOP4, UOP4 (0x2) },
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{ "madda", { DOTDEST, SP, ACCDEST, FSREG, FTREG }, MURES + MUOP11, UOP11 (0x2bd) },
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{ "maddai", { DOTDEST, SP, ACCDEST, FSREG, 'i' }, MURES + UFT (~0) + MUOP11, UOP11 (0x23f) },
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{ "maddaq", { DOTDEST, SP, ACCDEST, FSREG, 'q' }, MURES + UFT (~0) + MUOP11, UOP11 (0x23d) },
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{ "madda", { BC, DOTDEST, SP, ACCDEST, FSREG, FTREGBC }, MURES + MUOP9, UOP9 (0x2f) },
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{ "max", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x2b) },
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{ "maxi", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x2d) },
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{ "max", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + MUOP4, UOP4 (0x4) },
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{ "abs", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x1fd) },
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{ "add", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x28) },
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{ "addi", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x22) },
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{ "addq", { UDOTDEST, SP, UVFDREG, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x20) },
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{ "add", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + VUOP4 (~0), VUOP4 (0) },
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{ "adda", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG }, MURES + MUOP11, VUOP11 (0x2bc) },
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{ "addai", { UDOTDEST, SP, UACCDEST, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x23e) },
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{ "addaq", { UDOTDEST, SP, UACCDEST, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x23c) },
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{ "adda", { UBC, UDOTDEST, SP, UACCDEST, UVFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0xf) },
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{ "clip", { UDOTDEST, SP, UVFSREG }, MURES + VUDEST (~0) + VUFT (~0) + MUOP11, VUDEST (0xf) + VUOP11 (0x1ff) },
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{ "ftoi0", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x17c) },
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{ "ftoi4", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x17d) },
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{ "ftoi12", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x17e) },
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{ "ftoi15", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x17f) },
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{ "itof0", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x13c) },
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{ "itof4", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x13d) },
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{ "itof12", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x13e) },
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{ "itof15", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x13f) },
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{ "madd", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x29) },
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{ "maddi", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x23) },
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{ "maddq", { UDOTDEST, SP, UVFDREG, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x21) },
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{ "madd", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x2) },
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{ "madda", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG }, MURES + MUOP11, VUOP11 (0x2bd) },
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{ "maddai", { UDOTDEST, SP, UACCDEST, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x23f) },
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{ "maddaq", { UDOTDEST, SP, UACCDEST, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x23d) },
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{ "madda", { UBC, UDOTDEST, SP, UACCDEST, UVFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x2f) },
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{ "max", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x2b) },
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{ "maxi", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x2d) },
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{ "max", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x4) },
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/* FIXME: mini or min? */
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{ "mini", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x2f) },
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{ "mini", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x1f) },
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{ "mini", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + MUOP4, UOP4 (0x5) },
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{ "msub", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x2d) },
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{ "msubi", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x27) },
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{ "msubq", { DOTDEST, SP, FDREG, FSREG, 'q' }, MURES + UFT (~0) + MUOP6, UOP6 (0x25) },
|
||||
{ "msub", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + MUOP4, UOP4 (0x3) },
|
||||
{ "msuba", { DOTDEST, SP, ACCDEST, FSREG, FTREG }, MURES + MUOP11, UOP11 (0x2fd) },
|
||||
{ "msubai", { DOTDEST, SP, ACCDEST, FSREG, 'i' }, MURES + UFT (~0) + MUOP11, UOP11 (0x27f) },
|
||||
{ "msubaq", { DOTDEST, SP, ACCDEST, FSREG, 'q' }, MURES + UFT (~0) + MUOP11, UOP11 (0x27d) },
|
||||
{ "msuba", { BC, DOTDEST, SP, ACCDEST, FSREG, FTREGBC }, MURES + MUOP9, UOP9 (0x3f) },
|
||||
{ "mul", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x2a) },
|
||||
{ "muli", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x1e) },
|
||||
{ "mulq", { DOTDEST, SP, FDREG, FSREG, 'q' }, MURES + UFT (~0) + MUOP6, UOP6 (0x1c) },
|
||||
{ "mul", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + UOP4 (~0), UOP4 (6) },
|
||||
{ "mula", { DOTDEST, SP, ACCDEST, FSREG, FTREG }, MURES + MUOP11, UOP11 (0x2be) },
|
||||
{ "mulai", { DOTDEST, SP, ACCDEST, FSREG, 'i' }, MURES + UFT (~0) + MUOP11, UOP11 (0x1fe) },
|
||||
{ "mulaq", { DOTDEST, SP, ACCDEST, FSREG, 'q' }, MURES + UFT (~0) + MUOP11, UOP11 (0x1fc) },
|
||||
{ "mula", { BC, DOTDEST, SP, ACCDEST, FSREG, FTREGBC }, MURES + MUOP9, UOP9 (0x6f) },
|
||||
{ "nop", { 0 }, MURES + UDEST (~0) + UFT (~0) + UFS (~0) + MUOP11, UOP11 (0x2ff) },
|
||||
{ "opmula", { DOTDEST, SP, ACCDEST, FSREG, FTREG, XYZ }, MURES + MUOP11, UOP11 (0x2fe) },
|
||||
{ "opmsub", { DOTDEST, SP, FDREG, FSREG, FTREG, XYZ }, MURES + MUOP6, UOP6 (0x2e) },
|
||||
{ "sub", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x2c) },
|
||||
{ "subi", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x26) },
|
||||
{ "subq", { DOTDEST, SP, FDREG, FSREG, 'q' }, MURES + UFT (~0) + MUOP6, UOP6 (0x24) },
|
||||
{ "sub", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + UOP4 (~0), UOP4 (1) },
|
||||
{ "suba", { DOTDEST, SP, ACCDEST, FSREG, FTREG }, MURES + MUOP11, UOP11 (0x2fc) },
|
||||
{ "subai", { DOTDEST, SP, ACCDEST, FSREG, 'i' }, MURES + UFT (~0) + MUOP11, UOP11 (0x27e) },
|
||||
{ "subaq", { DOTDEST, SP, ACCDEST, FSREG, 'q' }, MURES + UFT (~0) + MUOP11, UOP11 (0x27c) },
|
||||
{ "suba", { BC, DOTDEST, SP, ACCDEST, FSREG, FTREGBC }, MURES + MUOP9, UOP9 (0x1f) }
|
||||
{ "mini", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x2f) },
|
||||
{ "mini", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x1f) },
|
||||
{ "mini", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x5) },
|
||||
{ "msub", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x2d) },
|
||||
{ "msubi", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x27) },
|
||||
{ "msubq", { UDOTDEST, SP, UVFDREG, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x25) },
|
||||
{ "msub", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x3) },
|
||||
{ "msuba", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG }, MURES + MUOP11, VUOP11 (0x2fd) },
|
||||
{ "msubai", { UDOTDEST, SP, UACCDEST, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x27f) },
|
||||
{ "msubaq", { UDOTDEST, SP, UACCDEST, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x27d) },
|
||||
{ "msuba", { UBC, UDOTDEST, SP, UACCDEST, UVFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x3f) },
|
||||
{ "mul", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x2a) },
|
||||
{ "muli", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x1e) },
|
||||
{ "mulq", { UDOTDEST, SP, UVFDREG, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x1c) },
|
||||
{ "mul", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + VUOP4 (~0), VUOP4 (6) },
|
||||
{ "mula", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG }, MURES + MUOP11, VUOP11 (0x2be) },
|
||||
{ "mulai", { UDOTDEST, SP, UACCDEST, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x1fe) },
|
||||
{ "mulaq", { UDOTDEST, SP, UACCDEST, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x1fc) },
|
||||
{ "mula", { UBC, UDOTDEST, SP, UACCDEST, UVFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x6f) },
|
||||
{ "nop", { 0 }, MURES + VUDEST (~0) + VUFT (~0) + VUFS (~0) + MUOP11, VUOP11 (0x2ff) },
|
||||
{ "opmula", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG, UXYZ }, MURES + MUOP11, VUOP11 (0x2fe) },
|
||||
{ "opmsub", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG, UXYZ }, MURES + MUOP6, VUOP6 (0x2e) },
|
||||
{ "sub", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x2c) },
|
||||
{ "subi", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x26) },
|
||||
{ "subq", { UDOTDEST, SP, UVFDREG, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x24) },
|
||||
{ "sub", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + VUOP4 (~0), VUOP4 (1) },
|
||||
{ "suba", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG }, MURES + MUOP11, VUOP11 (0x2fc) },
|
||||
{ "subai", { UDOTDEST, SP, UACCDEST, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x27e) },
|
||||
{ "subaq", { UDOTDEST, SP, UACCDEST, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x27c) },
|
||||
{ "suba", { UBC, UDOTDEST, SP, UACCDEST, UVFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x1f) }
|
||||
};
|
||||
const int txvu_upper_opcodes_count = sizeof (txvu_upper_opcodes) / sizeof (txvu_opcodes[0]);
|
||||
|
||||
|
|
@ -266,10 +355,37 @@ struct txvu_opcode txvu_lower_opcodes[] = {
|
|||
/* Macros appear first. */
|
||||
/* ??? Any aliases? */
|
||||
|
||||
/* The rest of these needn't be sorted, but it helps to find them if they
|
||||
are. */
|
||||
{ "waitp", { 0 }, 0xffffffff, 0x800007bf, 0 },
|
||||
{ "waitq", { 0 }, 0xffffffff, 0x800003bf, 0 },
|
||||
/* The rest of these needn't be sorted, but it helps to find them if they are. */
|
||||
{ "b", { SP, LIMM11 }, MLOP7 + MLDEST + MLIT + MLIS, VLOP7 (0x20) },
|
||||
{ "bal", { SP, LITREG, LIMM11 }, MLOP7 + MLDEST + MLIS, VLOP7 (0x21) },
|
||||
{ "div", { 'q', LFSFFSREG, LFTFFTREG }, MLOP7 + MLOP11, VLOP7 (0x40) + VLOP11 (0x3bc) },
|
||||
{ "eatan", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7fd) },
|
||||
{ "eatanxy", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x77c) },
|
||||
{ "eatanxz", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x77d) },
|
||||
{ "eexp", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7fe) },
|
||||
{ "eleng", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x74e) },
|
||||
{ "ercpr", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7be) },
|
||||
{ "erleng", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x73f) },
|
||||
{ "ersadd", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x73d) },
|
||||
{ "ersqrt", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7bd) },
|
||||
{ "esadd", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x73c) },
|
||||
{ "esin", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7fc) },
|
||||
{ "esqrt", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7bc) },
|
||||
{ "esum", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x77e) },
|
||||
{ "fcand", { LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x12) },
|
||||
{ "fceq", { LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x10) },
|
||||
{ "fcget", { LITREG }, MLOP7 + MLDEST + MLIS + MLIMM11, VLOP7 (0x1c) },
|
||||
{ "fcor", { LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x13) },
|
||||
{ "fcset", { LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x11) },
|
||||
{ "fmand", { LITREG, LISREG }, MLOP7 + MLDEST + MLIMM11, VLOP7 (0x1a) },
|
||||
{ "fmeq", { LITREG, LISREG }, MLOP7 + MLDEST + MLIMM11, VLOP7 (0x18) },
|
||||
{ "fmor", { LITREG, LISREG }, MLOP7 + MLDEST + MLIMM11, VLOP7 (0x1b) },
|
||||
{ "fsand", { LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MLIS, VLOP7 (0x16) },
|
||||
{ "fseq", { LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MLIS, VLOP7 (0x14) },
|
||||
{ "fsor", { LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MLIS, VLOP7 (0x17) },
|
||||
{ "fsset", { LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MLIS, VLOP7 (0x15) },
|
||||
{ "waitp", { 0 }, 0xffffffff, 0x800007bf },
|
||||
{ "waitq", { 0 }, 0xffffffff, 0x800003bf },
|
||||
};
|
||||
const int txvu_lower_opcodes_count = sizeof (txvu_lower_opcodes) / sizeof (txvu_opcodes[0]);
|
||||
|
||||
|
|
@ -607,7 +723,7 @@ print_bc (info, insn, value)
|
|||
/* FT register in broadcast case. */
|
||||
|
||||
static long
|
||||
parse_ftregbc (pstr, errmsg)
|
||||
parse_bcftreg (pstr, errmsg)
|
||||
char **pstr;
|
||||
const char **errmsg;
|
||||
{
|
||||
|
|
@ -642,7 +758,7 @@ parse_ftregbc (pstr, errmsg)
|
|||
}
|
||||
|
||||
static void
|
||||
print_ftregbc (info, insn, value)
|
||||
print_bcftreg (info, insn, value)
|
||||
disassemble_info *info;
|
||||
TXVU_INSN insn;
|
||||
long value;
|
||||
|
|
@ -710,3 +826,240 @@ parse_xyz (pstr, errmsg)
|
|||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* F[ST] register using selector in F[ST]F field. */
|
||||
|
||||
static long
|
||||
parse_ffstreg (pstr, errmsg)
|
||||
char **pstr;
|
||||
const char **errmsg;
|
||||
{
|
||||
char *str = *pstr;
|
||||
char *start;
|
||||
long reg;
|
||||
int reg_bc;
|
||||
|
||||
if (tolower (str[0]) != 'v'
|
||||
|| tolower (str[1]) != 'f')
|
||||
{
|
||||
*errmsg = "unknown register";
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* FIXME: quick hack until the framework works. */
|
||||
start = str = str + 2;
|
||||
while (*str && isdigit (*str))
|
||||
++str;
|
||||
reg = atoi (start);
|
||||
reg_bc = parse_bc (&str, errmsg);
|
||||
if (*errmsg)
|
||||
return 0;
|
||||
if (reg_bc != bc)
|
||||
{
|
||||
*errmsg = "register `bc' does not match instruction `bc'";
|
||||
return 0;
|
||||
}
|
||||
*pstr = str;
|
||||
*errmsg = NULL;
|
||||
return reg;
|
||||
}
|
||||
|
||||
static void
|
||||
print_ffstreg (info, insn, value)
|
||||
disassemble_info *info;
|
||||
TXVU_INSN insn;
|
||||
long value;
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "vf%ld", value);
|
||||
print_bc (info, insn, bc);
|
||||
}
|
||||
|
||||
#define INSERT_FN(fn) \
|
||||
static TXVU_INSN CONCAT2 (insert_,fn) \
|
||||
PARAMS ((TXVU_INSN, const struct txvu_operand *, \
|
||||
int, long, const char **))
|
||||
#define EXTRACT_FN(fn) \
|
||||
static long CONCAT2 (extract_,fn) \
|
||||
PARAMS ((TXVU_INSN, const struct txvu_operand *, \
|
||||
int, int *))
|
||||
|
||||
static TXVU_INSN
|
||||
insert_ffstreg (insn, operand, mods, value, errmsg)
|
||||
TXVU_INSN insn;
|
||||
const struct txvu_operand *operand;
|
||||
int mods;
|
||||
long value;
|
||||
const char **errmsg;
|
||||
{
|
||||
}
|
||||
|
||||
static long
|
||||
extract_ffstreg (insn, operand, mods, pinvalid)
|
||||
TXVU_INSN insn;
|
||||
const struct txvu_operand *operand;
|
||||
int mods;
|
||||
int *pinvalid;
|
||||
{
|
||||
}
|
||||
|
||||
/* F register. */
|
||||
|
||||
static long
|
||||
parse_freg (pstr, errmsg)
|
||||
char **pstr;
|
||||
const char **errmsg;
|
||||
{
|
||||
char *str = *pstr;
|
||||
char *start;
|
||||
long reg;
|
||||
int reg_bc;
|
||||
|
||||
if (tolower (str[0]) != 'v'
|
||||
|| tolower (str[1]) != 'f')
|
||||
{
|
||||
*errmsg = "unknown register";
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* FIXME: quick hack until the framework works. */
|
||||
start = str = str + 2;
|
||||
while (*str && isdigit (*str))
|
||||
++str;
|
||||
reg = atoi (start);
|
||||
reg_bc = parse_bc (&str, errmsg);
|
||||
if (*errmsg)
|
||||
return 0;
|
||||
if (reg_bc != bc)
|
||||
{
|
||||
*errmsg = "register `bc' does not match instruction `bc'";
|
||||
return 0;
|
||||
}
|
||||
*pstr = str;
|
||||
*errmsg = NULL;
|
||||
return reg;
|
||||
}
|
||||
|
||||
static void
|
||||
print_freg (info, insn, value)
|
||||
disassemble_info *info;
|
||||
TXVU_INSN insn;
|
||||
long value;
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "vf%ld", value);
|
||||
print_bc (info, insn, bc);
|
||||
}
|
||||
|
||||
/* I register. */
|
||||
|
||||
static long
|
||||
parse_ireg (pstr, errmsg)
|
||||
char **pstr;
|
||||
const char **errmsg;
|
||||
{
|
||||
char *str = *pstr;
|
||||
char *start;
|
||||
long reg;
|
||||
int reg_bc;
|
||||
|
||||
if (tolower (str[0]) != 'v'
|
||||
|| tolower (str[1]) != 'f')
|
||||
{
|
||||
*errmsg = "unknown register";
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* FIXME: quick hack until the framework works. */
|
||||
start = str = str + 2;
|
||||
while (*str && isdigit (*str))
|
||||
++str;
|
||||
reg = atoi (start);
|
||||
reg_bc = parse_bc (&str, errmsg);
|
||||
if (*errmsg)
|
||||
return 0;
|
||||
if (reg_bc != bc)
|
||||
{
|
||||
*errmsg = "register `bc' does not match instruction `bc'";
|
||||
return 0;
|
||||
}
|
||||
*pstr = str;
|
||||
*errmsg = NULL;
|
||||
return reg;
|
||||
}
|
||||
|
||||
static void
|
||||
print_ireg (info, insn, value)
|
||||
disassemble_info *info;
|
||||
TXVU_INSN insn;
|
||||
long value;
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "vf%ld", value);
|
||||
print_bc (info, insn, bc);
|
||||
}
|
||||
|
||||
/* VI01 register. */
|
||||
|
||||
static long
|
||||
parse_vi01 (pstr, errmsg)
|
||||
char **pstr;
|
||||
const char **errmsg;
|
||||
{
|
||||
char *str = *pstr;
|
||||
char *start;
|
||||
long reg;
|
||||
int reg_bc;
|
||||
|
||||
if (tolower (str[0]) != 'v'
|
||||
|| tolower (str[1]) != 'f')
|
||||
{
|
||||
*errmsg = "unknown register";
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* FIXME: quick hack until the framework works. */
|
||||
start = str = str + 2;
|
||||
while (*str && isdigit (*str))
|
||||
++str;
|
||||
reg = atoi (start);
|
||||
reg_bc = parse_bc (&str, errmsg);
|
||||
if (*errmsg)
|
||||
return 0;
|
||||
if (reg_bc != bc)
|
||||
{
|
||||
*errmsg = "register `bc' does not match instruction `bc'";
|
||||
return 0;
|
||||
}
|
||||
*pstr = str;
|
||||
*errmsg = NULL;
|
||||
return reg;
|
||||
}
|
||||
|
||||
static void
|
||||
print_vi01 (info, insn, value)
|
||||
disassemble_info *info;
|
||||
TXVU_INSN insn;
|
||||
long value;
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "vf%ld", value);
|
||||
print_bc (info, insn, bc);
|
||||
}
|
||||
|
||||
/* Lower instruction 12 bit immediate. */
|
||||
|
||||
static TXVU_INSN
|
||||
insert_limm12 (insn, operand, mods, value, errmsg)
|
||||
TXVU_INSN insn;
|
||||
const struct txvu_operand *operand;
|
||||
int mods;
|
||||
long value;
|
||||
const char **errmsg;
|
||||
{
|
||||
}
|
||||
|
||||
static long
|
||||
extract_limm12 (insn, operand, mods, pinvalid)
|
||||
TXVU_INSN insn;
|
||||
const struct txvu_operand *operand;
|
||||
int mods;
|
||||
int *pinvalid;
|
||||
{
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue