x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifier
Since we accept these without suffix / operand size specifier, we should
also do so with one. (The fact that we unilaterally accept these, other
than far branches, rather than limiting them to Intel64 mode, will be
taken care of later on.)
Also take the opportunity and make sure "lfs <reg>, tbyte ptr <mem>"
et al get rejected outside of 64-bit mode. This became broken by
dc2be329b9 ("i386: Only check suffix in instruction mnemonic").
Furthermore cover lgdt et al in the Intel syntax handling as well, which
continued to work after said commit just by coincidence.
This commit is contained in:
Jan Beulich
parent
d488367a42
commit
0ba59a2940
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@ -1,3 +1,17 @@
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2019-12-04 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386-intel.c (i386_intel_operand): Handle LFS et al
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as well as LGDT at al when processing O_tbyte_ptr.
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* testsuite/gas/i386/intelbad.s: Add LDS et al cases.
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* testsuite/gas/i386/x86-64-intel64.s,
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* testsuite/gas/i386/x86-64-opcode.s: Add LFS et al cases.
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* testsuite/gas/i386/ilp32/x86-64-intel64.d: Add -mintel64
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command line option and fold expectations with parent dir test.
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* testsuite/gas/i386/x86-64-intel64.d: Add -mintel64 command
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line option and adjust expectations.
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* testsuite/gas/i386/intelbad.l,
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testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.
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2019-12-04 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386-intel.c (i386_intel_operand): Also handle DWORD
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@ -698,6 +698,15 @@ i386_intel_operand (char *operand_string, int got_a_float)
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i.types[this_operand].bitfield.tbyte = 1;
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if (got_a_float == 1)
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suffix = LONG_DOUBLE_MNEM_SUFFIX;
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else if (current_templates->start->operand_types[0].bitfield.fword
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|| current_templates->start->operand_types[0].bitfield.tbyte)
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{
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/* l[defgs]s, [ls][gi]dt */
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if (flag_code == CODE_64BIT)
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suffix = QWORD_MNEM_SUFFIX;
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else
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i.types[this_operand].bitfield.byte = 1; /* cause an error */
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}
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else
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suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
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break;
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@ -1,11 +1,5 @@
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#source: ../x86-64-intel64.s
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#as: -mintel64
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#objdump: -dw
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#name: x86-64 (ILP32) Intel64
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 0f 05 syscall
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[ ]*[a-f0-9]+: 0f 07 sysret
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#pass
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#dump: ../x86-64-intel64.d
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@ -152,3 +152,8 @@
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.*:168: Error: .*
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.*:169: Error: .*
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.*:172: Error: .*
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.*:174: Error: .*
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.*:175: Error: .*
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.*:176: Warning: .*
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.*:177: Error: .*
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.*:178: Error: .*
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@ -170,3 +170,9 @@ start:
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#XXX? movzx eax, byte ptr [1]
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mov eax, 3:5
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lds eax, byte ptr [eax]
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les eax, word ptr [eax]
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lfs eax, dword ptr [eax]
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lgs eax, qword ptr [eax]
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lss eax, tbyte ptr [eax]
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@ -1,3 +1,4 @@
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#as: -mintel64
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#objdump: -dw
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#name: x86-64 Intel64
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@ -5,6 +6,18 @@
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 48 0f b4 08 lfs \(%rax\),%rcx
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[ ]*[a-f0-9]+: 48 0f b4 08 lfs \(%rax\),%rcx
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[ ]*[a-f0-9]+: 48 0f b5 11 lgs \(%rcx\),%rdx
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[ ]*[a-f0-9]+: 48 0f b5 11 lgs \(%rcx\),%rdx
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[ ]*[a-f0-9]+: 48 0f b2 1a lss \(%rdx\),%rbx
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[ ]*[a-f0-9]+: 48 0f b2 1a lss \(%rdx\),%rbx
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[ ]*[a-f0-9]+: 0f 05 syscall
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[ ]*[a-f0-9]+: 0f 07 sysret
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[ ]*[a-f0-9]+: 48 0f b4 01 lfs \(%rcx\),%rax
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[ ]*[a-f0-9]+: 48 0f b4 01 lfs \(%rcx\),%rax
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[ ]*[a-f0-9]+: 48 0f b5 0a lgs \(%rdx\),%rcx
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[ ]*[a-f0-9]+: 48 0f b5 0a lgs \(%rdx\),%rcx
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[ ]*[a-f0-9]+: 48 0f b2 13 lss \(%rbx\),%rdx
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[ ]*[a-f0-9]+: 48 0f b2 13 lss \(%rbx\),%rdx
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#pass
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@ -3,5 +3,20 @@
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.text
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.arch core2
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_start:
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lfs (%rax), %rcx
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lfsq (%rax), %rcx
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lgs (%rcx), %rdx
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lgsq (%rcx), %rdx
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lss (%rdx), %rbx
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lssq (%rdx), %rbx
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syscall
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sysret
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.intel_syntax noprefix
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lfs rax, [rcx]
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lfs rax, tbyte ptr [rcx]
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lgs rcx, [rdx]
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lgs rcx, tbyte ptr [rdx]
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lss rdx, [rbx]
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lss rdx, tbyte ptr [rbx]
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@ -45,6 +45,18 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c7 00 00 00 00 70 movl \$0x70000000,\(%rax\)
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[ ]*[a-f0-9]+: 49 c7 00 00 00 00 70 movq \$0x70000000,\(%r8\)
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[ ]*[a-f0-9]+: 48 c7 00 00 00 00 70 movq \$0x70000000,\(%rax\)
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[ ]*[a-f0-9]+: 0f b4 08 lfs \(%rax\),%ecx
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[ ]*[a-f0-9]+: 0f b4 01 lfs \(%rcx\),%eax
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[ ]*[a-f0-9]+: 66 0f b4 08 lfs \(%rax\),%cx
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[ ]*[a-f0-9]+: 66 0f b4 01 lfs \(%rcx\),%ax
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[ ]*[a-f0-9]+: 0f b5 11 lgs \(%rcx\),%edx
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[ ]*[a-f0-9]+: 0f b5 0a lgs \(%rdx\),%ecx
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[ ]*[a-f0-9]+: 66 0f b5 11 lgs \(%rcx\),%dx
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[ ]*[a-f0-9]+: 66 0f b5 0a lgs \(%rdx\),%cx
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[ ]*[a-f0-9]+: 0f b2 1a lss \(%rdx\),%ebx
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[ ]*[a-f0-9]+: 0f b2 13 lss \(%rbx\),%edx
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[ ]*[a-f0-9]+: 66 0f b2 1a lss \(%rdx\),%bx
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[ ]*[a-f0-9]+: 66 0f b2 13 lss \(%rbx\),%dx
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[ ]*[a-f0-9]+: 41 0f c3 00 movnti %eax,\(%r8\)
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[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\)
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[ ]*[a-f0-9]+: 49 0f c3 00 movnti %rax,\(%r8\)
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@ -50,6 +50,20 @@
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MOVq $0x70000000,(%r8) # -- -- -- 49 C7 00 00 00 00 70 ; REX for 64-bit operand size. REX to access upper reg.
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MOVq $0x70000000,(%rax) # -- -- -- 48 C7 00 00 00 00 70 ; REX for 64-bit operand size
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# LFS etc
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LFS (%rax), %ecx # -- -- -- -- 0F B4 ..
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LFSl (%rcx), %eax # -- -- -- -- 0F B4 ..
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LFS (%rax), %cx # 66 -- -- -- 0F B4 ..
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LFSw (%rcx), %ax # 66 -- -- -- 0F B4 ..
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LGS (%rcx), %edx # -- -- -- -- 0F B5 ..
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LGSl (%rdx), %ecx # -- -- -- -- 0F B5 ..
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LGS (%rcx), %dx # 66 -- -- -- 0F B5 ..
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LGSw (%rdx), %cx # 66 -- -- -- 0F B5 ..
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LSS (%rdx), %ebx # -- -- -- -- 0F B2 ..
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LSSl (%rbx), %edx # -- -- -- -- 0F B2 ..
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LSS (%rdx), %bx # 66 -- -- -- 0F B2 ..
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LSSw (%rbx), %dx # 66 -- -- -- 0F B2 ..
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# MOVNTI
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MOVNTI %eax,(%r8) # -- -- -- 41 0f c3 00 ; REX to access upper reg.
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MOVNTI %eax,(%rax) # -- -- -- -- 0f c3 00
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@ -1,3 +1,8 @@
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2019-12-04 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
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* i386-tbl.h: Re-generate.
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2019-12-04 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
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@ -201,9 +201,9 @@ lea, 2, 0x8d, None, 1, 0, Modrm|Anysize|No_bSuf|No_sSuf|No_ldSuf, { BaseIndex, R
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// Load segment registers from memory.
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lds, 2, 0xc5, None, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
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les, 2, 0xc4, None, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
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lfs, 2, 0xfb4, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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lgs, 2, 0xfb5, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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lss, 2, 0xfb2, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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lfs, 2, 0xfb4, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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lgs, 2, 0xfb5, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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lss, 2, 0xfb2, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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// Flags register instructions.
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clc, 0, 0xf8, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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@ -965,7 +965,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0,
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@ -979,7 +979,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0,
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@ -993,7 +993,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0,
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