gas/
2009-01-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (December, 2008) * config/tc-i386.c (build_modrm_byte): Remove 5 operand instruction support. Don't swap REG and NDS for FMA. gas/testsuite/ 2009-01-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (December, 2008) * gas/i386/arch-10.s: Replace vfmaddpd with vfmadd132pd. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/inval-avx.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-inval-avx.l: Likewise. * gas/i386/avx.s: Remove vpermil2ps/vpermil2pd and FMA instructions. Update tests. * gas/i386/inval-avx.s: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-inval-avx.s: Likewise. * gas/i386/fma.d: New. * gas/i386/fma.s: Likewise. * gas/i386/fma-intel.d: Likewise. * gas/i386/x86-64-fma.d: Likewise. * gas/i386/x86-64-fma.s: Likewise. * gas/i386/x86-64-fma-intel.d: Likewise. * gas/i386/i386.exp: Run fma, fma-intel, x86-64-fma and x86-64-fma-intel. opcodes/ 2009-01-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (December, 2008) * i386-dis.c (OP_VEX_FMA): Removed. (OP_EX_VexW): Likewise. (OP_EX_VexImmW): Likewise. (OP_XMM_VexW): Likewise. (VEXI4_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. (VexI4): Likewise. (VexFMA): Likewise. (Vex128FMA): Likewise. (EXVexW): Likewise. (EXdVexW): Likewise. (EXqVexW): Likewise. (EXVexImmW): Likewise. (XMVexW): Likewise. (VPERMIL2): Likewise. (PREFIX_VEX_3A48...PREFIX_VEX_3A4A): Likewise. (PREFIX_VEX_3A5C...PREFIX_VEX_3A5F): Likewise. (PREFIX_VEX_3A68...PREFIX_VEX_3A6F): Likewise. (PREFIX_VEX_3A78...PREFIX_VEX_3A7F): Likewise. (VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2): Likewise. (VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2): Likewise. (get_vex_imm8): Likewise. (OP_EX_VexReg): Likewise. vpermil2_op): Likewise. (EXVexWdq): New. (vex_w_dq_mode): Likewise. (PREFIX_VEX_3896...PREFIX_VEX_389F): Likewise. (PREFIX_VEX_38A6...PREFIX_VEX_38AF): Likewise. (PREFIX_VEX_38B6...PREFIX_VEX_38BF): Likewise. (es_reg): Updated. (PREFIX_VEX_38DB): Likewise. (PREFIX_VEX_3A4A): Likewise. (PREFIX_VEX_3A60): Likewise. (PREFIX_VEX_3ADF): Likewise. (VEX_LEN_3ADF_P_2): Likewise. (prefix_table): Remove PREFIX_VEX_3A48...PREFIX_VEX_3A4A, PREFIX_VEX_3A5C...PREFIX_VEX_3A5F, PREFIX_VEX_3A68...PREFIX_VEX_3A6F and PREFIX_VEX_3A78...PREFIX_VEX_3A7F. Add PREFIX_VEX_3896...PREFIX_VEX_389F, PREFIX_VEX_38A6...PREFIX_VEX_38AF and PREFIX_VEX_38B6...PREFIX_VEX_38BF. (vex_table): Likewise. (vex_len_table): Remove VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2 and VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2. (putop): Support "%XW". (intel_operand_size): Handle vex_w_dq_mode. * i386-opc.h (VexNDS): Add a comment for VEX NDS and VEX DDS. * i386-opc.tbl: Remove vpermil2pd/vpermil2ps and old FMA instructions. Add new FMA instructions. * i386-tbl.h: Regenerated.
This commit is contained in:
parent
f21cc1a2b7
commit
0bfee64967
1881
gas/ChangeLog
1881
gas/ChangeLog
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -1,6 +1,6 @@
|
|||
/* tc-i386.c -- Assemble code for the Intel 80386
|
||||
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
|
||||
2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
|
||||
2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
@ -5142,125 +5142,43 @@ build_modrm_byte (void)
|
|||
{
|
||||
unsigned int nds, reg;
|
||||
|
||||
if (i.tm.opcode_modifier.veximmext
|
||||
&& i.tm.opcode_modifier.immext)
|
||||
{
|
||||
dest = i.operands - 2;
|
||||
assert (dest == 3);
|
||||
}
|
||||
else
|
||||
dest = i.operands - 1;
|
||||
dest = i.operands - 1;
|
||||
nds = dest - 1;
|
||||
source = 1;
|
||||
reg = 0;
|
||||
|
||||
/* There are 2 kinds of instructions:
|
||||
1. 5 operands: one immediate operand and 4 register
|
||||
operands or 3 register operands plus 1 memory operand.
|
||||
It must have VexNDS and VexW0 or VexW1. The destination
|
||||
must be either XMM or YMM register.
|
||||
2. 4 operands: 4 register operands or 3 register operands
|
||||
plus 1 memory operand. It must have VexNDS and VexImmExt. */
|
||||
if (!((i.reg_operands == 4
|
||||
|| (i.reg_operands == 3 && i.mem_operands == 1))
|
||||
&& i.tm.opcode_modifier.vexnds
|
||||
&& (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
|
||||
|| operand_type_equal (&i.tm.operand_types[dest], ®ymm))
|
||||
&& ((dest == 4
|
||||
&& i.imm_operands == 1
|
||||
&& i.types[0].bitfield.vex_imm4
|
||||
&& (i.tm.opcode_modifier.vexw0
|
||||
|| i.tm.opcode_modifier.vexw1))
|
||||
|| (dest == 3
|
||||
&& (i.imm_operands == 0
|
||||
|| (i.imm_operands == 1
|
||||
&& i.tm.opcode_modifier.immext))
|
||||
&& i.tm.opcode_modifier.veximmext))))
|
||||
abort ();
|
||||
|
||||
if (i.imm_operands == 0)
|
||||
{
|
||||
/* When there is no immediate operand, generate an 8bit
|
||||
immediate operand to encode the first operand. */
|
||||
expressionS *exp = &im_expressions[i.imm_operands++];
|
||||
i.op[i.operands].imms = exp;
|
||||
i.types[i.operands] = imm8;
|
||||
i.operands++;
|
||||
/* If VexW1 is set, the first operand is the source and
|
||||
the second operand is encoded in the immediate operand. */
|
||||
if (i.tm.opcode_modifier.vexw1)
|
||||
{
|
||||
source = 0;
|
||||
reg = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
source = 1;
|
||||
reg = 0;
|
||||
}
|
||||
|
||||
/* FMA swaps REG and NDS. */
|
||||
if (i.tm.cpu_flags.bitfield.cpufma)
|
||||
{
|
||||
unsigned int tmp;
|
||||
tmp = reg;
|
||||
reg = nds;
|
||||
nds = tmp;
|
||||
}
|
||||
|
||||
assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm)
|
||||
/* This instruction must have 4 operands: 4 register operands
|
||||
or 3 register operands plus 1 memory operand. It must have
|
||||
VexNDS and VexImmExt. */
|
||||
assert (i.operands == 4
|
||||
&& (i.reg_operands == 4
|
||||
|| (i.reg_operands == 3 && i.mem_operands == 1))
|
||||
&& i.tm.opcode_modifier.vexnds
|
||||
&& i.tm.opcode_modifier.veximmext
|
||||
&& (operand_type_equal (&i.tm.operand_types[dest],
|
||||
®xmm)
|
||||
|| operand_type_equal (&i.tm.operand_types[dest],
|
||||
®ymm))
|
||||
&& (operand_type_equal (&i.tm.operand_types[nds],
|
||||
®xmm)
|
||||
|| operand_type_equal (&i.tm.operand_types[nds],
|
||||
®ymm))
|
||||
&& (operand_type_equal (&i.tm.operand_types[reg],
|
||||
®xmm)
|
||||
|| operand_type_equal (&i.tm.operand_types[reg],
|
||||
®ymm));
|
||||
exp->X_op = O_constant;
|
||||
exp->X_add_number
|
||||
= ((i.op[reg].regs->reg_num
|
||||
+ ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
unsigned int imm;
|
||||
®ymm)));
|
||||
|
||||
if (i.tm.opcode_modifier.vexw0)
|
||||
{
|
||||
/* If VexW0 is set, the third operand is the source and
|
||||
the second operand is encoded in the immediate
|
||||
operand. */
|
||||
source = 2;
|
||||
reg = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* VexW1 is set, the second operand is the source and
|
||||
the third operand is encoded in the immediate
|
||||
operand. */
|
||||
source = 1;
|
||||
reg = 2;
|
||||
}
|
||||
/* Generate an 8bit immediate operand to encode the register
|
||||
operand. */
|
||||
expressionS *exp = &im_expressions[i.imm_operands++];
|
||||
i.op[i.operands].imms = exp;
|
||||
i.types[i.operands] = imm8;
|
||||
i.operands++;
|
||||
exp->X_op = O_constant;
|
||||
exp->X_add_number
|
||||
= ((i.op[0].regs->reg_num
|
||||
+ ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
|
||||
|
||||
if (i.tm.opcode_modifier.immext)
|
||||
{
|
||||
/* When ImmExt is set, the immdiate byte is the last
|
||||
operand. */
|
||||
imm = i.operands - 1;
|
||||
source--;
|
||||
reg--;
|
||||
}
|
||||
else
|
||||
{
|
||||
imm = 0;
|
||||
|
||||
/* Turn on Imm8 so that output_imm will generate it. */
|
||||
i.types[imm].bitfield.imm8 = 1;
|
||||
}
|
||||
|
||||
assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm)
|
||||
|| operand_type_equal (&i.tm.operand_types[reg],
|
||||
®ymm));
|
||||
i.op[imm].imms->X_add_number
|
||||
|= ((i.op[reg].regs->reg_num
|
||||
+ ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
|
||||
}
|
||||
|
||||
assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
|
||||
|| operand_type_equal (&i.tm.operand_types[nds], ®ymm));
|
||||
i.vex.register_specifier = i.op[nds].regs;
|
||||
}
|
||||
else
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -61,7 +61,7 @@ GAS LISTING .*
|
|||
[ ]*31[ ]+\# AES \+ AVX
|
||||
[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*33[ ]+\# FMA
|
||||
[ ]*34[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*35[ ]+\# MOVBE
|
||||
[ ]*36[ ]+movbe \(%ecx\),%ebx
|
||||
[ ]*37[ ]+\# EPT
|
||||
|
|
|
@ -60,7 +60,7 @@ GAS LISTING .*
|
|||
[ ]*31[ ]+\# AES \+ AVX
|
||||
[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*33[ ]+\# FMA
|
||||
[ ]*34[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*35[ ]+\# MOVBE
|
||||
[ ]*36[ ]+movbe \(%ecx\),%ebx
|
||||
[ ]*37[ ]+\# EPT
|
||||
|
|
|
@ -56,7 +56,7 @@ GAS LISTING .*
|
|||
[ ]*31[ ]+\# AES \+ AVX
|
||||
[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*33[ ]+\# FMA
|
||||
[ ]*34[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*35[ ]+\# MOVBE
|
||||
[ ]*36[ ]+movbe \(%ecx\),%ebx
|
||||
[ ]*37[ ]+\# EPT
|
||||
|
|
|
@ -54,7 +54,7 @@ GAS LISTING .*
|
|||
[ ]*31[ ]+\# AES \+ AVX
|
||||
[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*33[ ]+\# FMA
|
||||
[ ]*34[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*35[ ]+\# MOVBE
|
||||
[ ]*36[ ]+movbe \(%ecx\),%ebx
|
||||
[ ]*37[ ]+\# EPT
|
||||
|
|
|
@ -22,7 +22,7 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
|
||||
|
|
|
@ -31,7 +31,7 @@ pclmulqdq $8,%xmm1,%xmm0
|
|||
# AES + AVX
|
||||
vaesenc (%ecx),%xmm0,%xmm2
|
||||
# FMA
|
||||
vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
# MOVBE
|
||||
movbe (%ecx),%ebx
|
||||
# EPT
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -144,6 +144,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "opts-intel"
|
||||
run_dump_test "sse2avx-opts"
|
||||
run_dump_test "sse2avx-opts-intel"
|
||||
run_dump_test "fma"
|
||||
run_dump_test "fma-intel"
|
||||
|
||||
# These tests require support for 8 and 16 bit relocs,
|
||||
# so we only run them for ELF and COFF targets.
|
||||
|
@ -303,6 +305,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-sse2avx-opts-intel"
|
||||
run_dump_test "x86-64-avx-swap"
|
||||
run_dump_test "x86-64-avx-swap-intel"
|
||||
run_dump_test "x86-64-fma"
|
||||
run_dump_test "x86-64-fma-intel"
|
||||
|
||||
if { ![istarget "*-*-aix*"]
|
||||
&& ![istarget "*-*-beos*"]
|
||||
|
|
|
@ -2,53 +2,9 @@
|
|||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:9: Error: .*
|
||||
.*:10: Error: .*
|
||||
.*:11: Error: .*
|
||||
.*:12: Error: .*
|
||||
.*:13: Error: .*
|
||||
.*:14: Error: .*
|
||||
.*:15: Error: .*
|
||||
.*:16: Error: .*
|
||||
.*:17: Error: .*
|
||||
.*:18: Error: .*
|
||||
.*:19: Error: .*
|
||||
.*:20: Error: .*
|
||||
.*:21: Error: .*
|
||||
.*:22: Error: .*
|
||||
.*:23: Error: .*
|
||||
.*:24: Error: .*
|
||||
.*:25: Error: .*
|
||||
.*:26: Error: .*
|
||||
.*:27: Error: .*
|
||||
.*:28: Error: .*
|
||||
.*:31: Error: .*
|
||||
.*:32: Error: .*
|
||||
.*:33: Error: .*
|
||||
.*:34: Error: .*
|
||||
.*:35: Error: .*
|
||||
.*:36: Error: .*
|
||||
.*:37: Error: .*
|
||||
.*:38: Error: .*
|
||||
.*:39: Error: .*
|
||||
.*:40: Error: .*
|
||||
.*:41: Error: .*
|
||||
.*:42: Error: .*
|
||||
.*:43: Error: .*
|
||||
.*:44: Error: .*
|
||||
.*:45: Error: .*
|
||||
.*:46: Error: .*
|
||||
.*:47: Error: .*
|
||||
.*:48: Error: .*
|
||||
.*:49: Error: .*
|
||||
.*:50: Error: .*
|
||||
.*:51: Error: .*
|
||||
.*:52: Error: .*
|
||||
.*:53: Error: .*
|
||||
.*:54: Error: .*
|
||||
.*:55: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
|
@ -58,52 +14,8 @@ GAS LISTING .*
|
|||
[ ]*4[ ]+vcvtpd2dq \(%ecx\),%xmm2
|
||||
[ ]*5[ ]+vcvtpd2ps \(%ecx\),%xmm2
|
||||
[ ]*6[ ]+vcvttpd2dq \(%ecx\),%xmm2
|
||||
[ ]*7[ ]+vfmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*8[ ]+vfmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*9[ ]+vfmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*10[ ]+vfmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*11[ ]+vfmaddsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*12[ ]+vfmaddsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*13[ ]+vfmsubaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*14[ ]+vfmsubaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*15[ ]+vfmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*16[ ]+vfmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*17[ ]+vfmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*18[ ]+vfmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*19[ ]+vfnmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*20[ ]+vfnmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*21[ ]+vfnmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*22[ ]+vfnmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*23[ ]+vfnmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*24[ ]+vfnmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*25[ ]+vfnmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*26[ ]+vfnmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*27[ ]+vpermil2pd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*28[ ]+vpermil2ps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*29[ ]+
|
||||
[ ]*30[ ]+\.intel_syntax noprefix
|
||||
[ ]*31[ ]+vcvtpd2dq xmm2,\[ecx\]
|
||||
[ ]*32[ ]+vcvtpd2ps xmm2,\[ecx\]
|
||||
[ ]*33[ ]+vcvttpd2dq xmm2,\[ecx\]
|
||||
[ ]*34[ ]+vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*35[ ]+vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*36[ ]+vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*37[ ]+vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*38[ ]+vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*39[ ]+vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*40[ ]+vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*41[ ]+vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*42[ ]+vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*43[ ]+vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*44[ ]+vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*45[ ]+vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*46[ ]+vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*47[ ]+vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*48[ ]+vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*49[ ]+vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*50[ ]+vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*51[ ]+vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*52[ ]+vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*53[ ]+vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*54[ ]+vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*55[ ]+vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*7[ ]+
|
||||
[ ]*8[ ]+\.intel_syntax noprefix
|
||||
[ ]*9[ ]+vcvtpd2dq xmm2,\[ecx\]
|
||||
[ ]*10[ ]+vcvtpd2ps xmm2,\[ecx\]
|
||||
[ ]*11[ ]+vcvttpd2dq xmm2,\[ecx\]
|
||||
|
|
|
@ -4,52 +4,8 @@ _start:
|
|||
vcvtpd2dq (%ecx),%xmm2
|
||||
vcvtpd2ps (%ecx),%xmm2
|
||||
vcvttpd2dq (%ecx),%xmm2
|
||||
vfmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vpermil2pd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vpermil2ps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
|
||||
.intel_syntax noprefix
|
||||
vcvtpd2dq xmm2,[ecx]
|
||||
vcvtpd2ps xmm2,[ecx]
|
||||
vcvttpd2dq xmm2,[ecx]
|
||||
vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
|
|
|
@ -22,7 +22,7 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%rcx\),%xmm0,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
|
||||
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
|
||||
|
|
|
@ -31,7 +31,7 @@ pclmulqdq $8,%xmm1,%xmm0
|
|||
# AES + AVX
|
||||
vaesenc (%rcx),%xmm0,%xmm2
|
||||
# FMA
|
||||
vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
# MOVBE
|
||||
movbe (%rcx),%ebx
|
||||
# EPT
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -2,53 +2,9 @@
|
|||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:9: Error: .*
|
||||
.*:10: Error: .*
|
||||
.*:11: Error: .*
|
||||
.*:12: Error: .*
|
||||
.*:13: Error: .*
|
||||
.*:14: Error: .*
|
||||
.*:15: Error: .*
|
||||
.*:16: Error: .*
|
||||
.*:17: Error: .*
|
||||
.*:18: Error: .*
|
||||
.*:19: Error: .*
|
||||
.*:20: Error: .*
|
||||
.*:21: Error: .*
|
||||
.*:22: Error: .*
|
||||
.*:23: Error: .*
|
||||
.*:24: Error: .*
|
||||
.*:25: Error: .*
|
||||
.*:26: Error: .*
|
||||
.*:27: Error: .*
|
||||
.*:28: Error: .*
|
||||
.*:31: Error: .*
|
||||
.*:32: Error: .*
|
||||
.*:33: Error: .*
|
||||
.*:34: Error: .*
|
||||
.*:35: Error: .*
|
||||
.*:36: Error: .*
|
||||
.*:37: Error: .*
|
||||
.*:38: Error: .*
|
||||
.*:39: Error: .*
|
||||
.*:40: Error: .*
|
||||
.*:41: Error: .*
|
||||
.*:42: Error: .*
|
||||
.*:43: Error: .*
|
||||
.*:44: Error: .*
|
||||
.*:45: Error: .*
|
||||
.*:46: Error: .*
|
||||
.*:47: Error: .*
|
||||
.*:48: Error: .*
|
||||
.*:49: Error: .*
|
||||
.*:50: Error: .*
|
||||
.*:51: Error: .*
|
||||
.*:52: Error: .*
|
||||
.*:53: Error: .*
|
||||
.*:54: Error: .*
|
||||
.*:55: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
|
@ -58,52 +14,8 @@ GAS LISTING .*
|
|||
[ ]*4[ ]+vcvtpd2dq \(%rcx\),%xmm2
|
||||
[ ]*5[ ]+vcvtpd2ps \(%rcx\),%xmm2
|
||||
[ ]*6[ ]+vcvttpd2dq \(%rcx\),%xmm2
|
||||
[ ]*7[ ]+vfmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*8[ ]+vfmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*9[ ]+vfmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*10[ ]+vfmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*11[ ]+vfmaddsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*12[ ]+vfmaddsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*13[ ]+vfmsubaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*14[ ]+vfmsubaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*15[ ]+vfmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*16[ ]+vfmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*17[ ]+vfmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*18[ ]+vfmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*19[ ]+vfnmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*20[ ]+vfnmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*21[ ]+vfnmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*22[ ]+vfnmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*23[ ]+vfnmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*24[ ]+vfnmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*25[ ]+vfnmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*26[ ]+vfnmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*27[ ]+vpermil2pd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*28[ ]+vpermil2ps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*29[ ]+
|
||||
[ ]*30[ ]+\.intel_syntax noprefix
|
||||
[ ]*31[ ]+vcvtpd2dq xmm2,\[rcx\]
|
||||
[ ]*32[ ]+vcvtpd2ps xmm2,\[rcx\]
|
||||
[ ]*33[ ]+vcvttpd2dq xmm2,\[rcx\]
|
||||
[ ]*34[ ]+vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*35[ ]+vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*36[ ]+vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*37[ ]+vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*38[ ]+vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*39[ ]+vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*40[ ]+vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*41[ ]+vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*42[ ]+vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*43[ ]+vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*44[ ]+vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*45[ ]+vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*46[ ]+vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*47[ ]+vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*48[ ]+vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*49[ ]+vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*50[ ]+vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*51[ ]+vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*52[ ]+vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*53[ ]+vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*54[ ]+vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*55[ ]+vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*7[ ]+
|
||||
[ ]*8[ ]+\.intel_syntax noprefix
|
||||
[ ]*9[ ]+vcvtpd2dq xmm2,\[rcx\]
|
||||
[ ]*10[ ]+vcvtpd2ps xmm2,\[rcx\]
|
||||
[ ]*11[ ]+vcvttpd2dq xmm2,\[rcx\]
|
||||
|
|
|
@ -4,52 +4,8 @@ _start:
|
|||
vcvtpd2dq (%rcx),%xmm2
|
||||
vcvtpd2ps (%rcx),%xmm2
|
||||
vcvttpd2dq (%rcx),%xmm2
|
||||
vfmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vpermil2pd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vpermil2ps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
|
||||
.intel_syntax noprefix
|
||||
vcvtpd2dq xmm2,[rcx]
|
||||
vcvtpd2ps xmm2,[rcx]
|
||||
vcvttpd2dq xmm2,[rcx]
|
||||
vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
|
|
1233
opcodes/ChangeLog
1233
opcodes/ChangeLog
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -1,5 +1,5 @@
|
|||
/* Declarations for Intel 80386 opcode table
|
||||
Copyright 2007, 2008
|
||||
Copyright 2007, 2008, 2009
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU opcodes library.
|
||||
|
@ -248,8 +248,9 @@ typedef union i386_cpu_flags
|
|||
#define Vex (Drexc + 1)
|
||||
/* insn has 256bit VEX prefix. */
|
||||
#define Vex256 (Vex + 1)
|
||||
/* insn has VEX NDS. Register-only source is encoded in Vex
|
||||
prefix. */
|
||||
/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
|
||||
We use VexNDS on insns with VEX DDS since the register-only source
|
||||
is the second source register. */
|
||||
#define VexNDS (Vex256 + 1)
|
||||
/* insn has VEX NDD. Register destination is encoded in Vex
|
||||
prefix. */
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
// i386 opcode table.
|
||||
// Copyright 2007, 2008
|
||||
// Copyright 2007, 2008, 2009
|
||||
// Free Software Foundation, Inc.
|
||||
//
|
||||
// This file is part of the GNU opcodes library.
|
||||
|
@ -2192,14 +2192,6 @@ vpcmpgtw, 3, 0x6665, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|
|
|||
vpcmpistri, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vpcmpistrm, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vperm2f128, 4, 0x6606, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
|
@ -2208,30 +2200,6 @@ vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bS
|
|||
vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ByteOkIntel|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
vpextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
vpextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F3A|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
|
||||
|
@ -2389,70 +2357,102 @@ vaeskeygenassist, 3, 0x66df, None, 1, CpuAVX|CpuAES, Modrm|Vex|Vex0F3A|IgnoreSiz
|
|||
|
||||
// FMA instructions
|
||||
|
||||
vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsd, 4, 0x666b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsd, 4, 0x666b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddss, 4, 0x666a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddss, 4, 0x666a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubsd, 4, 0x666f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubsd, 4, 0x666f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubss, 4, 0x666e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubss, 4, 0x666e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmaddsd, 4, 0x667b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddsd, 4, 0x667b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddss, 4, 0x667a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddss, 4, 0x667a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmsubsd, 4, 0x667f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubsd, 4, 0x667f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmadd132ps, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd132ps, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmadd213pd, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd213pd, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmadd213ps, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd213ps, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmadd231pd, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd231pd, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmadd231ps, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd231ps, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmadd132sd, 3, 0x6699, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd132ss, 3, 0x6699, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd213sd, 3, 0x66a9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd213ss, 3, 0x66a9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd231sd, 3, 0x66b9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmadd231ss, 3, 0x66b9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsub132pd, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsub132pd, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsub132ps, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsub132ps, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsub213pd, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsub213pd, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsub213ps, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsub213ps, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsub231pd, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsub231pd, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsub231ps, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsub231ps, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubadd132pd, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubadd132pd, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubadd132ps, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubadd132ps, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubadd213pd, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubadd213pd, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubadd213ps, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubadd213ps, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubadd231pd, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubadd231pd, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubadd231ps, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubadd231ps, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsub132pd, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsub132pd, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsub132ps, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsub132ps, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsub213pd, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsub213pd, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsub213ps, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsub213ps, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsub231pd, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsub231pd, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsub231ps, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsub231ps, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsub132sd, 3, 0x669b, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsub132ss, 3, 0x669b, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsub213sd, 3, 0x66ab, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsub213ss, 3, 0x66ab, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsub231sd, 3, 0x66bb, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsub231ss, 3, 0x66bb, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd132pd, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd132pd, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmadd132ps, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd132ps, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmadd213pd, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd213pd, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmadd213ps, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd213ps, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmadd231pd, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd231pd, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmadd231ps, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd231ps, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmadd132sd, 3, 0x669d, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd132ss, 3, 0x669d, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd213sd, 3, 0x66ad, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd213ss, 3, 0x66ad, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd231sd, 3, 0x66bd, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmadd231ss, 3, 0x66bd, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub132pd, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub132pd, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmsub132ps, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub132ps, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmsub213pd, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub213pd, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmsub213ps, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub213ps, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmsub132sd, 3, 0x669f, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub132ss, 3, 0x669f, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub213sd, 3, 0x66af, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub213ss, 3, 0x66af, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub231sd, 3, 0x66bf, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub231ss, 3, 0x66bf, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
// AMD 3DNow! instructions.
|
||||
|
||||
|
|
2632
opcodes/i386-tbl.h
2632
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue