ubsan: m32c: left shift of negative value
More nonsense fixing "bugs" with left shifts of signed values. Yes, the C standard does say this is undefined (and right shifts of signed values are implementation defined BTW) but in practice there is no problem with current machines. 1's complement is a thing of the past. cpu/ * m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting. (f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise. (f-dst32-rn-prefixed-QI): Likewise. (f-dsp-32-s32): Mask before shifting left. (f-dsp-48-u32, f-dsp-48-s32): Likewise. (f-bitbase32-16-s11-unprefixed): Multiply signed field rather than shifting left. (f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise. (h-gr-SI): Mask before shifting. opcodes/ * m32c-ibld.c: Regenerate.
This commit is contained in:
Alan Modra
parent
b5d36aaa8a
commit
0c115f8483
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@ -1,3 +1,15 @@
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2020-01-30 Alan Modra <amodra@gmail.com>
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* m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.
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(f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise.
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(f-dst32-rn-prefixed-QI): Likewise.
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(f-dsp-32-s32): Mask before shifting left.
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(f-dsp-48-u32, f-dsp-48-s32): Likewise.
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(f-bitbase32-16-s11-unprefixed): Multiply signed field rather than
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shifting left.
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(f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise.
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(h-gr-SI): Mask before shifting.
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2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
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* bpf.cpu (define-alu-insn-un): The unary BPF instructions
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36
cpu/m32c.cpu
36
cpu/m32c.cpu
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@ -240,7 +240,7 @@
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; r1l 10'b 11'b
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; r1h 11'b 01'b
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(df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT
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((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
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((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert
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((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
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)
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; QI mode gr encoding for m32c is different than for m16c. The hardware
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@ -252,7 +252,7 @@
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; r1l 10'b 11'b
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; r1h 11'b 01'b
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(df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT
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((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
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((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert
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((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
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)
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; HI mode gr encoding for m32c is different than for m16c. The hardware
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@ -316,11 +316,11 @@
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; r1l 10'b 11'b
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; r1h 11'b 01'b
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(df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT
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((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
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((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert
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((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
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)
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(df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT
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((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
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((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert
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((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
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)
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; HI mode gr encoding for m32c is different than for m16c. The hardware
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@ -720,22 +720,22 @@
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(ext INT
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(or SI
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(or SI
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(and (srl value 24) #x000000ff)
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(and (srl value 8) #x0000ff00))
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(and (srl value 24) #x00ff)
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(and (srl value 8) #xff00))
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(or SI
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(and (sll value 8) #x00ff0000)
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(and (sll value 24) #xff000000)))))
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(sll (and value #xff00) 8)
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(sll (and value #x00ff) 24)))))
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;; extract
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((value pc)
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(ext INT
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(or SI
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(or SI
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(and (srl value 24) #x000000ff)
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(and (srl value 8) #x0000ff00))
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(and (srl value 24) #x00ff)
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(and (srl value 8) #xff00))
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(or SI
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(and (sll value 8) #x00ff0000)
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(and (sll value 24) #xff000000)))))
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(sll (and value #xff00) 8)
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(sll (and value #x00ff) 24)))))
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)
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(dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT
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@ -746,7 +746,7 @@
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)
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(sequence () ; extract
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(set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff)
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(and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
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(sll (and (ifield f-dsp-64-u16) #xffff) 16)))
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)
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)
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@ -758,7 +758,7 @@
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)
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(sequence () ; extract
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(set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff)
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(and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
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(sll (and (ifield f-dsp-64-u16) #xffff) 16)))
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)
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)
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@ -827,7 +827,7 @@
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(set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3))
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)
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(sequence () ; extract
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(set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3)
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(set (ifield f-bitbase32-16-s11-unprefixed) (or (mul (ifield f-dsp-16-s8) 8)
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(ifield f-bitno32-unprefixed)))
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)
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)
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@ -885,7 +885,7 @@
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(set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3))
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)
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(sequence () ; extract
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(set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3)
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(set (ifield f-bitbase32-24-s11-prefixed) (or (mul (ifield f-dsp-24-s8) 8)
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(ifield f-bitno32-prefixed)))
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)
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)
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@ -913,7 +913,7 @@
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)
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(sequence () ; extract
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(set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
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(or (sll (ifield f-dsp-32-s8) 11)
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(or (mul (ifield f-dsp-32-s8) 2048)
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(ifield f-bitno32-prefixed))))
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)
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)
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@ -1075,7 +1075,7 @@
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(indices keyword "" (("r2r0" 0) ("r3r1" 1)))
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(get (index) (or SI
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(and (reg h-gr index) #xffff)
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(and (sll (reg h-gr (add index 2)) 16) #xffff0000)))
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(sll (and (reg h-gr (add index 2)) #xffff) 16)))
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(set (index newval) (sequence ()
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(set (reg h-gr index) (and newval #xffff))
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(set (reg h-gr (add index 2)) (srl newval 16)))))
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@ -1,3 +1,7 @@
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2020-01-30 Alan Modra <amodra@gmail.com>
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* m32c-ibld.c: Regenerate.
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2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
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* bpf-opc.c: Regenerate.
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@ -609,14 +609,14 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
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case M32C_OPERAND_BIT32RNPREFIXED :
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{
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long value = fields->f_dst32_rn_prefixed_QI;
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value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer);
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}
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break;
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case M32C_OPERAND_BIT32RNUNPREFIXED :
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{
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long value = fields->f_dst32_rn_unprefixed_QI;
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value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer);
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}
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break;
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@ -1191,7 +1191,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
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case M32C_OPERAND_DST32RNPREFIXEDQI :
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{
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long value = fields->f_dst32_rn_prefixed_QI;
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value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer);
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}
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break;
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@ -1212,7 +1212,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
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case M32C_OPERAND_DST32RNUNPREFIXEDQI :
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{
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long value = fields->f_dst32_rn_unprefixed_QI;
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value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer);
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}
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break;
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@ -1317,7 +1317,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
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case M32C_OPERAND_IMM_32_SI :
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{
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long value = fields->f_dsp_32_s32;
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value = EXTSISI (((((((((UINT) (value) >> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) << (8))) & (16711680))) | (((((value) << (24))) & (0xff000000)))))));
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value = EXTSISI (((((((((UINT) (value) >> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) & (65280))) << (8))) | (((((value) & (255))) << (24)))))));
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errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 32, 0, 32, 32, total_length, buffer);
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}
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break;
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@ -1603,7 +1603,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
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case M32C_OPERAND_SRC32RNPREFIXEDQI :
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{
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long value = fields->f_src32_rn_prefixed_QI;
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value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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errmsg = insert_normal (cd, value, 0, 0, 18, 2, 32, total_length, buffer);
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}
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break;
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@ -1624,7 +1624,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
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case M32C_OPERAND_SRC32RNUNPREFIXEDQI :
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{
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long value = fields->f_src32_rn_unprefixed_QI;
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value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1))));
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errmsg = insert_normal (cd, value, 0, 0, 10, 2, 32, total_length, buffer);
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}
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break;
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@ -1851,7 +1851,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
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length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_s8);
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if (length <= 0) break;
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{
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FLD (f_bitbase32_16_s11_unprefixed) = ((((FLD (f_dsp_16_s8)) << (3))) | (FLD (f_bitno32_unprefixed)));
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FLD (f_bitbase32_16_s11_unprefixed) = ((((FLD (f_dsp_16_s8)) * (8))) | (FLD (f_bitno32_unprefixed)));
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}
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}
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break;
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@ -1923,7 +1923,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
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length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_s8);
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if (length <= 0) break;
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{
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FLD (f_bitbase32_24_s11_prefixed) = ((((FLD (f_dsp_24_s8)) << (3))) | (FLD (f_bitno32_prefixed)));
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FLD (f_bitbase32_24_s11_prefixed) = ((((FLD (f_dsp_24_s8)) * (8))) | (FLD (f_bitno32_prefixed)));
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}
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}
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break;
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@ -1936,7 +1936,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
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length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_s8);
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if (length <= 0) break;
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{
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FLD (f_bitbase32_24_s19_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_s8)) << (11))) | (FLD (f_bitno32_prefixed)))));
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FLD (f_bitbase32_24_s19_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_s8)) * (2048))) | (FLD (f_bitno32_prefixed)))));
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}
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}
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break;
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@ -2480,7 +2480,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
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{
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long value;
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length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 32, 0, 32, 32, total_length, pc, & value);
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value = EXTSISI (((((((((UINT) (value) >> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) << (8))) & (16711680))) | (((((value) << (24))) & (0xff000000)))))));
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value = EXTSISI (((((((((UINT) (value) >> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) & (65280))) << (8))) | (((((value) & (255))) << (24)))))));
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fields->f_dsp_32_s32 = value;
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}
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break;
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@ -2539,7 +2539,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
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}
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if (length <= 0) break;
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{
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FLD (f_dsp_48_s32) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u16)) << (16))) & (0xffff0000))));
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FLD (f_dsp_48_s32) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u16)) & (65535))) << (16))));
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}
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}
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break;
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