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Add stack high register and stack low register for MicroBlaze 

hardware assisted stack protection, stores stack low / stack high limits
for detecting stack overflow / underflow

binutils/opcodes
          * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
          * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
binutils/gas
          * config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
binutils/gas
          * gas/microblaze/allinsn.s: Test use of SHR, SLR
          * gas/microblaze/allinsn.d: Likewise
This commit is contained in:
Michael Eager 2012-11-21 17:34:14 +00:00
parent e0f33b1fbf
commit 0db4b3260c
8 changed files with 64 additions and 0 deletions
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4
gas/ChangeLog
View File

@ -1,3 +1,7 @@
2012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com>
* config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
2012-11-20 H.J. Lu <hongjiu.lu@intel.com>
PR gas/14859

20
gas/config/tc-microblaze.c
View File

@ -531,6 +531,17 @@ parse_reg (char * s, unsigned * reg)
}
return s;
}
/* Stack protection registers. */
else if (strncasecmp (s, "rshr", 4) == 0)
{
*reg = REG_SHR;
return s + 4;
}
else if (strncasecmp (s, "rslr", 4) == 0)
{
*reg = REG_SLR;
return s + 4;
}
else
{
if (TOLOWER (s[0]) == 'r')
@ -760,6 +771,7 @@ check_spl_reg (unsigned * reg)
|| (*reg == REG_PID) || (*reg == REG_ZPR)
|| (*reg == REG_TLBX) || (*reg == REG_TLBLO)
|| (*reg == REG_TLBHI) || (*reg == REG_TLBSX)
|| (*reg == REG_SHR) || (*reg == REG_SLR)
|| (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM))
return TRUE;
@ -1280,6 +1292,10 @@ md_assemble (char * str)
immed = opcode->immval_mask | REG_TLBLO_MASK;
else if (reg2 == REG_TLBHI)
immed = opcode->immval_mask | REG_TLBHI_MASK;
else if (reg2 == REG_SHR)
immed = opcode->immval_mask | REG_SHR_MASK;
else if (reg2 == REG_SLR)
immed = opcode->immval_mask | REG_SLR_MASK;
else if (reg2 >= (REG_PVR+MIN_PVR_REGNUM) && reg2 <= (REG_PVR+MAX_PVR_REGNUM))
immed = opcode->immval_mask | REG_PVR_MASK | reg2;
else
@ -1331,6 +1347,10 @@ md_assemble (char * str)
immed = opcode->immval_mask | REG_TLBHI_MASK;
else if (reg1 == REG_TLBSX)
immed = opcode->immval_mask | REG_TLBSX_MASK;
else if (reg1 == REG_SHR)
immed = opcode->immval_mask | REG_SHR_MASK;
else if (reg1 == REG_SLR)
immed = opcode->immval_mask | REG_SLR_MASK;
else
as_fatal (_("invalid value for special purpose register"));
inst |= (reg2 << RA_LOW) & RA_MASK;

5
gas/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2012-11-21 David Holsgrove <david.holsgrove@xilinx.com>
* gas/microblaze/allinsn.s: Test use of SHR, SLR
* gas/microblaze/allinsn.d: Likewise
2012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/zarch-z9-109.d: Fix srstu opcode.

10
gas/testsuite/gas/microblaze/allinsn.d
View File

@ -31,3 +31,13 @@ Disassembly of section .text:
00000020 <sleep>:
20: ba020004 sleep
00000024 <regslr>:
24: b0000000 imm 0
28: 31600000 addik r11, r0, 0
2c: 940bc800 mts rslr, r11
00000030 <regshr>:
30: b0000000 imm 0
34: 31600000 addik r11, r0, 0
38: 940bc802 mts rshr, r11

10
gas/testsuite/gas/microblaze/allinsn.s
View File

@ -36,4 +36,14 @@ mbar:
.global sleep
sleep:
sleep
.text
.global regslr
regslr:
la r11,r0,r0
mts rslr,r11
.text
.global regshr
regshr:
la r11,r0,r0
mts rshr,r11

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com>
* microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
* microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
2012-11-20 Kirill Yukhin <kirill.yukhin@intel.com>
H.J. Lu <hongjiu.lu@intel.com>

6
opcodes/microblaze-dis.c
View File

@ -139,6 +139,12 @@ get_field_special (long instr, struct op_code_struct * op)
case REG_TLBSX_MASK :
strcpy (spr, "tlbsx");
break;
case REG_SHR_MASK :
strcpy (spr, "shr");
break;
case REG_SLR_MASK :
strcpy (spr, "slr");
break;
default :
if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
== REG_PVR_MASK)

4
opcodes/microblaze-opcm.h
View File

@ -79,6 +79,8 @@ enum microblaze_instr_type
#define REG_BTR_MASK 0x800b
#define REG_EDR_MASK 0x800d
#define REG_PVR_MASK 0xa000
#define REG_SLR_MASK 0x8800
#define REG_SHR_MASK 0x8802
#define REG_PID_MASK 0x9000
#define REG_ZPR_MASK 0x9001
@ -100,6 +102,8 @@ enum microblaze_instr_type
#define REG_FSR 39 /* FPU Status reg. */
#define REG_BTR 43 /* Branch Target reg. */
#define REG_EDR 45 /* Exception reg. */
#define REG_SHR 50 /* Stack High reg. */
#define REG_SLR 51 /* Stack Low reg. */
#define REG_PVR 40960 /* Program Verification reg. */
#define REG_PID 36864 /* MMU: Process ID reg. */