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* Removed short_hand field from opcode table and 

refactored assembler/disassember accordingly.
     Testsuite checkout OK.
This commit is contained in:
Sean Keys 2013-10-11 04:55:42 +00:00
parent bd80dc1a7c
commit 0e1c243401
7 changed files with 327 additions and 324 deletions
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4
gas/ChangeLog
View File

@ -1,3 +1,7 @@
2013-10-10 Sean Keys <skeys@ipdatasys.com>
* tc-xgate.c (xgate_find_match): Refactor opcode matching.
2013-10-10 Jan Beulich <jbeulich@suse.com>
* tc-i386-intel.c (i386_intel_simplify_register): Suppress base/index

153
gas/config/tc-xgate.c
View File

@ -33,6 +33,9 @@ const char line_separator_chars[] = "";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
/* Max opcodes per opcode handle. */
#define MAX_OPCODES 0x05
#define SIXTEENTH_BIT 0x8000
#define N_BITS_IN_WORD 16
#define MAX_NUM_OPERANDS 3
@ -101,7 +104,7 @@ static inline char *skip_whitespace (char *);
static void get_default_target (void);
static char *extract_word (char *, char *, int);
static struct xgate_opcode *xgate_find_match (struct xgate_opcode_handle *,
int, unsigned int);
int, s_operand [], unsigned int);
static int cmp_opcode (struct xgate_opcode *, struct xgate_opcode *);
static void xgate_print_table (void);
static unsigned int xgate_get_operands (char *, s_operand []);
@ -479,7 +482,7 @@ md_assemble (char *input_line)
/* Caller expects it to be returned as it was passed. */
char *saved_input_line = input_line;
char op_name[9] = { 0 };
unsigned int sh_format = 0;
unsigned int operandCount = 0;
char *p = 0;
s_operand new_operands[MAX_NUM_OPERANDS];
@ -501,10 +504,10 @@ md_assemble (char *input_line)
{
/* Parse operands so we can find the proper opcode bin. */
sh_format = xgate_get_operands(input_line, new_operands);
operandCount = xgate_get_operands (input_line, new_operands);
opcode = xgate_find_match (opcode_handle, opcode_handle->number_of_modes,
sh_format);
new_operands, operandCount);
if (!opcode)
{
@ -552,13 +555,11 @@ md_assemble (char *input_line)
}
else
{
sh_format = xgate_get_operands(input_line, new_operands);
macro_opcode
= xgate_find_match (opcode_handle,
opcode_handle->number_of_modes,
sh_format);
operandCount = xgate_get_operands(input_line, new_operands);
macro_opcode = xgate_find_match (opcode_handle,
opcode_handle->number_of_modes, new_operands,
operandCount);
xgate_scan_operands (macro_opcode, new_operands);
}
}
}
@ -905,8 +906,7 @@ cmp_opcode (struct xgate_opcode *op1, struct xgate_opcode *op2)
static struct xgate_opcode *
xgate_find_match (struct xgate_opcode_handle *opcode_handle,
int numberOfModes,
unsigned int sh_format)
int numberOfModes, s_operand oprs[], unsigned int operandCount)
{
int i;
@ -914,10 +914,84 @@ xgate_find_match (struct xgate_opcode_handle *opcode_handle,
return opcode_handle->opc0[0];
for (i = 0; i <= numberOfModes; i++)
if (opcode_handle->opc0[i]->sh_format & sh_format)
return opcode_handle->opc0[i];
{
switch (operandCount)
{
case 0:
if (!strcmp(opcode_handle->opc0[i]->constraints, XGATE_OP_INH))
return opcode_handle->opc0[i];
break;
case 1:
if (oprs[0].reg >= REG_R0 && oprs[0].reg <= REG_R7)
if (!strcmp(opcode_handle->opc0[i]->constraints, XGATE_OP_MON))
return opcode_handle->opc0[i];
if (!strcmp(opcode_handle->opc0[i]->constraints, XGATE_OP_DYA_MON))
return opcode_handle->opc0[i];
if (oprs[0].reg == REG_NONE)
if (!strcmp(opcode_handle->opc0[i]->constraints, XGATE_OP_IMM3))
return opcode_handle->opc0[i];
break;
case 2:
if (oprs[0].reg >= REG_R0 && oprs[0].reg <= REG_R7)
{
if (oprs[1].reg >= REG_R0 && oprs[1].reg <= REG_R7)
if (!strcmp(opcode_handle->opc0[i]->constraints, XGATE_OP_DYA))
return opcode_handle->opc0[i];
if (oprs[1].reg == REG_CCR)
if (!strcmp(opcode_handle->opc0[i]->constraints,
XGATE_OP_MON_R_C))
return opcode_handle->opc0[i];
if (oprs[1].reg == REG_PC)
if (!strcmp(opcode_handle->opc0[i]->constraints,
XGATE_OP_MON_R_P))
return opcode_handle->opc0[i];
if (oprs[1].reg == REG_NONE)
if (!strcmp(opcode_handle->opc0[i]->constraints, XGATE_OP_IMM16)
|| !strcmp(opcode_handle->opc0[i]->constraints, XGATE_OP_IMM8)
|| !strcmp(opcode_handle->opc0[i]->constraints, XGATE_OP_IMM4)
|| !strcmp(opcode_handle->opc0[i]->constraints,
XGATE_OP_IMM16mADD)
|| !strcmp(opcode_handle->opc0[i]->constraints,
XGATE_OP_IMM16mAND)
|| !strcmp(opcode_handle->opc0[i]->constraints,
XGATE_OP_IMM16mCPC)
|| !strcmp(opcode_handle->opc0[i]->constraints,
XGATE_OP_IMM16mSUB)
|| !strcmp(opcode_handle->opc0[i]->constraints,
XGATE_OP_IMM16mLDW))
return opcode_handle->opc0[i];
}
if (oprs[0].reg == REG_CCR)
if (!strcmp(opcode_handle->opc0[i]->constraints, XGATE_OP_MON_C_R))
return opcode_handle->opc0[i];
break;
case 3:
if (oprs[0].reg >= REG_R0 && oprs[0].reg <= REG_R7)
{
if (oprs[1].reg >= REG_R0 && oprs[1].reg <= REG_R7)
{
if (oprs[2].reg >= REG_R0 && oprs[2].reg <= REG_R7)
{
if (!strcmp(opcode_handle->opc0[i]->constraints,
XGATE_OP_IDR)
|| !strcmp(opcode_handle->opc0[i]->constraints,
XGATE_OP_TRI))
return opcode_handle->opc0[i];
}
return NULL;
if (oprs[2].reg == REG_NONE)
if (!strcmp(opcode_handle->opc0[i]->constraints,
XGATE_OP_IDO5))
return opcode_handle->opc0[i];
}
}
break;
default:
as_bad(_("unknown operand count"));
break;
}
}
return NULL ;
}
/* Because we are dealing with two different core that view the system
@ -948,7 +1022,7 @@ xgate_get_operands (char *line, s_operand oprs[])
/* If there are no operands, then it must be inherent. */
if (*line == 0 || *line == '\n' || *line == '\r')
return XG_INH;
return 0;
for (num_operands = 0; strlen (line) && (num_operands < MAX_NUM_OPERANDS);
num_operands++)
@ -973,51 +1047,9 @@ xgate_get_operands (char *line, s_operand oprs[])
line++;
}
}
if (num_operands > MAX_NUM_OPERANDS)
return 0;
switch (num_operands)
{
case 1:
if (oprs[0].reg >= REG_R0 && oprs[0].reg <= REG_R7)
return XG_R;
if (oprs[0].reg == REG_NONE)
return XG_I;
break;
case 2:
if (oprs[0].reg >= REG_R0 && oprs[0].reg <= REG_R7)
{
if (oprs[1].reg >= REG_R0 && oprs[1].reg <= REG_R7)
return XG_R_R;
if (oprs[1].reg == REG_CCR)
return XG_R_C;
if (oprs[1].reg == REG_PC)
return XG_R_P;
if (oprs[1].reg == REG_NONE)
return XG_R_I;
}
if (oprs[0].reg == REG_CCR)
return XG_C_R;
break;
case 3:
if (oprs[0].reg >= REG_R0 && oprs[0].reg <= REG_R7)
{
if (oprs[1].reg >= REG_R0 && oprs[1].reg <= REG_R7)
{
if (oprs[2].reg >= REG_R0 && oprs[2].reg <= REG_R7)
return XG_R_R_R;
if (oprs[2].reg >= REG_NONE)
return XG_R_R_I;
}
}
break;
default:
as_bad (_("unknown operand format"));
break;
}
return 0;
return num_operands;
}
/* reg_name_search() finds the register number given its name.
@ -1158,7 +1190,8 @@ xgate_scan_operands (struct xgate_opcode *opcode, s_operand oprs[])
{
bfd_putl16 (bin, frag);
}
else if ((opcode->sh_format & XG_PCREL))
else if ( !strcmp (opcode->constraints, XGATE_OP_REL9)
|| !strcmp (opcode->constraints, XGATE_OP_REL10))
{
/* Write our data to a frag for further processing. */
bfd_putl16 (opcode->bin_opcode, frag);

5
include/ChangeLog
View File

@ -1,3 +1,8 @@
2013-10-10 Sean Keys <skeys@ipdatasys.com>
* xgate.h : Cleanup after opcode
table modification..
2013-08-20 Alan Modra <amodra@gmail.com>
* floatformat.h (floatformat_ibm_long_double): Delete.

52
include/opcode/xgate.h
View File

@ -46,38 +46,24 @@
#define XGATE_CYCLE_A 0x40
#define XGATE_CYCLE_f 0x80
/* Opcode format abbreviations. */
#define XG_INH 0x0001 /* Inherent. */
#define XG_I 0x0002 /* 3-bit immediate address. */
#define XG_R_I 0x0004 /* Register followed by 4/8-bit immediate value. */
#define XG_R_R 0x0008 /* Register followed by a register. */
#define XG_R_R_R 0x0010 /* Register followed by two registers. */
#define XG_R 0x0020 /* Single register. */
#define XG_PC 0x0040 /* PC relative 10 or 11 bit. */
#define XG_R_C 0x0080 /* General register followed by ccr register. */
#define XG_C_R 0x0100 /* CCR register followed by a general register. */
#define XG_R_P 0x0200 /* General register followed by pc register. */
#define XG_R_R_I 0x0400 /* Two general registers followed by an immediate value. */
#define XG_PCREL 0x0800 /* Immediate value that is relative to the current pc. */
/* XGATE operand formats as stored in the XGATE_opcode table.
They are only used by GAS to recognize operands. */
#define XGATE_OP_INH ""
#define XGATE_OP_TRI "r,r,r"
#define XGATE_OP_DYA "r,r"
#define XGATE_OP_IMM16 "r,if"
#define XGATE_OP_IMM8 "r,i8"
#define XGATE_OP_IMM4 "r,i4"
#define XGATE_OP_IMM3 "i3"
#define XGATE_OP_MON "r"
#define XGATE_OP_MON_R_C "r,c"
#define XGATE_OP_MON_C_R "c,r"
#define XGATE_OP_MON_R_P "r,p"
#define XGATE_OP_IDR "r,r,+"
#define XGATE_OP_IDO5 "r,r,i5"
#define XGATE_OP_REL9 "b9"
#define XGATE_OP_REL10 "ba"
#define XGATE_OP_DYA_MON "=r"
#define XGATE_OP_INH "" /* Inherent. */
#define XGATE_OP_TRI "r,r,r" /* Register followed by two registers. */
#define XGATE_OP_DYA "r,r" /* Register followed by a register. */
#define XGATE_OP_IMM16 "r,if" /* Register followed by 16-bit value. */
#define XGATE_OP_IMM8 "r,i8" /* Register followed by 8-bit value. */
#define XGATE_OP_IMM4 "r,i4" /* Register followed by 4-bit value. */
#define XGATE_OP_IMM3 "i3" /* Register followed by 3-bit value. */
#define XGATE_OP_MON "r" /* Single register. */
#define XGATE_OP_MON_R_C "r,c" /* General register followed by ccr register. */
#define XGATE_OP_MON_C_R "c,r" /* CCR register followed by a general register. */
#define XGATE_OP_MON_R_P "r,p" /* General register followed by pc register. */
#define XGATE_OP_IDR "r,r,+" /* Three registers with the third having a -/+ directive. */
#define XGATE_OP_IDO5 "r,r,i5" /* Two general registers followed by an immediate value. */
#define XGATE_OP_REL9 "b9" /* 9-bit value that is relative to the current pc. */
#define XGATE_OP_REL10 "ba" /* 10-bit value that is relative to the current pc. */
#define XGATE_OP_DYA_MON "=r"
/* Macro definitions. */
#define XGATE_OP_IMM16mADD "r,if; addl addh"
#define XGATE_OP_IMM16mAND "r,if; andl andh"
@ -90,18 +76,12 @@
#define XGATE_V2 0x2
#define XGATE_V3 0x4
/* Max opcodes per opcode handle. */
#define MAX_OPCODES 0x05
#define MAX_DETECT_CHARS 0x10
/* The opcode table definitions. */
struct xgate_opcode
{
char * name; /* Op-code name. */
char * constraints; /* Constraint chars. */
char * format; /* Bit definitions. */
unsigned int sh_format; /* Shorthand format mask. */
unsigned int size; /* Opcode size in bytes. */
unsigned int bin_opcode; /* Binary opcode with operands masked off. */
unsigned char cycles_min; /* Minimum cpu cycles needed. */

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2013-10-10 Sean Keys <skeys@ipdatasys.com>
* xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
table.
* xgate-dis.c (print_insn): Refactor to work with table change.
2013-10-10 Roland McGrath <mcgrathr@google.com>
* i386-dis.c (oappend_maybe_intel): New function.

228
opcodes/xgate-dis.c
View File

@ -124,83 +124,69 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info)
(*info->fprintf_func)(info->stream, "%s", decodePTR->opcodePTR->name);
/* First we compare the shorthand format of the constraints. If we
still are unable to pinpoint the operands
we analyze the opcodes constraint string. */
switch (decodePTR->opcodePTR->sh_format)
{
case XG_R_C:
(*info->fprintf_func)(info->stream, " R%x, CCR",
(raw_code >> 8) & 0x7);
break;
case XG_C_R:
(*info->fprintf_func)(info->stream, " CCR, R%x",
(raw_code >> 8) & 0x7);
break;
case XG_R_P:
(*info->fprintf_func)(info->stream, " R%x, PC",
(raw_code >> 8) & 0x7);
break;
case XG_INH:
break;
case XG_R_R_R:
if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_TRI))
{
(*info->fprintf_func)(info->stream, " R%x, R%x, R%x",
(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
(raw_code >> 2) & 0x7);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IDR))
{
if (raw_code & 0x01)
{
(*info->fprintf_func)(info->stream, " R%x, (R%x, R%x+)",
(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
(raw_code >> 2) & 0x7);
}
else if (raw_code & 0x02)
{
(*info->fprintf_func)(info->stream, " R%x, (R%x, -R%x)",
(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
(raw_code >> 2) & 0x7);
}
else
{
(*info->fprintf_func)(info->stream, " R%x, (R%x, R%x)",
(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
(raw_code >> 2) & 0x7);
}
}
else
{
(*info->fprintf_func)(info->stream, " unhandled mode %s",
decodePTR->opcodePTR->constraints);
}
break;
case XG_R_R:
if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_DYA))
{
operandOne = ripBits (&operMaskReg, 3, opcodePTR, raw_code);
operandTwo = ripBits (&operMaskReg, 3, opcodePTR, raw_code);
(*info->fprintf_func)(info->stream, " R%x, R%x", operandOne,
operandTwo);
}
else
{
(*info->fprintf_func)(info->stream, " unhandled mode %s",
opcodePTR->constraints);
}
break;
case XG_R_R_I:
(*info->fprintf_func)(info->stream, " R%x, (R%x, #0x%x)",
(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7, raw_code & 0x1f);
break;
case XG_R:
operandOne = ripBits (&operMaskReg, 3, decodePTR->opcodePTR,
raw_code);
(*info->fprintf_func)(info->stream, " R%x", operandOne);
break;
case XG_I | XG_PCREL:
if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_REL9))
still are unable to pinpoint the operands
we analyze the opcodes constraint string. */
if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_MON_R_C))
{
(*info->fprintf_func)(info->stream, " R%x, CCR",
(raw_code >> 8) & 0x7);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_MON_C_R))
{
(*info->fprintf_func)(info->stream, " CCR, R%x",
(raw_code >> 8) & 0x7);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_MON_R_P))
{
(*info->fprintf_func)(info->stream, " R%x, PC",
(raw_code >> 8) & 0x7);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_TRI))
{
(*info->fprintf_func)(info->stream, " R%x, R%x, R%x",
(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
(raw_code >> 2) & 0x7);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IDR))
{
if (raw_code & 0x01)
{
(*info->fprintf_func)(info->stream, " R%x, (R%x, R%x+)",
(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
(raw_code >> 2) & 0x7);
}
else if (raw_code & 0x02)
{
(*info->fprintf_func)(info->stream, " R%x, (R%x, -R%x)",
(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
(raw_code >> 2) & 0x7);
}
else
{
(*info->fprintf_func)(info->stream, " R%x, (R%x, R%x)",
(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
(raw_code >> 2) & 0x7);
}
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_DYA))
{
operandOne = ripBits (&operMaskReg, 3, opcodePTR, raw_code);
operandTwo = ripBits (&operMaskReg, 3, opcodePTR, raw_code);
( *info->fprintf_func)(info->stream, " R%x, R%x", operandOne,
operandTwo);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IDO5))
{
(*info->fprintf_func)(info->stream, " R%x, (R%x, #0x%x)",
(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7, raw_code & 0x1f);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_MON))
{
operandOne = ripBits (&operMaskReg, 3, decodePTR->opcodePTR,
raw_code);
(*info->fprintf_func)(info->stream, " R%x", operandOne);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_REL9))
{
/* If address is negative handle it accordingly. */
if (raw_code & XGATE_NINE_SIGNBIT)
@ -215,10 +201,10 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info)
relAddr = raw_code & 0xff;
relAddr = (relAddr << 1) + 2;
}
(*info->fprintf_func)(info->stream, " *%d", relAddr);
(*info->fprintf_func)(info->stream, " Abs* 0x");
(*info->print_address_func)(memaddr + relAddr, info);
}
(*info->fprintf_func)(info->stream, " *%d", relAddr);
(*info->fprintf_func)(info->stream, " Abs* 0x");
(*info->print_address_func)(memaddr + relAddr, info);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_REL10))
{
/* If address is negative handle it accordingly. */
@ -238,54 +224,44 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info)
(*info->fprintf_func)(info->stream, " Abs* 0x");
(*info->print_address_func)(memaddr + relAddr, info);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IMM4))
{
(*info->fprintf_func)(info->stream, " R%x, #0x%02x",
(raw_code >> 8) & 0x7, (raw_code >> 4) & 0xF);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IMM8))
{
if (macro_search (decodePTR->opcodePTR->name, previousOpName) &&
previousOpName[0])
{
absAddress = (0xFF & raw_code) << 8;
absAddress |= perviousBin & 0xFF;
(*info->fprintf_func)(info->stream, " R%x, #0x%02x Abs* 0x",
(raw_code >> 8) & 0x7, raw_code & 0xff);
(*info->print_address_func)(absAddress, info);
previousOpName[0] = 0;
}
else
{
strcpy (previousOpName, decodePTR->opcodePTR->name);
(*info->fprintf_func)(info->stream, " R%x, #0x%02x",
(raw_code >> 8) & 0x7, raw_code & 0xff);
}
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IMM3))
{
(*info->fprintf_func)(info->stream, " #0x%x",
(raw_code >> 8) & 0x7);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_INH))
{
//
}
else
{
(*info->fprintf_func)(info->stream,
" Can't disassemble for mode) %s",
decodePTR->opcodePTR->constraints);
(*info->fprintf_func)(info->stream, " unhandled mode %s",
opcodePTR->constraints);
}
break;
case XG_R_I:
if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IMM4))
{
(*info->fprintf_func)(info->stream, " R%x, #0x%02x",
(raw_code >> 8) & 0x7, (raw_code >> 4) & 0xF);
}
else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IMM8))
{
if (macro_search (decodePTR->opcodePTR->name, previousOpName) &&
previousOpName[0])
{
absAddress = (0xFF & raw_code) << 8;
absAddress |= perviousBin & 0xFF;
(*info->fprintf_func)(info->stream, " R%x, #0x%02x Abs* 0x",
(raw_code >> 8) & 0x7, raw_code & 0xff);
(*info->print_address_func)(absAddress, info);
previousOpName[0] = 0;
}
else
{
strcpy (previousOpName, decodePTR->opcodePTR->name);
(*info->fprintf_func)(info->stream, " R%x, #0x%02x",
(raw_code >> 8) & 0x7, raw_code & 0xff);
}
}
else
{
(*info->fprintf_func)(info->stream,
" Can't disassemble for mode %s",
decodePTR->opcodePTR->constraints);
}
break;
case XG_I:
(*info->fprintf_func)(info->stream, " #0x%x",
(raw_code >> 8) & 0x7);
break;
default:
(*info->fprintf_func)(info->stream, "address mode not found\t %x",
opcodePTR->bin_opcode);
break;
}
perviousBin = raw_code;
}
else

203
opcodes/xgate-opc.c
View File

@ -86,7 +86,7 @@
#define OP_IDO5 XGATE_OP_IDO5
#define OP_REL9 XGATE_OP_REL9
#define OP_REL10 XGATE_OP_REL10
#define OP_DM XGATE_OP_DYA_MON
#define OP_DM XGATE_OP_DYA_MON
/* macro operand modes */
#define OP_mADD XGATE_OP_IMM16mADD
#define OP_mAND XGATE_OP_IMM16mAND
@ -95,110 +95,109 @@
#define OP_mSUB XGATE_OP_IMM16mSUB
#define ALL XGATE_V1|XGATE_V2|XGATE_V3
#define XG_IP XG_I|XG_PCREL
const struct xgate_opcode xgate_opcodes[] = {
/* Name -+ +-- CPU
Constraints --+ +------------ CCR changes
Format ----------------+ +---------------- Max # cycles
Short Hand Format-------------------------+ +------------------- Min # cycles
Size -----------------------------------------------+ +-------------------------- Opcode */
{ "adc", OP_TRI, "00011rrrrrrrrr11", XG_R_R_R, 2, 0x1803, 1, 1, CHG_NZVC, ALL},
{ "add", OP_TRI, "00011rrrrrrrrr10", XG_R_R_R, 2, 0x1802, 1, 1, CHG_NZVC, ALL},
{ "addh", OP_IMM8, "11101rrriiiiiiii", XG_R_I, 2, 0xE800, 1, 1, CHG_NZVC, ALL},
{ "addl", OP_IMM8, "11100rrriiiiiiii", XG_R_I, 2, 0xE000, 1, 1, CHG_NZVC, ALL},
{ "and", OP_TRI, "00010rrrrrrrrr00", XG_R_R_R, 2, 0x1000, 1, 1, CHG_NZV, ALL},
{ "andh", OP_IMM8, "10001rrriiiiiiii", XG_R_I, 2, 0x8800, 1, 1, CHG_NZV, ALL},
{ "andl", OP_IMM8, "10000rrriiiiiiii", XG_R_I, 2, 0x8000, 1, 1, CHG_NZV, ALL},
{ "asr", OP_IMM4, "00001rrriiii1001", XG_R_I, 2, 0x0809, 1, 1, CHG_NZVC, ALL},
{ "asr", OP_DYA, "00001rrrrrr10001", XG_R_R, 2, 0x0811, 1, 1, CHG_NZVC, ALL},
{ "bcc", OP_REL9, "0010000iiiiiiiii", XG_IP, 2, 0x2000, 1, 2, CHG_NONE, ALL},
{ "bcs", OP_REL9, "0010001iiiiiiiii", XG_IP, 2, 0x2200, 1, 2, CHG_NONE, ALL},
{ "beq", OP_REL9, "0010011iiiiiiiii", XG_IP, 2, 0x2600, 1, 2, CHG_NONE, ALL},
{ "bfext", OP_TRI, "01100rrrrrrrrr11", XG_R_R_R, 2, 0x6003, 1, 1, CHG_NZV, ALL},
{ "bffo", OP_DYA, "00001rrrrrr10000", XG_R_R, 2, 0x0810, 1, 1, CHG_NZVC, ALL},
{ "bfins", OP_TRI, "01101rrrrrrrrr11", XG_R_R_R, 2, 0x6803, 1, 1, CHG_NZV, ALL},
{"bfinsi", OP_TRI, "01110rrrrrrrrr11", XG_R_R_R, 2, 0x7003, 1, 1, CHG_NZV, ALL},
{"bfinsx", OP_TRI, "01111rrrrrrrrr11", XG_R_R_R, 2, 0x7803, 1, 1, CHG_NZV, ALL},
{ "bge", OP_REL9, "0011010iiiiiiiii", XG_IP, 2, 0x3400, 1, 2, CHG_NONE, ALL},
{ "bgt", OP_REL9, "0011100iiiiiiiii", XG_IP, 2, 0x3800, 1, 2, CHG_NONE, ALL},
{ "bhi", OP_REL9, "0011000iiiiiiiii", XG_IP, 2, 0x3000, 1, 2, CHG_NONE, ALL},
{ "bith", OP_IMM8, "10011rrriiiiiiii", XG_R_I, 2, 0x9800, 1, 1, CHG_NZV, ALL},
{ "bitl", OP_IMM8, "10010rrriiiiiiii", XG_R_I, 2, 0x9000, 1, 1, CHG_NZV, ALL},
{ "ble", OP_REL9, "0011101iiiiiiiii", XG_IP, 2, 0x3A00, 1, 2, CHG_NONE, ALL},
{ "bls", OP_REL9, "0011001iiiiiiiii", XG_IP, 2, 0x3200, 1, 2, CHG_NONE, ALL},
{ "blt", OP_REL9, "0011011iiiiiiiii", XG_IP, 2, 0x3600, 1, 2, CHG_NONE, ALL},
{ "bmi", OP_REL9, "0010101iiiiiiiii", XG_IP, 2, 0x2A00, 1, 2, CHG_NONE, ALL},
{ "bne", OP_REL9, "0010010iiiiiiiii", XG_IP, 2, 0x2400, 1, 2, CHG_NONE, ALL},
{ "bpl", OP_REL9, "0010100iiiiiiiii", XG_IP, 2, 0x2800, 1, 2, CHG_NONE, ALL},
{ "bra", OP_REL10, "001111iiiiiiiiii", XG_IP, 2, 0x3C00, 2, 2, CHG_NONE, ALL},
{ "brk", OP_INH, "0000000000000000", XG_INH, 2, 0x0000, 1, 1, CHG_NONE, ALL},
{ "bvc", OP_REL9, "0010110iiiiiiiii", XG_IP, 2, 0x2C00, 1, 2, CHG_NONE, ALL},
{ "bvs", OP_REL9, "0010111iiiiiiiii", XG_IP, 2, 0x2E00, 1, 2, CHG_NONE, ALL},
{ "cmpl", OP_IMM8, "11010rrriiiiiiii", XG_R_I, 2, 0xD000, 1, 1, CHG_NZVC, ALL},
{ "cpch", OP_IMM8, "11011rrriiiiiiii", XG_R_I, 2, 0xD800, 1, 1, CHG_NZVC, ALL},
{ "csem", OP_IMM3, "00000iii11110000", XG_I , 2, 0x00F0, 1, 1, CHG_NONE, ALL},
{ "csem", OP_MON, "00000rrr11110001", XG_R, 2, 0x00F1, 1, 1, CHG_NONE, ALL},
{ "csl", OP_IMM4, "00001rrriiii1010", XG_R_I, 2, 0x080A, 1, 1, CHG_NZVC, ALL},
{ "csl", OP_DYA, "00001rrrrrr10010", XG_R_R, 2, 0x0812, 1, 1, CHG_NZVC, ALL},
{ "csr", OP_IMM4, "00001rrriiii1011", XG_R_I, 2, 0x080B, 1, 1, CHG_NZVC, ALL},
{ "csr", OP_DYA, "00001rrrrrr10011", XG_R_R, 2, 0x0813, 1, 1, CHG_NZVC, ALL},
{ "jal", OP_MON, "00000rrr11110110", XG_R, 2, 0x00F6, 2, 2, CHG_NONE, ALL},
{ "ldb", OP_IDO5, "01000rrrrrriiiii", XG_R_R_I, 2, 0x4000, 2, 2, CHG_NONE, ALL},
{ "ldb", OP_IDR, "01100rrrrrrrrrrr", XG_R_R_R, 2, 0x6000, 2, 2, CHG_NONE, ALL},
{ "ldh", OP_IMM8, "11111rrriiiiiiii", XG_R_I, 2, 0xF800, 1, 1, CHG_NONE, ALL},
{ "ldl", OP_IMM8, "11110rrriiiiiiii", XG_R_I, 2, 0xF000, 1, 1, CHG_NONE, ALL},
{ "ldw", OP_IDO5, "01001rrrrrriiiii", XG_R_R_I, 2, 0x4800, 2, 2, CHG_NONE, ALL},
{ "ldw", OP_IDR, "01101rrrrrrrrrrr", XG_R_R_R, 2, 0x6800, 2, 2, CHG_NONE, ALL},
{ "lsl", OP_IMM4, "00001rrriiii1100", XG_R_I, 2, 0x080C, 1, 1, CHG_NZVC, ALL},
{ "lsl", OP_DYA, "00001rrrrrr10100", XG_R_R, 2, 0x0814, 1, 1, CHG_NZVC, ALL},
{ "lsr", OP_IMM4, "00001rrriiii1101", XG_R_I, 2, 0x080D, 1, 1, CHG_NZVC, ALL},
{ "lsr", OP_DYA, "00001rrrrrr10101", XG_R_R, 2, 0x0815, 1, 1, CHG_NZVC, ALL},
{ "nop", OP_INH, "0000000100000000", XG_INH, 2, 0x0100, 1, 1, CHG_NONE, ALL},
{ "or", OP_TRI, "00010rrrrrrrrr10", XG_R_R_R, 2, 0x1002, 1, 1, CHG_NZV, ALL},
{ "orh", OP_IMM8, "10101rrriiiiiiii", XG_R_I, 2, 0xA800, 1, 1, CHG_NZV, ALL},
{ "orl", OP_IMM8, "10100rrriiiiiiii", XG_R_I, 2, 0xA000, 1, 1, CHG_NZV, ALL},
{ "par", OP_MON, "00000rrr11110101", XG_R, 2, 0x00F5, 1, 1, CHG_NZV, ALL},
{ "rol", OP_IMM4, "00001rrriiii1110", XG_R_I, 2, 0x080E, 1, 1, CHG_NZV, ALL},
{ "rol", OP_DYA, "00001rrrrrr10110", XG_R_R, 2, 0x0816, 1, 1, CHG_NZV, ALL},
{ "ror", OP_IMM4, "00001rrriiii1111", XG_R_I, 2, 0x080F, 1, 1, CHG_NZV, ALL},
{ "ror", OP_DYA, "00001rrrrrr10111", XG_R_R, 2, 0x0817, 1, 1, CHG_NZV, ALL},
{ "rts", OP_INH, "0000001000000000", XG_INH, 2, 0x0200, 2, 2, CHG_NONE, ALL},
{ "sbc", OP_TRI, "00011rrrrrrrrr01", XG_R_R_R, 2, 0x1801, 1, 1, CHG_NZV, ALL},
{ "ssem", OP_IMM3, "00000iii11110010", XG_I , 2, 0x00F2, 2, 2, CHG_C, ALL},
{ "ssem", OP_MON, "00000rrr11110011", XG_R, 2, 0x00F3, 2, 2, CHG_C, ALL},
{ "sex", OP_MON, "00000rrr11110100", XG_R, 2, 0x00F4, 1, 1, CHG_NZV, ALL},
{ "sif", OP_INH, "0000001100000000", XG_INH, 2, 0x0300, 2, 2, CHG_NONE, ALL},
{ "sif", OP_MON, "00000rrr11110111", XG_R, 2, 0x00F7, 2, 2, CHG_NONE, ALL},
{ "stb", OP_IDO5, "01010rrrrrriiiii", XG_R_R_I, 2, 0x5000, 2, 2, CHG_NONE, ALL},
{ "stb", OP_IDR, "01110rrrrrrrrrrr", XG_R_R_R, 2, 0x7000, 2, 2, CHG_NONE, ALL},
{ "stw", OP_IDO5, "01011rrrrrriiiii", XG_R_R_I, 2, 0x5800, 2, 2, CHG_NONE, ALL},
{ "stw", OP_IDR, "01111rrrrrrrrrrr", XG_R_R_R, 2, 0x7800, 2, 2, CHG_NONE, ALL},
{ "sub", OP_TRI, "00011rrrrrrrrr00", XG_R_R_R, 2, 0x1800, 1, 1, CHG_NZVC, ALL},
{ "subh", OP_IMM8, "11001rrriiiiiiii", XG_R_I, 2, 0xC800, 1, 1, CHG_NZVC, ALL},
{ "subl", OP_IMM8, "11000rrriiiiiiii", XG_R_I, 2, 0xC000, 1, 1, CHG_NZVC, ALL},
{ "tfr", OP_MON_R_C, "00000rrr11111000",XG_R_C, 2, 0x00F8, 1, 1, CHG_NONE, ALL},
{ "tfr", OP_MON_C_R, "00000rrr11111001",XG_C_R, 2, 0x00F9, 1, 1, CHG_NONE, ALL},
{ "tfr", OP_MON_R_P, "00000rrr11111010",XG_R_P, 2, 0x00FA, 1, 1, CHG_NONE, ALL},
{ "xnor", OP_TRI, "00010rrrrrrrrr11", XG_R_R_R, 2, 0x1003, 1, 1, CHG_NZV, ALL},
{ "xnorh", OP_IMM8, "10111rrriiiiiiii", XG_R_I, 2, 0xB800, 1, 1, CHG_NZV, ALL},
{ "xnorl", OP_IMM8, "10110rrriiiiiiii", XG_R_I, 2, 0xB000, 1, 1, CHG_NZV, ALL},
/* Name -+ +--- CPU
Constraints --+ +----------- CCR changes
Format -------+ +---------------- Max # cycles
+------------------- Min # cycles
Size -------------------------------------+ +-------------------------- Opcode */
{ "adc", OP_TRI, "00011rrrrrrrrr11", 2, 0x1803, 1, 1, CHG_NZVC, ALL},
{ "add", OP_TRI, "00011rrrrrrrrr10", 2, 0x1802, 1, 1, CHG_NZVC, ALL},
{ "addh", OP_IMM8, "11101rrriiiiiiii", 2, 0xE800, 1, 1, CHG_NZVC, ALL},
{ "addl", OP_IMM8, "11100rrriiiiiiii", 2, 0xE000, 1, 1, CHG_NZVC, ALL},
{ "and", OP_TRI, "00010rrrrrrrrr00", 2, 0x1000, 1, 1, CHG_NZV, ALL},
{ "andh", OP_IMM8, "10001rrriiiiiiii", 2, 0x8800, 1, 1, CHG_NZV, ALL},
{ "andl", OP_IMM8, "10000rrriiiiiiii", 2, 0x8000, 1, 1, CHG_NZV, ALL},
{ "asr", OP_IMM4, "00001rrriiii1001", 2, 0x0809, 1, 1, CHG_NZVC, ALL},
{ "asr", OP_DYA, "00001rrrrrr10001", 2, 0x0811, 1, 1, CHG_NZVC, ALL},
{ "bcc", OP_REL9, "0010000iiiiiiiii", 2, 0x2000, 1, 2, CHG_NONE, ALL},
{ "bcs", OP_REL9, "0010001iiiiiiiii", 2, 0x2200, 1, 2, CHG_NONE, ALL},
{ "beq", OP_REL9, "0010011iiiiiiiii", 2, 0x2600, 1, 2, CHG_NONE, ALL},
{ "bfext", OP_TRI, "01100rrrrrrrrr11", 2, 0x6003, 1, 1, CHG_NZV, ALL},
{ "bffo", OP_DYA, "00001rrrrrr10000", 2, 0x0810, 1, 1, CHG_NZVC, ALL},
{ "bfins", OP_TRI, "01101rrrrrrrrr11", 2, 0x6803, 1, 1, CHG_NZV, ALL},
{"bfinsi", OP_TRI, "01110rrrrrrrrr11", 2, 0x7003, 1, 1, CHG_NZV, ALL},
{"bfinsx", OP_TRI, "01111rrrrrrrrr11", 2, 0x7803, 1, 1, CHG_NZV, ALL},
{ "bge", OP_REL9, "0011010iiiiiiiii", 2, 0x3400, 1, 2, CHG_NONE, ALL},
{ "bgt", OP_REL9, "0011100iiiiiiiii", 2, 0x3800, 1, 2, CHG_NONE, ALL},
{ "bhi", OP_REL9, "0011000iiiiiiiii", 2, 0x3000, 1, 2, CHG_NONE, ALL},
{ "bith", OP_IMM8, "10011rrriiiiiiii", 2, 0x9800, 1, 1, CHG_NZV, ALL},
{ "bitl", OP_IMM8, "10010rrriiiiiiii", 2, 0x9000, 1, 1, CHG_NZV, ALL},
{ "ble", OP_REL9, "0011101iiiiiiiii", 2, 0x3A00, 1, 2, CHG_NONE, ALL},
{ "bls", OP_REL9, "0011001iiiiiiiii", 2, 0x3200, 1, 2, CHG_NONE, ALL},
{ "blt", OP_REL9, "0011011iiiiiiiii", 2, 0x3600, 1, 2, CHG_NONE, ALL},
{ "bmi", OP_REL9, "0010101iiiiiiiii", 2, 0x2A00, 1, 2, CHG_NONE, ALL},
{ "bne", OP_REL9, "0010010iiiiiiiii", 2, 0x2400, 1, 2, CHG_NONE, ALL},
{ "bpl", OP_REL9, "0010100iiiiiiiii", 2, 0x2800, 1, 2, CHG_NONE, ALL},
{ "bra", OP_REL10, "001111iiiiiiiiii", 2, 0x3C00, 2, 2, CHG_NONE, ALL},
{ "brk", OP_INH, "0000000000000000", 2, 0x0000, 1, 1, CHG_NONE, ALL},
{ "bvc", OP_REL9, "0010110iiiiiiiii", 2, 0x2C00, 1, 2, CHG_NONE, ALL},
{ "bvs", OP_REL9, "0010111iiiiiiiii", 2, 0x2E00, 1, 2, CHG_NONE, ALL},
{ "cmpl", OP_IMM8, "11010rrriiiiiiii", 2, 0xD000, 1, 1, CHG_NZVC, ALL},
{ "cpch", OP_IMM8, "11011rrriiiiiiii", 2, 0xD800, 1, 1, CHG_NZVC, ALL},
{ "csem", OP_IMM3, "00000iii11110000", 2, 0x00F0, 1, 1, CHG_NONE, ALL},
{ "csem", OP_MON, "00000rrr11110001", 2, 0x00F1, 1, 1, CHG_NONE, ALL},
{ "csl", OP_IMM4, "00001rrriiii1010", 2, 0x080A, 1, 1, CHG_NZVC, ALL},
{ "csl", OP_DYA, "00001rrrrrr10010", 2, 0x0812, 1, 1, CHG_NZVC, ALL},
{ "csr", OP_IMM4, "00001rrriiii1011", 2, 0x080B, 1, 1, CHG_NZVC, ALL},
{ "csr", OP_DYA, "00001rrrrrr10011", 2, 0x0813, 1, 1, CHG_NZVC, ALL},
{ "jal", OP_MON, "00000rrr11110110", 2, 0x00F6, 2, 2, CHG_NONE, ALL},
{ "ldb", OP_IDO5, "01000rrrrrriiiii", 2, 0x4000, 2, 2, CHG_NONE, ALL},
{ "ldb", OP_IDR, "01100rrrrrrrrrrr", 2, 0x6000, 2, 2, CHG_NONE, ALL},
{ "ldh", OP_IMM8, "11111rrriiiiiiii", 2, 0xF800, 1, 1, CHG_NONE, ALL},
{ "ldl", OP_IMM8, "11110rrriiiiiiii", 2, 0xF000, 1, 1, CHG_NONE, ALL},
{ "ldw", OP_IDO5, "01001rrrrrriiiii", 2, 0x4800, 2, 2, CHG_NONE, ALL},
{ "ldw", OP_IDR, "01101rrrrrrrrrrr", 2, 0x6800, 2, 2, CHG_NONE, ALL},
{ "lsl", OP_IMM4, "00001rrriiii1100", 2, 0x080C, 1, 1, CHG_NZVC, ALL},
{ "lsl", OP_DYA, "00001rrrrrr10100", 2, 0x0814, 1, 1, CHG_NZVC, ALL},
{ "lsr", OP_IMM4, "00001rrriiii1101", 2, 0x080D, 1, 1, CHG_NZVC, ALL},
{ "lsr", OP_DYA, "00001rrrrrr10101", 2, 0x0815, 1, 1, CHG_NZVC, ALL},
{ "nop", OP_INH, "0000000100000000", 2, 0x0100, 1, 1, CHG_NONE, ALL},
{ "or", OP_TRI, "00010rrrrrrrrr10", 2, 0x1002, 1, 1, CHG_NZV, ALL},
{ "orh", OP_IMM8, "10101rrriiiiiiii", 2, 0xA800, 1, 1, CHG_NZV, ALL},
{ "orl", OP_IMM8, "10100rrriiiiiiii", 2, 0xA000, 1, 1, CHG_NZV, ALL},
{ "par", OP_MON, "00000rrr11110101", 2, 0x00F5, 1, 1, CHG_NZV, ALL},
{ "rol", OP_IMM4, "00001rrriiii1110", 2, 0x080E, 1, 1, CHG_NZV, ALL},
{ "rol", OP_DYA, "00001rrrrrr10110", 2, 0x0816, 1, 1, CHG_NZV, ALL},
{ "ror", OP_IMM4, "00001rrriiii1111", 2, 0x080F, 1, 1, CHG_NZV, ALL},
{ "ror", OP_DYA, "00001rrrrrr10111", 2, 0x0817, 1, 1, CHG_NZV, ALL},
{ "rts", OP_INH, "0000001000000000", 2, 0x0200, 2, 2, CHG_NONE, ALL},
{ "sbc", OP_TRI, "00011rrrrrrrrr01", 2, 0x1801, 1, 1, CHG_NZV, ALL},
{ "ssem", OP_IMM3, "00000iii11110010", 2, 0x00F2, 2, 2, CHG_C, ALL},
{ "ssem", OP_MON, "00000rrr11110011", 2, 0x00F3, 2, 2, CHG_C, ALL},
{ "sex", OP_MON, "00000rrr11110100", 2, 0x00F4, 1, 1, CHG_NZV, ALL},
{ "sif", OP_INH, "0000001100000000", 2, 0x0300, 2, 2, CHG_NONE, ALL},
{ "sif", OP_MON, "00000rrr11110111", 2, 0x00F7, 2, 2, CHG_NONE, ALL},
{ "stb", OP_IDO5, "01010rrrrrriiiii", 2, 0x5000, 2, 2, CHG_NONE, ALL},
{ "stb", OP_IDR, "01110rrrrrrrrrrr", 2, 0x7000, 2, 2, CHG_NONE, ALL},
{ "stw", OP_IDO5, "01011rrrrrriiiii", 2, 0x5800, 2, 2, CHG_NONE, ALL},
{ "stw", OP_IDR, "01111rrrrrrrrrrr", 2, 0x7800, 2, 2, CHG_NONE, ALL},
{ "sub", OP_TRI, "00011rrrrrrrrr00", 2, 0x1800, 1, 1, CHG_NZVC, ALL},
{ "subh", OP_IMM8, "11001rrriiiiiiii", 2, 0xC800, 1, 1, CHG_NZVC, ALL},
{ "subl", OP_IMM8, "11000rrriiiiiiii", 2, 0xC000, 1, 1, CHG_NZVC, ALL},
{ "tfr", OP_MON_R_C, "00000rrr11111000", 2, 0x00F8, 1, 1, CHG_NONE, ALL},
{ "tfr", OP_MON_C_R, "00000rrr11111001", 2, 0x00F9, 1, 1, CHG_NONE, ALL},
{ "tfr", OP_MON_R_P, "00000rrr11111010", 2, 0x00FA, 1, 1, CHG_NONE, ALL},
{ "xnor", OP_TRI, "00010rrrrrrrrr11", 2, 0x1003, 1, 1, CHG_NZV, ALL},
{ "xnorh", OP_IMM8, "10111rrriiiiiiii", 2, 0xB800, 1, 1, CHG_NZV, ALL},
{ "xnorl", OP_IMM8, "10110rrriiiiiiii", 2, 0xB000, 1, 1, CHG_NZV, ALL},
/* macro and alias codes */
{ "add", OP_mADD, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
{ "and", OP_mAND, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
{ "bhs", OP_REL9, "0010000iiiiiiiii", XG_IP, 2, 0x2000, 0, 0, CHG_NONE, ALL},
{ "blo", OP_REL9, "0010001iiiiiiiii", XG_IP, 2, 0x2200, 0, 0, CHG_NONE, ALL},
{ "cmp", OP_mCPC, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
{ "cmp", OP_DYA, "00011sssrrrrrr00", XG_R_R, 2, 0x1800, 0, 0, CHG_NZVC, ALL},
{ "com", OP_DM, "00010rrrsssrrr11", XG_R, 2, 0x1003, 0, 0, CHG_NZVC, ALL},
{ "com", OP_DYA, "00010rrrsssrrr11", XG_R_R, 2, 0x1003, 0, 0, CHG_NZV, ALL},
{ "cpc", OP_DYA, "00011sssrrrrrr01", XG_R_R, 2, 0x1801, 0, 0, CHG_NZVC, ALL},
{ "ldd", OP_mLDW, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
{ "ldw", OP_mLDW, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
{ "mov", OP_DYA, "00010rrrsssrrr10", XG_R_R, 2, 0x1002, 0, 0, CHG_NZVC, ALL},
{ "neg", OP_DYA, "00011rrrsssrrr00", XG_R_R, 2, 0x1800, 0, 0, CHG_NZVC, ALL},
{ "sub", OP_mSUB, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
{ "tst", OP_MON, "00011sssrrrsss00", XG_R, 2, 0x1800, 0, 0, CHG_NZV, ALL}
{ "add", OP_mADD, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
{ "and", OP_mAND, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
{ "bhs", OP_REL9, "0010000iiiiiiiii", 2, 0x2000, 0, 0, CHG_NONE, ALL},
{ "blo", OP_REL9, "0010001iiiiiiiii", 2, 0x2200, 0, 0, CHG_NONE, ALL},
{ "cmp", OP_mCPC, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
{ "cmp", OP_DYA, "00011sssrrrrrr00", 2, 0x1800, 0, 0, CHG_NZVC, ALL},
{ "com", OP_DM, "00010rrrsssrrr11", 2, 0x1003, 0, 0, CHG_NZVC, ALL},
{ "com", OP_DYA, "00010rrrsssrrr11", 2, 0x1003, 0, 0, CHG_NZV, ALL},
{ "cpc", OP_DYA, "00011sssrrrrrr01", 2, 0x1801, 0, 0, CHG_NZVC, ALL},
{ "ldd", OP_mLDW, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
{ "ldw", OP_mLDW, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
{ "mov", OP_DYA, "00010rrrsssrrr10", 2, 0x1002, 0, 0, CHG_NZVC, ALL},
{ "neg", OP_DYA, "00011rrrsssrrr00", 2, 0x1800, 0, 0, CHG_NZVC, ALL},
{ "sub", OP_mSUB, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
{ "tst", OP_MON, "00011sssrrrsss00", 2, 0x1800, 0, 0, CHG_NZV, ALL}
};
const int xgate_num_opcodes = TABLE_SIZE (xgate_opcodes);