RISC-V: Add .insn support.
gas/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * config/tc-riscv.c (opcode_name_list): New. (opcode_names_hash): Likewise. (init_opcode_names_hash): Likewise. (opcode_name_lookup): Likewise. (validate_riscv_insn): New argument length, and add new format which used in .insn directive. (md_begin): Refine hash table initialization logic into init_opcode_hash. (init_opcode_hash): New. (my_getOpcodeExpression): Parse opcode name for .insn. (riscv_ip): New argument hash, able to handle .insn directive. (s_riscv_insn): Handler for .insn directive. (riscv_pseudo_table): New entry for .insn. * doc/c-riscv.texi: Add documentation for .insn directive. * testsuite/gas/riscv/insn.d: Add testcase for .insn directive. * testsuite/gas/riscv/insn.s: Likewise. include/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * opcode/riscv.h (OP_MASK_FUNCT3): New. (OP_SH_FUNCT3): Likewise. (OP_MASK_FUNCT7): Likewise. (OP_SH_FUNCT7): Likewise. (OP_MASK_OP2): Likewise. (OP_SH_OP2): Likewise. (OP_MASK_CFUNCT4): Likewise. (OP_SH_CFUNCT4): Likewise. (OP_MASK_CFUNCT3): Likewise. (OP_SH_CFUNCT3): Likewise. (riscv_insn_types): Likewise. opcodes/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_insn_types): New.
This commit is contained in:
Jim Wilson
parent
3ae9ce5dd7
commit
0e35537d75
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@ -1,3 +1,22 @@
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2018-03-14 Kito Cheng <kito.cheng@gmail.com>
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* config/tc-riscv.c (opcode_name_list): New.
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(opcode_names_hash): Likewise.
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(init_opcode_names_hash): Likewise.
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(opcode_name_lookup): Likewise.
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(validate_riscv_insn): New argument length, and add new format
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which used in .insn directive.
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(md_begin): Refine hash table initialization logic into
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init_opcode_hash.
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(init_opcode_hash): New.
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(my_getOpcodeExpression): Parse opcode name for .insn.
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(riscv_ip): New argument hash, able to handle .insn directive.
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(s_riscv_insn): Handler for .insn directive.
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(riscv_pseudo_table): New entry for .insn.
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* doc/c-riscv.texi: Add documentation for .insn directive.
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* testsuite/gas/riscv/insn.d: Add testcase for .insn directive.
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* testsuite/gas/riscv/insn.s: Likewise.
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2018-03-13 Nick Clifton <nickc@redhat.com>
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* po/ru.po: Updated Russian translation.
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@ -221,6 +221,9 @@ riscv_set_arch (const char *s)
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/* Handle of the OPCODE hash table. */
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static struct hash_control *op_hash = NULL;
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/* Handle of the type of .insn hash table. */
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static struct hash_control *insn_type_hash = NULL;
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/* This array holds the chars that always start a comment. If the
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pre-processor is disabled, these aren't very useful */
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const char comment_chars[] = "#";
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@ -391,6 +394,111 @@ relaxed_branch_length (fragS *fragp, asection *sec, int update)
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return length;
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}
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/* Information about an opcode name, mnemonics and its value. */
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struct opcode_name_t
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{
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const char *name;
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unsigned int val;
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};
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/* List for all supported opcode name. */
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static const struct opcode_name_t opcode_name_list[] =
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{
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{"C0", 0x0},
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{"C1", 0x1},
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{"C2", 0x2},
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{"LOAD", 0x03},
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{"LOAD_FP", 0x07},
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{"CUSTOM_0", 0x0b},
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{"MISC_MEM", 0x0f},
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{"OP_IMM", 0x13},
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{"AUIPC", 0x17},
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{"OP_IMM_32", 0x1b},
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/* 48b 0x1f. */
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{"STORE", 0x23},
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{"STORE_FP", 0x27},
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{"CUSTOM_1", 0x2b},
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{"AMO", 0x2f},
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{"OP", 0x33},
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{"LUI", 0x37},
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{"OP_32", 0x3b},
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/* 64b 0x3f. */
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{"MADD", 0x43},
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{"MSUB", 0x47},
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{"NMADD", 0x4f},
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{"NMSUB", 0x4b},
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{"OP_FP", 0x53},
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/*reserved 0x57. */
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{"CUSTOM_2", 0x5b},
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/* 48b 0x5f. */
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{"BRANCH", 0x63},
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{"JALR", 0x67},
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/*reserved 0x5b. */
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{"JAL", 0x6f},
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{"SYSTEM", 0x73},
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/*reserved 0x77. */
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{"CUSTOM_3", 0x7b},
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/* >80b 0x7f. */
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{NULL, 0}
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};
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/* Hash table for lookup opcode name. */
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static struct hash_control *opcode_names_hash = NULL;
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/* Initialization for hash table of opcode name. */
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static void
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init_opcode_names_hash (void)
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{
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const char *retval;
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const struct opcode_name_t *opcode;
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for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
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{
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retval = hash_insert (opcode_names_hash, opcode->name, (void *)opcode);
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if (retval != NULL)
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as_fatal (_("internal error: can't hash `%s': %s"),
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opcode->name, retval);
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}
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}
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/* Find `s` is a valid opcode name or not,
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return the opcode name info if found. */
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static const struct opcode_name_t *
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opcode_name_lookup (char **s)
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{
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char *e;
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char save_c;
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struct opcode_name_t *o;
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/* Find end of name. */
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e = *s;
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if (is_name_beginner (*e))
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++e;
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while (is_part_of_name (*e))
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++e;
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/* Terminate name. */
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save_c = *e;
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*e = '\0';
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o = (struct opcode_name_t *) hash_find (opcode_names_hash, *s);
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/* Advance to next token if one was recognized. */
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if (o)
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*s = e;
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*e = save_c;
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expr_end = e;
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return o;
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}
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struct regname
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{
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const char *name;
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@ -488,15 +596,24 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
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/* For consistency checking, verify that all bits are specified either
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by the match/mask part of the instruction definition, or by the
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operand list. */
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operand list.
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`length` could be 0, 4 or 8, 0 for auto detection. */
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static bfd_boolean
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validate_riscv_insn (const struct riscv_opcode *opc)
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validate_riscv_insn (const struct riscv_opcode *opc, int length)
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{
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const char *p = opc->args;
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char c;
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insn_t used_bits = opc->mask;
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int insn_width = 8 * riscv_insn_length (opc->match);
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insn_t required_bits = ~0ULL >> (64 - insn_width);
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int insn_width;
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insn_t required_bits;
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if (length == 0)
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insn_width = 8 * riscv_insn_length (opc->match);
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else
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insn_width = 8 * length;
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required_bits = ~0ULL >> (64 - insn_width);
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if ((used_bits & opc->match) != (opc->match & required_bits))
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{
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@ -536,8 +653,22 @@ validate_riscv_insn (const struct riscv_opcode *opc)
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case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
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case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
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case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
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case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
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case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
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case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
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case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
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case 'F': /* funct */
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switch (c = *p++)
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{
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case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
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case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
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default:
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as_bad (_("internal: bad RISC-V opcode"
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" (unknown operand type `CF%c'): %s %s"),
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c, opc->name, opc->args);
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return FALSE;
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}
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break;
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default:
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as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
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c, opc->name, opc->args);
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@ -562,6 +693,7 @@ validate_riscv_insn (const struct riscv_opcode *opc)
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case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
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case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
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case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
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case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
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case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
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case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
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case 'o':
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@ -574,6 +706,31 @@ validate_riscv_insn (const struct riscv_opcode *opc)
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case '[': break;
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case ']': break;
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case '0': break;
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case 'F': /* funct */
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switch (c = *p++)
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{
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case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
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case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
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case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
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default:
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as_bad (_("internal: bad RISC-V opcode"
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" (unknown operand type `F%c'): %s %s"),
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c, opc->name, opc->args);
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return FALSE;
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}
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break;
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case 'O': /* opcode */
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switch (c = *p++)
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{
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case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
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case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
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default:
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as_bad (_("internal: bad RISC-V opcode"
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" (unknown operand type `F%c'): %s %s"),
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c, opc->name, opc->args);
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return FALSE;
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}
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break;
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default:
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as_bad (_("internal: bad RISC-V opcode "
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"(unknown operand type `%c'): %s %s"),
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@ -597,52 +754,73 @@ struct percent_op_match
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bfd_reloc_code_real_type reloc;
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};
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/* This function is called once, at assembler startup time. It should set up
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all the tables, etc. that the MD part of the assembler will need. */
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void
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md_begin (void)
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/* Common hash table initialization function for
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instruction and .insn directive. */
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static struct hash_control *
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init_opcode_hash (const struct riscv_opcode *opcodes,
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bfd_boolean insn_directive_p)
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{
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int i = 0;
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unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
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if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
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as_warn (_("Could not set architecture and machine"));
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op_hash = hash_new ();
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while (riscv_opcodes[i].name)
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int length;
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struct hash_control *hash = hash_new ();
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while (opcodes[i].name)
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{
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const char *name = riscv_opcodes[i].name;
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const char *name = opcodes[i].name;
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const char *hash_error =
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hash_insert (op_hash, name, (void *) &riscv_opcodes[i]);
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hash_insert (hash, name, (void *) &opcodes[i]);
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if (hash_error)
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{
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fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
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riscv_opcodes[i].name, hash_error);
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opcodes[i].name, hash_error);
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/* Probably a memory allocation problem? Give up now. */
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as_fatal (_("Broken assembler. No assembly attempted."));
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}
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do
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{
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if (riscv_opcodes[i].pinfo != INSN_MACRO)
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if (opcodes[i].pinfo != INSN_MACRO)
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{
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if (!validate_riscv_insn (&riscv_opcodes[i]))
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if (insn_directive_p)
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length = ((name[0] == 'c') ? 2 : 4);
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else
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length = 0; /* Let assembler determine the length. */
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if (!validate_riscv_insn (&opcodes[i], length))
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as_fatal (_("Broken assembler. No assembly attempted."));
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}
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else
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gas_assert (!insn_directive_p);
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++i;
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}
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while (riscv_opcodes[i].name && !strcmp (riscv_opcodes[i].name, name));
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while (opcodes[i].name && !strcmp (opcodes[i].name, name));
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}
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return hash;
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}
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/* This function is called once, at assembler startup time. It should set up
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all the tables, etc. that the MD part of the assembler will need. */
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void
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md_begin (void)
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{
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unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
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if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
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as_warn (_("Could not set architecture and machine"));
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op_hash = init_opcode_hash (riscv_opcodes, FALSE);
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insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
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reg_names_hash = hash_new ();
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hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
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hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
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hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
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hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
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opcode_names_hash = hash_new ();
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init_opcode_names_hash ();
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#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
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#define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
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#include "opcode/riscv-opc.h"
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@ -1186,6 +1364,23 @@ my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
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return reloc_index;
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}
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/* Parse opcode name, could be an mnemonics or number. */
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static size_t
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my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
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char *str, const struct percent_op_match *percent_op)
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{
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const struct opcode_name_t *o = opcode_name_lookup (&str);
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if (o != NULL)
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{
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ep->X_op = O_constant;
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ep->X_add_number = o->val;
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return 0;
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}
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return my_getSmallExpression (ep, reloc, str, percent_op);
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}
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/* Detect and handle implicitly zero load-store offsets. For example,
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"lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
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an implicit offset was detected. */
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@ -1211,7 +1406,7 @@ riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
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static const char *
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riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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bfd_reloc_code_real_type *imm_reloc)
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bfd_reloc_code_real_type *imm_reloc, struct hash_control *hash)
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{
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char *s;
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const char *args;
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@ -1234,7 +1429,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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break;
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}
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insn = (struct riscv_opcode *) hash_find (op_hash, str);
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insn = (struct riscv_opcode *) hash_find (hash, str);
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argsStart = s;
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for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
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@ -1259,7 +1454,12 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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{
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if (!insn->match_func (insn, ip->insn_opcode))
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break;
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if (riscv_insn_length (insn->match) == 2 && !riscv_opts.rvc)
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/* For .insn, insn->match and insn->mask are 0. */
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if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
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? ip->insn_opcode
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: insn->match) == 2
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&& !riscv_opts.rvc)
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break;
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}
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if (*s != '\0')
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@ -1328,6 +1528,15 @@ rvc_imm_done:
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break;
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ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
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goto rvc_imm_done;
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case '8':
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if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
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|| imm_expr->X_op != O_constant
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|| !VALID_RVC_UIMM8 (imm_expr->X_add_number)
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|| imm_expr->X_add_number < 0
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|| imm_expr->X_add_number >= 256)
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break;
|
||||
ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
|
||||
goto rvc_imm_done;
|
||||
case 'i':
|
||||
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
||||
|| imm_expr->X_op != O_constant
|
||||
|
|
@ -1457,6 +1666,12 @@ rvc_lui:
|
|||
goto branch;
|
||||
case 'a':
|
||||
goto jump;
|
||||
case 'S': /* Floating-point RS1 x8-x15. */
|
||||
if (!reg_lookup (&s, RCLASS_FPR, ®no)
|
||||
|| !(regno >= 8 && regno <= 15))
|
||||
break;
|
||||
INSERT_OPERAND (CRS1S, *ip, regno % 8);
|
||||
continue;
|
||||
case 'D': /* Floating-point RS2 x8-x15. */
|
||||
if (!reg_lookup (&s, RCLASS_FPR, ®no)
|
||||
|| !(regno >= 8 && regno <= 15))
|
||||
|
|
@ -1468,6 +1683,45 @@ rvc_lui:
|
|||
break;
|
||||
INSERT_OPERAND (CRS2, *ip, regno);
|
||||
continue;
|
||||
case 'F':
|
||||
switch (*++args)
|
||||
{
|
||||
case '4':
|
||||
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
||||
|| imm_expr->X_op != O_constant
|
||||
|| imm_expr->X_add_number < 0
|
||||
|| imm_expr->X_add_number >= 16)
|
||||
{
|
||||
as_bad (_("bad value for funct4 field, "
|
||||
"value must be 0...15"));
|
||||
break;
|
||||
}
|
||||
|
||||
INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
|
||||
imm_expr->X_op = O_absent;
|
||||
s = expr_end;
|
||||
continue;
|
||||
case '3':
|
||||
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
||||
|| imm_expr->X_op != O_constant
|
||||
|| imm_expr->X_add_number < 0
|
||||
|| imm_expr->X_add_number >= 8)
|
||||
{
|
||||
as_bad (_("bad value for funct3 field, "
|
||||
"value must be 0...7"));
|
||||
break;
|
||||
}
|
||||
INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
|
||||
imm_expr->X_op = O_absent;
|
||||
s = expr_end;
|
||||
continue;
|
||||
default:
|
||||
as_bad (_("bad compressed FUNCT field"
|
||||
" specifier 'CF%c'\n"),
|
||||
*args);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
|
||||
}
|
||||
|
|
@ -1561,6 +1815,7 @@ rvc_lui:
|
|||
case 'd': /* Destination register. */
|
||||
case 's': /* Source register. */
|
||||
case 't': /* Target register. */
|
||||
case 'r': /* rs3. */
|
||||
if (reg_lookup (&s, RCLASS_GPR, ®no))
|
||||
{
|
||||
c = *args;
|
||||
|
|
@ -1580,6 +1835,9 @@ rvc_lui:
|
|||
case 't':
|
||||
INSERT_OPERAND (RS2, *ip, regno);
|
||||
break;
|
||||
case 'r':
|
||||
INSERT_OPERAND (RS3, *ip, regno);
|
||||
break;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
|
@ -1712,6 +1970,99 @@ jump:
|
|||
else
|
||||
*imm_reloc = BFD_RELOC_RISCV_CALL;
|
||||
continue;
|
||||
case 'O':
|
||||
switch (*++args)
|
||||
{
|
||||
case '4':
|
||||
if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
|
||||
|| imm_expr->X_op != O_constant
|
||||
|| imm_expr->X_add_number < 0
|
||||
|| imm_expr->X_add_number >= 128
|
||||
|| (imm_expr->X_add_number & 0x3) != 3)
|
||||
{
|
||||
as_bad (_("bad value for opcode field, "
|
||||
"value must be 0...127 and "
|
||||
"lower 2 bits must be 0x3"));
|
||||
break;
|
||||
}
|
||||
|
||||
INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
|
||||
imm_expr->X_op = O_absent;
|
||||
s = expr_end;
|
||||
continue;
|
||||
case '2':
|
||||
if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
|
||||
|| imm_expr->X_op != O_constant
|
||||
|| imm_expr->X_add_number < 0
|
||||
|| imm_expr->X_add_number >= 3)
|
||||
{
|
||||
as_bad (_("bad value for opcode field, "
|
||||
"value must be 0...2"));
|
||||
break;
|
||||
}
|
||||
|
||||
INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
|
||||
imm_expr->X_op = O_absent;
|
||||
s = expr_end;
|
||||
continue;
|
||||
default:
|
||||
as_bad (_("bad Opcode field specifier 'O%c'\n"), *args);
|
||||
}
|
||||
break;
|
||||
|
||||
case 'F':
|
||||
switch (*++args)
|
||||
{
|
||||
case '7':
|
||||
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
||||
|| imm_expr->X_op != O_constant
|
||||
|| imm_expr->X_add_number < 0
|
||||
|| imm_expr->X_add_number >= 128)
|
||||
{
|
||||
as_bad (_("bad value for funct7 field, "
|
||||
"value must be 0...127"));
|
||||
break;
|
||||
}
|
||||
|
||||
INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
|
||||
imm_expr->X_op = O_absent;
|
||||
s = expr_end;
|
||||
continue;
|
||||
case '3':
|
||||
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
||||
|| imm_expr->X_op != O_constant
|
||||
|| imm_expr->X_add_number < 0
|
||||
|| imm_expr->X_add_number >= 8)
|
||||
{
|
||||
as_bad (_("bad value for funct3 field, "
|
||||
"value must be 0...7"));
|
||||
break;
|
||||
}
|
||||
|
||||
INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
|
||||
imm_expr->X_op = O_absent;
|
||||
s = expr_end;
|
||||
continue;
|
||||
case '2':
|
||||
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
||||
|| imm_expr->X_op != O_constant
|
||||
|| imm_expr->X_add_number < 0
|
||||
|| imm_expr->X_add_number >= 4)
|
||||
{
|
||||
as_bad (_("bad value for funct2 field, "
|
||||
"value must be 0...3"));
|
||||
break;
|
||||
}
|
||||
|
||||
INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
|
||||
imm_expr->X_op = O_absent;
|
||||
s = expr_end;
|
||||
continue;
|
||||
|
||||
default:
|
||||
as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args);
|
||||
}
|
||||
break;
|
||||
|
||||
case 'z':
|
||||
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
||||
|
|
@ -1746,7 +2097,7 @@ md_assemble (char *str)
|
|||
expressionS imm_expr;
|
||||
bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
|
||||
|
||||
const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc);
|
||||
const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
|
||||
|
||||
if (error)
|
||||
{
|
||||
|
|
@ -2614,6 +2965,40 @@ s_riscv_leb128 (int sign)
|
|||
return s_leb128 (sign);
|
||||
}
|
||||
|
||||
/* Parse the .insn directive. */
|
||||
|
||||
static void
|
||||
s_riscv_insn (int x ATTRIBUTE_UNUSED)
|
||||
{
|
||||
char *str = input_line_pointer;
|
||||
struct riscv_cl_insn insn;
|
||||
expressionS imm_expr;
|
||||
bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
|
||||
char save_c;
|
||||
|
||||
while (!is_end_of_line[(unsigned char) *input_line_pointer])
|
||||
++input_line_pointer;
|
||||
|
||||
save_c = *input_line_pointer;
|
||||
*input_line_pointer = '\0';
|
||||
|
||||
const char *error = riscv_ip (str, &insn, &imm_expr,
|
||||
&imm_reloc, insn_type_hash);
|
||||
|
||||
if (error)
|
||||
{
|
||||
as_bad ("%s `%s'", error, str);
|
||||
}
|
||||
else
|
||||
{
|
||||
gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
|
||||
append_insn (&insn, &imm_expr, imm_reloc);
|
||||
}
|
||||
|
||||
*input_line_pointer = save_c;
|
||||
demand_empty_rest_of_line ();
|
||||
}
|
||||
|
||||
/* Pseudo-op table. */
|
||||
|
||||
static const pseudo_typeS riscv_pseudo_table[] =
|
||||
|
|
@ -2628,6 +3013,7 @@ static const pseudo_typeS riscv_pseudo_table[] =
|
|||
{"bss", s_bss, 0},
|
||||
{"uleb128", s_riscv_leb128, 0},
|
||||
{"sleb128", s_riscv_leb128, 1},
|
||||
{"insn", s_riscv_insn, 0},
|
||||
|
||||
{ NULL, NULL, 0 },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
@menu
|
||||
* RISC-V-Options:: RISC-V Options
|
||||
* RISC-V-Directives:: RISC-V Directives
|
||||
* RISC-V-Formats:: RISC-V Instruction Formats
|
||||
@end menu
|
||||
|
||||
@node RISC-V-Options
|
||||
|
|
@ -148,4 +149,244 @@ opportunistically relax some code sequences, but sometimes this behavior is not
|
|||
desirable.
|
||||
@end table
|
||||
|
||||
@cindex INSN directives
|
||||
@item .insn @var{value}
|
||||
@itemx .insn @var{value}
|
||||
This directive permits the numeric representation of an instructions
|
||||
and makes the assembler insert the operands according to one of the
|
||||
instruction formats for @samp{.insn} (@ref{RISC-V-Formats}).
|
||||
For example, the instruction @samp{add a0, a1, a2} could be written as
|
||||
@samp{.insn r 0x33, 0, 0, a0, a1, a2}.
|
||||
|
||||
@end table
|
||||
|
||||
@node RISC-V-Formats
|
||||
@section Instruction Formats
|
||||
@cindex instruction formats, risc-v
|
||||
@cindex RISC-V instruction formats
|
||||
|
||||
The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12
|
||||
instruction formats where some of the formats have multiple variants.
|
||||
For the @samp{.insn} pseudo directive the assembler recognizes some
|
||||
of the formats.
|
||||
Typically, the most general variant of the instruction format is used
|
||||
by the @samp{.insn} directive.
|
||||
|
||||
The following table lists the abbreviations used in the table of
|
||||
instruction formats:
|
||||
|
||||
@display
|
||||
@multitable @columnfractions .15 .40
|
||||
@item opcode @tab Unsigned immediate or opcode name for 7-bits opcode.
|
||||
@item opcode2 @tab Unsigned immediate or opcode name for 2-bits opcode.
|
||||
@item func7 @tab Unsigned immediate for 7-bits function code.
|
||||
@item func4 @tab Unsigned immediate for 4-bits function code.
|
||||
@item func3 @tab Unsigned immediate for 3-bits function code.
|
||||
@item func2 @tab Unsigned immediate for 2-bits function code.
|
||||
@item rd @tab Destination register number for operand x, can be GPR or FPR.
|
||||
@item rd' @tab Destination register number for operand x,
|
||||
only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
|
||||
@item rs1 @tab First source register number for operand x, can be GPR or FPR.
|
||||
@item rs1' @tab First source register number for operand x,
|
||||
only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
|
||||
@item rs2 @tab Second source register number for operand x, can be GPR or FPR.
|
||||
@item rs2' @tab Second source register number for operand x,
|
||||
only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
|
||||
@item simm12 @tab Sign-extended 12-bit immediate for operand x.
|
||||
@item simm20 @tab Sign-extended 20-bit immediate for operand x.
|
||||
@item simm6 @tab Sign-extended 6-bit immediate for operand x.
|
||||
@item uimm8 @tab Unsigned 8-bit immediate for operand x.
|
||||
@item symbol @tab Symbol or lable reference for operand x.
|
||||
@end multitable
|
||||
@end display
|
||||
|
||||
The following table lists all available opcode name:
|
||||
|
||||
@table @code
|
||||
@item C0
|
||||
@item C1
|
||||
@item C2
|
||||
Opcode space for compressed instructions.
|
||||
|
||||
@item LOAD
|
||||
Opcode space for load instructions.
|
||||
|
||||
@item LOAD_FP
|
||||
Opcode space for floating-point load instructions.
|
||||
|
||||
@item STORE
|
||||
Opcode space for store instructions.
|
||||
|
||||
@item STORE_FP
|
||||
Opcode space for floating-point store instructions.
|
||||
|
||||
@item AUIPC
|
||||
Opcode space for auipc instruction.
|
||||
|
||||
@item LUI
|
||||
Opcode space for lui instruction.
|
||||
|
||||
@item BRANCH
|
||||
Opcode space for branch instructions.
|
||||
|
||||
@item JAL
|
||||
Opcode space for jal instruction.
|
||||
|
||||
@item JALR
|
||||
Opcode space for jalr instruction.
|
||||
|
||||
@item OP
|
||||
Opcode space for ALU instructions.
|
||||
|
||||
@item OP_32
|
||||
Opcode space for 32-bits ALU instructions.
|
||||
|
||||
@item OP_IMM
|
||||
Opcode space for ALU with immediate instructions.
|
||||
|
||||
@item OP_IMM_32
|
||||
Opcode space for 32-bits ALU with immediate instructions.
|
||||
|
||||
@item OP_FP
|
||||
Opcode space for floating-point operation instructions.
|
||||
|
||||
@item MADD
|
||||
Opcode space for madd instruction.
|
||||
|
||||
@item MSUB
|
||||
Opcode space for msub instruction.
|
||||
|
||||
@item NMADD
|
||||
Opcode space for nmadd instruction.
|
||||
|
||||
@item NMSUB
|
||||
Opcode space for msub instruction.
|
||||
|
||||
@item AMO
|
||||
Opcode space for atomic memory operation instructions.
|
||||
|
||||
@item MISC_IMM
|
||||
Opcode space for misc instructions.
|
||||
|
||||
@item SYSTEM
|
||||
Opcode space for system instructions.
|
||||
|
||||
@item CUSTOM_0
|
||||
@item CUSTOM_1
|
||||
@item CUSTOM_2
|
||||
@item CUSTOM_3
|
||||
Opcode space for customize instructions.
|
||||
|
||||
@end table
|
||||
|
||||
An instruction is two or four bytes in length and must be aligned
|
||||
on a 2 byte boundary. The first two bits of the instruction specify the
|
||||
length of the instruction, 00, 01 and 10 indicates a two byte instruction,
|
||||
11 indicates a four byte instruction.
|
||||
|
||||
The following table lists the RISC-V instruction formats that are available
|
||||
with the @samp{.insn} pseudo directive:
|
||||
|
||||
@table @code
|
||||
@item R type: .insn r opcode, func3, func7, rd, rs1, rs2
|
||||
@verbatim
|
||||
+-------+-----+-----+-------+----+-------------+
|
||||
| func7 | rs2 | rs1 | func3 | rd | opcode |
|
||||
+-------+-----+-----+-------+----+-------------+
|
||||
31 25 20 15 12 7 0
|
||||
@end verbatim
|
||||
|
||||
@item R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3
|
||||
@verbatim
|
||||
+-----+-------+-----+-----+-------+----+-------------+
|
||||
| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode |
|
||||
+-----+-------+-----+-----+-------+----+-------------+
|
||||
31 27 25 20 15 12 7 0
|
||||
@end verbatim
|
||||
|
||||
@item I type: .insn i opcode, func3, rd, rs1, simm12
|
||||
@verbatim
|
||||
+-------------+-----+-------+----+-------------+
|
||||
| simm12 | rs1 | func3 | rd | opcode |
|
||||
+-------------+-----+-------+----+-------------+
|
||||
31 20 15 12 7 0
|
||||
@end verbatim
|
||||
|
||||
@item S type: .insn s opcode, func3, rd, rs1, simm12
|
||||
@verbatim
|
||||
+--------------+-----+-----+-------+-------------+-------------+
|
||||
| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode |
|
||||
+--------------+-----+-----+-------+-------------+-------------+
|
||||
31 25 20 15 12 7 0
|
||||
@end verbatim
|
||||
|
||||
@item SB type: .insn sb opcode, func3, rd, rs1, symbol
|
||||
@itemx SB type: .insn sb opcode, func3, rd, simm12(rs1)
|
||||
@verbatim
|
||||
+--------------+-----+-----+-------+-------------+-------------+
|
||||
| simm21[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode |
|
||||
+--------------+-----+-----+-------+-------------+-------------+
|
||||
31 25 20 15 12 7 0
|
||||
@end verbatim
|
||||
|
||||
@item U type: .insn u opcode, rd, simm20
|
||||
@verbatim
|
||||
+---------------------------+----+-------------+
|
||||
| simm20 | rd | opcode |
|
||||
+---------------------------+----+-------------+
|
||||
31 12 7 0
|
||||
@end verbatim
|
||||
|
||||
@item UJ type: .insn uj opcode, rd, symbol
|
||||
@verbatim
|
||||
+------------+--------------+------------+---------------+----+-------------+
|
||||
| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode |
|
||||
+------------+--------------+------------+---------------+----+-------------+
|
||||
31 30 21 20 12 7 0
|
||||
@end verbatim
|
||||
|
||||
@item CR type: .insn cr opcode2, func4, rd, rs1
|
||||
@verbatim
|
||||
+---------+--------+-----+---------+
|
||||
| func4 | rd/rs1 | rs2 | opcode2 |
|
||||
+---------+--------+-----+---------+
|
||||
15 12 7 2 0
|
||||
@end verbatim
|
||||
|
||||
@item CI type: .insn ci opcode2, func3, rd, simm6
|
||||
@verbatim
|
||||
+---------+-----+--------+-----+---------+
|
||||
| func3 | imm | rd/rs1 | imm | opcode2 |
|
||||
+---------+-----+--------+-----+---------+
|
||||
15 13 12 7 2 0
|
||||
@end verbatim
|
||||
|
||||
@item CIW type: .insn ciw opcode2, func3, rd, uimm8
|
||||
@verbatim
|
||||
+---------+--------------+-----+---------+
|
||||
| func3 | imm | rd' | opcode2 |
|
||||
+---------+--------------+-----+---------+
|
||||
15 13 7 2 0
|
||||
@end verbatim
|
||||
|
||||
@item CB type: .insn cb opcode2, func3, rs1, symbol
|
||||
@verbatim
|
||||
+---------+--------+------+--------+---------+
|
||||
| func3 | offset | rs1' | offset | opcode2 |
|
||||
+---------+--------+------+--------+---------+
|
||||
15 13 10 7 2 0
|
||||
@end verbatim
|
||||
|
||||
@item CJ type: .insn cj opcode2, symbol
|
||||
@verbatim
|
||||
+---------+--------------------+---------+
|
||||
| func3 | jump target | opcode2 |
|
||||
+---------+--------------------+---------+
|
||||
15 13 7 2 0
|
||||
@end verbatim
|
||||
|
||||
|
||||
@end table
|
||||
|
||||
For the complete list of all instruction format variants see
|
||||
The RISC-V Instruction Set Manual Volume I: User-Level ISA.
|
||||
|
|
|
|||
|
|
@ -1,3 +1,17 @@
|
|||
2018-03-14 Kito Cheng <kito.cheng@gmail.com>
|
||||
|
||||
* opcode/riscv.h (OP_MASK_FUNCT3): New.
|
||||
(OP_SH_FUNCT3): Likewise.
|
||||
(OP_MASK_FUNCT7): Likewise.
|
||||
(OP_SH_FUNCT7): Likewise.
|
||||
(OP_MASK_OP2): Likewise.
|
||||
(OP_SH_OP2): Likewise.
|
||||
(OP_MASK_CFUNCT4): Likewise.
|
||||
(OP_SH_CFUNCT4): Likewise.
|
||||
(OP_MASK_CFUNCT3): Likewise.
|
||||
(OP_SH_CFUNCT3): Likewise.
|
||||
(riscv_insn_types): Likewise.
|
||||
|
||||
2018-03-13 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
PR 22113
|
||||
|
|
|
|||
|
|
@ -77,6 +77,8 @@ static const char * const riscv_pred_succ[16] =
|
|||
(EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)
|
||||
#define EXTRACT_RVC_SIMM3(x) \
|
||||
(RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))
|
||||
#define EXTRACT_RVC_UIMM8(x) \
|
||||
(RV_X(x, 5, 8))
|
||||
#define EXTRACT_RVC_ADDI4SPN_IMM(x) \
|
||||
((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
|
||||
#define EXTRACT_RVC_ADDI16SP_IMM(x) \
|
||||
|
|
@ -114,6 +116,8 @@ static const char * const riscv_pred_succ[16] =
|
|||
ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)
|
||||
#define ENCODE_RVC_SIMM3(x) \
|
||||
(RV_X(x, 0, 3) << 10)
|
||||
#define ENCODE_RVC_UIMM8(x) \
|
||||
(RV_X(x, 0, 8) << 5)
|
||||
#define ENCODE_RVC_ADDI4SPN_IMM(x) \
|
||||
((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
|
||||
#define ENCODE_RVC_ADDI16SP_IMM(x) \
|
||||
|
|
@ -143,6 +147,7 @@ static const char * const riscv_pred_succ[16] =
|
|||
#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
|
||||
#define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
|
||||
#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
|
||||
#define VALID_RVC_UIMM8(x) (EXTRACT_RVC_UIMM8(ENCODE_RVC_UIMM8(x)) == (x))
|
||||
#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
|
||||
#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
|
||||
#define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x))
|
||||
|
|
@ -223,8 +228,18 @@ static const char * const riscv_pred_succ[16] =
|
|||
#define OP_MASK_CSR 0xfff
|
||||
#define OP_SH_CSR 20
|
||||
|
||||
#define OP_MASK_FUNCT3 0x7
|
||||
#define OP_SH_FUNCT3 12
|
||||
#define OP_MASK_FUNCT7 0x7f
|
||||
#define OP_SH_FUNCT7 25
|
||||
#define OP_MASK_FUNCT2 0x3
|
||||
#define OP_SH_FUNCT2 25
|
||||
|
||||
/* RVC fields. */
|
||||
|
||||
#define OP_MASK_OP2 0x3
|
||||
#define OP_SH_OP2 0
|
||||
|
||||
#define OP_MASK_CRS2 0x1f
|
||||
#define OP_SH_CRS2 2
|
||||
#define OP_MASK_CRS1S 0x7
|
||||
|
|
@ -232,6 +247,11 @@ static const char * const riscv_pred_succ[16] =
|
|||
#define OP_MASK_CRS2S 0x7
|
||||
#define OP_SH_CRS2S 2
|
||||
|
||||
#define OP_MASK_CFUNCT4 0xf
|
||||
#define OP_SH_CFUNCT4 12
|
||||
#define OP_MASK_CFUNCT3 0x7
|
||||
#define OP_SH_CFUNCT3 13
|
||||
|
||||
/* ABI names for selected x-registers. */
|
||||
|
||||
#define X_RA 1
|
||||
|
|
@ -340,5 +360,6 @@ extern const char * const riscv_fpr_names_numeric[NFPR];
|
|||
extern const char * const riscv_fpr_names_abi[NFPR];
|
||||
|
||||
extern const struct riscv_opcode riscv_opcodes[];
|
||||
extern const struct riscv_opcode riscv_insn_types[];
|
||||
|
||||
#endif /* _RISCV_H_ */
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
2018-03-14 Kito Cheng <kito.cheng@gmail.com>
|
||||
|
||||
* riscv-opc.c (riscv_insn_types): New.
|
||||
|
||||
2018-03-13 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
||||
|
|
|
|||
|
|
@ -741,3 +741,77 @@ const struct riscv_opcode riscv_opcodes[] =
|
|||
/* Terminate the list. */
|
||||
{0, 0, 0, 0, 0, 0, 0}
|
||||
};
|
||||
|
||||
/* Instruction format for .insn directive. */
|
||||
const struct riscv_opcode riscv_insn_types[] =
|
||||
{
|
||||
/* name, isa, operands, match, mask, match_func, pinfo. */
|
||||
{"r", "I", "O4,F3,F7,d,s,t", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F7,D,s,t", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F7,d,S,t", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F7,D,S,t", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F7,d,s,T", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F7,D,s,T", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F7,d,S,T", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F7,D,S,T", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"r", "I", "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 },
|
||||
{"r", "I", "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"i", "I", "O4,F3,d,s,j", 0, 0, match_opcode, 0 },
|
||||
{"i", "I", "O4,F3,D,s,j", 0, 0, match_opcode, 0 },
|
||||
{"i", "I", "O4,F3,d,S,j", 0, 0, match_opcode, 0 },
|
||||
{"i", "I", "O4,F3,D,S,j", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"i", "I", "O4,F3,d,o(s)", 0, 0, match_opcode, 0 },
|
||||
{"i", "I", "O4,F3,D,o(s)", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"s", "I", "O4,F3,d,o(s)", 0, 0, match_opcode, 0 },
|
||||
{"s", "I", "O4,F3,D,o(s)", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"sb", "I", "O4,F3,s,t,p", 0, 0, match_opcode, 0 },
|
||||
{"sb", "I", "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
|
||||
{"sb", "I", "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
|
||||
{"sb", "I", "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"sb", "I", "O4,F3,t,q(s)", 0, 0, match_opcode, 0 },
|
||||
{"sb", "I", "O4,F3,T,q(s)", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"u", "I", "O4,d,u", 0, 0, match_opcode, 0 },
|
||||
{"u", "I", "O4,D,u", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"uj", "I", "O4,d,a", 0, 0, match_opcode, 0 },
|
||||
{"uj", "I", "O4,D,a", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"cr", "C", "O2,CF4,d,CV", 0, 0, match_opcode, 0 },
|
||||
{"cr", "C", "O2,CF4,D,CV", 0, 0, match_opcode, 0 },
|
||||
{"cr", "C", "O2,CF4,d,CT", 0, 0, match_opcode, 0 },
|
||||
{"cr", "C", "O2,CF4,D,CT", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"ci", "C", "O2,CF3,d,Co", 0, 0, match_opcode, 0 },
|
||||
{"ci", "C", "O2,CF3,D,Co", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"ciw", "C", "O2,CF3,Ct,C8", 0, 0, match_opcode, 0 },
|
||||
{"ciw", "C", "O2,CF3,CD,C8", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"cb", "C", "O2,CF3,Cs,Cp", 0, 0, match_opcode, 0 },
|
||||
{"cb", "C", "O2,CF3,CS,Cp", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"cj", "C", "O2,CF3,Ca", 0, 0, match_opcode, 0 },
|
||||
/* Terminate the list. */
|
||||
{0, 0, 0, 0, 0, 0, 0}
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue