The r5900 doesn't have HI/LO DIV/MUL register problems. Hobble
checks on hi/lo usage but retain functions so that they can be used for HI/LO stall counting code.
This commit is contained in:
Andrew Cagney
parent
05f6bf9cea
commit
0e797366ef
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@ -1,3 +1,15 @@
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start-sanitize-r5900
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Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
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Select corresponding check_mt_hilo function.
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(check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
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Ditto.
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* r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
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as r5900 specific.
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end-sanitize-r5900
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Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
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* interp.c (signal_exception): SystemCall exception now uses
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@ -132,9 +132,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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{
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signed64 time = sim_events_time (SD);
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int ok = check_mf_cycles (SD_, history, time, "MT");
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@ -148,6 +145,9 @@
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// start-sanitize-tx19
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*tx19:
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// end-sanitize-tx19
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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{
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signed64 time = sim_events_time (SD);
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history->mt.timestamp = time;
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@ -155,7 +155,20 @@
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return 1;
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}
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:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr5000:
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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*r3900:
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// start-sanitize-tx19
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*tx19:
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// end-sanitize-tx19
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{
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signed64 time = sim_events_time (SD);
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int ok = 1;
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@ -177,6 +190,24 @@
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return ok;
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}
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// start-sanitize-r5900
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// The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
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:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
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// end-sanitize-r5900
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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// start-sanitize-r5900
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{
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/* FIXME: could record the fact that a stall occured if we want */
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signed64 time = sim_events_time (SD);
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history->mf.timestamp = time;
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history->mf.cia = CIA;
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return 1;
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}
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// end-sanitize-r5900
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:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr5000:
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@ -186,9 +217,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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{
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signed64 time = sim_events_time (SD);
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int ok = (check_mf_cycles (SD_, hi, time, "OP")
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@ -200,7 +228,6 @@
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return ok;
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}
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// The r3900 mult and multu insns _can_ be exectuted immediatly after
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// a mf{hi,lo}
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:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
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@ -208,7 +235,11 @@
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// start-sanitize-tx19
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*tx19:
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// end-sanitize-tx19
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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{
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/* FIXME: could record the fact that a stall occured if we want */
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signed64 time = sim_events_time (SD);
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hi->op.timestamp = time;
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lo->op.timestamp = time;
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@ -217,6 +248,7 @@
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return 1;
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}
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:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr5000:
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@ -230,9 +262,6 @@
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// start-sanitize-tx19
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*tx19:
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// end-sanitize-tx19
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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{
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signed64 time = sim_events_time (SD);
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int ok = (check_mf_cycles (SD_, hi, time, "OP")
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@ -245,6 +274,27 @@
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}
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// start-sanitize-r5900
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// The r5900 div et.al insns _can_ be exectuted immediatly after
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// a mf{hi,lo}
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:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
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// end-sanitize-r5900
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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// start-sanitize-r5900
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{
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/* FIXME: could record the fact that a stall occured if we want */
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signed64 time = sim_events_time (SD);
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hi->op.timestamp = time;
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lo->op.timestamp = time;
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hi->op.cia = CIA;
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lo->op.cia = CIA;
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return 1;
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}
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// end-sanitize-r5900
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//
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// Mips Architecture:
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@ -2074,33 +2124,53 @@
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address_word reverseendian = (ReverseEndian ? -1 : 0);
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address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
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unsigned int byte;
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unsigned int word;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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address_word vaddr;
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int nr_lhs_bits;
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int nr_rhs_bits;
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unsigned_word lhs_mask;
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unsigned_word temp;
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vaddr = base + offset;
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AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
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paddr = (paddr ^ (reverseendian & mask));
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if (BigEndianMem == 0)
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paddr = paddr & ~access;
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byte = ((vaddr & mask) ^ (bigendiancpu & mask));
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LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
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/* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
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(long) vaddr, byte, (long) paddr, (long) memval); */
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if ((byte & ~access) == 0)
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/* compute where within the word/mem we are */
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byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
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word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
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nr_lhs_bits = 8 * byte + 8;
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nr_rhs_bits = 8 * access - 8 * byte;
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/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
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/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
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(long) ((unsigned64) vaddr >> 32), (long) vaddr,
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(long) ((unsigned64) paddr >> 32), (long) paddr,
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word, byte, nr_lhs_bits, nr_rhs_bits); */
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LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
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if (word == 0)
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{
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int bits = 8 * (access - byte);
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unsigned_word screen = LSMASK (bits - 1, 0);
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rt &= screen;
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rt |= ((memval << bits) & ~screen);
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/* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
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temp = (memval << nr_rhs_bits);
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}
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else
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{
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unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
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rt &= screen;
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rt |= ((memval >> (8 * (mask - byte))) & ~screen);
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/* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
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temp = (memval >> nr_lhs_bits);
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}
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lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
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rt = (rt & ~lhs_mask) | (temp & lhs_mask);
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/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
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(long) ((unsigned64) memval >> 32), (long) memval,
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(long) ((unsigned64) temp >> 32), (long) temp,
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(long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
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(long) (rt >> 32), (long) rt); */
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return rt;
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}
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@ -3212,22 +3282,43 @@
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address_word reverseendian = (ReverseEndian ? -1 : 0);
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address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
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unsigned int byte;
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unsigned int word;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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address_word vaddr;
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int nr_lhs_bits;
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int nr_rhs_bits;
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vaddr = base + offset;
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AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
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paddr = (paddr ^ (reverseendian & mask));
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if (BigEndianMem == 0)
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paddr = paddr & ~access;
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byte = ((vaddr & mask) ^ (bigendiancpu & mask));
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if ((byte & ~access) == 0)
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memval = (rt >> (8 * (access - byte)));
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/* compute where within the word/mem we are */
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byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
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word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
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nr_lhs_bits = 8 * byte + 8;
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nr_rhs_bits = 8 * access - 8 * byte;
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/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
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/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
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(long) ((unsigned64) vaddr >> 32), (long) vaddr,
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(long) ((unsigned64) paddr >> 32), (long) paddr,
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word, byte, nr_lhs_bits, nr_rhs_bits); */
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if (word == 0)
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{
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memval = (rt >> nr_rhs_bits);
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}
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else
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memval = (rt << (8 * (mask - byte)));
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StoreMemory (uncached, byte & access, memval, 0, paddr, vaddr, isREAL);
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{
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memval = (rt << nr_lhs_bits);
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}
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/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
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(long) ((unsigned64) rt >> 32), (long) rt,
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(long) ((unsigned64) memval >> 32), (long) memval); */
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StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
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}
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