start-sanitize-d10v
Mon Jul 22 11:32:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com> * config/tc-d10v.c: Many changes to get relocs working. (register_name): No longer creates a symbol for register names. (pre_defined_registers): moved to opcodes/d10v-opc.c. (d10v_insert_operand): Now works correctly for either container. * config/tc-d10v.h (d10v_cleanup): Declare. end-sanitize-d10v
This commit is contained in:
Martin Hunt
parent
d82a4ac0aa
commit
0ef325594a
@ -1,3 +1,13 @@
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start-sanitize-d10v
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Mon Jul 22 11:32:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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* config/tc-d10v.c: Many changes to get relocs working.
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(register_name): No longer creates a symbol for register names.
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(pre_defined_registers): moved to opcodes/d10v-opc.c.
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(d10v_insert_operand): Now works correctly for either container.
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* config/tc-d10v.h (d10v_cleanup): Declare.
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end-sanitize-d10v
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Mon Jul 22 14:01:33 1996 Ian Lance Taylor <ian@cygnus.com>
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* config/tc-mips.c (tc_gen_reloc): BFD_RELOC_PCREL_HI16_S and
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@ -33,29 +33,40 @@ const char *md_shortopts = "";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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/* local functions */
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static int reg_name_search PARAMS ((char *name));
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static void register_name PARAMS ((expressionS *expressionP));
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static int postfix PARAMS ((char *p));
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static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op));
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static int get_operands PARAMS ((expressionS exp[]));
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static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers));
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static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn));
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static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn));
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static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
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struct d10v_opcode *opcode2, unsigned long insn2, int exec_type));
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static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode));
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/* fixups */
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#define MAX_INSN_FIXUPS (5)
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struct d10v_fixup
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{
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expressionS exp;
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int opindex;
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bfd_reloc_code_real_type reloc;
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};
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struct d10v_fixup fixups[MAX_INSN_FIXUPS];
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static int fc;
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typedef struct _fixups
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{
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int fc;
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struct d10v_fixup fix[MAX_INSN_FIXUPS];
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struct _fixups *next;
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} Fixups;
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static Fixups FixUps[2];
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static Fixups *fixups;
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/* local functions */
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static int reg_name_search PARAMS ((char *name));
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static int register_name PARAMS ((expressionS *expressionP));
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static int postfix PARAMS ((char *p));
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static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op));
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static int get_operands PARAMS ((expressionS exp[]));
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static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers));
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static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
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static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
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static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
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struct d10v_opcode *opcode2, unsigned long insn2, int exec_type, Fixups *fx));
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static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode));
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static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type,
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offsetT value, int left));
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struct option md_longopts[] = {
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{NULL, no_argument, NULL, 0}
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@ -65,71 +76,12 @@ size_t md_longopts_size = sizeof(md_longopts);
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/* The target specific pseudo-ops which we support. */
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const pseudo_typeS md_pseudo_table[] =
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{
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/*
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{ "byte", ppc_byte, 0 },
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{ "long", ppc_elf_cons, 4 },
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{ "word", ppc_elf_cons, 2 },
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{ "short", ppc_elf_cons, 2 },
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{ "rdata", ppc_elf_rdata, 0 },
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{ "rodata", ppc_elf_rdata, 0 },
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{ "lcomm", ppc_elf_lcomm, 0 },
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*/
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{ NULL, NULL, 0 }
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};
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/* Opcode hash table. */
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static struct hash_control *d10v_hash;
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/* Structure to hold information about predefined registers. */
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struct pd_reg
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{
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char *name;
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int value;
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};
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/* an expressionS only has one register type, so we fake it */
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/* by setting high bits to indicate type */
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#define REGISTER_MASK 0xFF
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/* The table is sorted. Suitable for searching by a binary search. */
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static const struct pd_reg pre_defined_registers[] =
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{
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{ "a0", OPERAND_ACC+0 },
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{ "a1", OPERAND_ACC+1 },
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{ "bpc", OPERAND_CONTROL+3 },
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{ "bpsw", OPERAND_CONTROL+1 },
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{ "c", OPERAND_FLAG+3 },
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{ "f0", OPERAND_FLAG+0 },
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{ "f1", OPERAND_FLAG+1 },
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{ "iba", OPERAND_CONTROL+14 },
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{ "mod_e", OPERAND_CONTROL+11 },
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{ "mod_s", OPERAND_CONTROL+10 },
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{ "pc", OPERAND_CONTROL+2 },
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{ "psw", OPERAND_CONTROL+0 },
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{ "r0", 0 },
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{ "r1", 1 },
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{ "r10", 10 },
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{ "r11", 11 },
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{ "r12", 12 },
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{ "r13", 13 },
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{ "r14", 14 },
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{ "r15", 15 },
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{ "r2", 2 },
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{ "r3", 3 },
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{ "r4", 4 },
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{ "r5", 5 },
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{ "r6", 6 },
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{ "r7", 7 },
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{ "r8", 8 },
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{ "r9", 9 },
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{ "rpt_c", OPERAND_CONTROL+7 },
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{ "rpt_e", OPERAND_CONTROL+9 },
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{ "rpt_s", OPERAND_CONTROL+8 },
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{ "sp", 15 },
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};
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#define REG_NAME_CNT (sizeof(pre_defined_registers) / sizeof(struct pd_reg))
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/* reg_name_search does a binary search of the pre_defined_registers
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array to see if "name" is a valid regiter name. Returns the register
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number from the array on success, or -1 on failure. */
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@ -142,7 +94,7 @@ reg_name_search (name)
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int cmp;
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low = 0;
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high = REG_NAME_CNT - 1;
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high = reg_name_cnt() - 1;
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do
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{
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@ -159,30 +111,37 @@ reg_name_search (name)
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return -1;
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}
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/* register_name() checks the string at input_line_pointer
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to see if it is a valid register name */
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/* register_name check to see if an expression is a valid
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register name. If it is, it marks the expression type
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as O_register. */
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static void
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static int
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register_name (expressionP)
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expressionS *expressionP;
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{
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int reg_number;
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char *name;
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char c, *p = input_line_pointer;
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while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')')
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p++;
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if (expressionP->X_op == O_symbol)
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c = *p;
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if (c)
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*p++ = 0;
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/* look to see if it's in the register table */
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reg_number = reg_name_search (input_line_pointer);
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if (reg_number >= 0)
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{
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name = (char *)S_GET_NAME (expressionP->X_add_symbol);
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reg_number = reg_name_search (name);
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/* look to see if it's in the register table */
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if (reg_number >= 0)
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{
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expressionP->X_op = O_register;
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expressionP->X_add_number = reg_number;
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}
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expressionP->X_op = O_register;
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/* temporarily store a pointer to the string here */
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expressionP->X_op_symbol = (struct symbol *)input_line_pointer;
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expressionP->X_add_number = reg_number;
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input_line_pointer = p;
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return 1;
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}
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if (c)
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*(p-1) = c;
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return 0;
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}
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void
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@ -223,7 +182,7 @@ md_convert_frag (abfd, sec, fragP)
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asection *sec;
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fragS *fragP;
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{
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/* printf ("call to md_convert_frag \n"); */
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printf ("call to md_convert_frag \n");
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abort ();
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}
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@ -236,6 +195,7 @@ md_section_align (seg, addr)
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return ((addr + (1 << align) - 1) & (-1 << align));
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}
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void
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md_begin ()
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{
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@ -256,6 +216,10 @@ md_begin ()
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hash_insert (d10v_hash, opcode->name, (char *) opcode);
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}
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}
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fixups = &FixUps[0];
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FixUps[0].next = &FixUps[1];
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FixUps[1].next = &FixUps[0];
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}
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@ -299,8 +263,8 @@ get_reloc (op)
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if (op->flags & OPERAND_ADDR)
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{
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if (bits == 8)
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return (BFD_RELOC_D10V_10_PCREL_R);
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if (bits == 8)
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return (BFD_RELOC_D10V_10_PCREL_R);
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else
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return (BFD_RELOC_D10V_18_PCREL);
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}
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@ -357,10 +321,14 @@ get_operands (exp)
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}
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input_line_pointer = p;
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/* create an expression */
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expression (&exp[numops]);
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/* check to see if it might be a register name */
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register_name (&exp[numops]);
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if (!register_name (&exp[numops]))
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{
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/* parse as an expression */
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expression (&exp[numops]);
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}
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if (exp[numops].X_op == O_illegal)
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as_bad ("illegal operand");
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@ -388,14 +356,18 @@ get_operands (exp)
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}
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static unsigned long
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d10v_insert_operand (insn, op_type, value)
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d10v_insert_operand (insn, op_type, value, left)
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unsigned long insn;
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int op_type;
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offsetT value;
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int left;
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{
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int shift, bits;
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shift = d10v_operands[op_type].shift;
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if (left)
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shift += 15;
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bits = d10v_operands[op_type].bits;
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/* truncate to the proper number of bits */
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/* FIXME: overflow checking here? */
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@ -443,14 +415,14 @@ build_insn (opcode, opers)
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printf("\n");
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*/
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if (fc >= MAX_INSN_FIXUPS)
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if (fixups->fc >= MAX_INSN_FIXUPS)
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as_fatal ("too many fixups");
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fixups[fc].exp = opers[i];
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fixups->fix[fixups->fc].exp = opers[i];
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/* put the operand number here for now. We can look up
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the reloc type and/or fixup the instruction in md_apply_fix() */
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fixups[fc].reloc = opcode->operands[i];
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fc++;
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fixups->fix[fixups->fc].reloc = opcode->operands[i];
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(fixups->fc)++;
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}
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/* truncate to the proper number of bits */
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@ -463,84 +435,92 @@ build_insn (opcode, opers)
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/* write out a long form instruction */
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static void
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write_long (opcode, insn)
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write_long (opcode, insn, fx)
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struct d10v_opcode *opcode;
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unsigned long insn;
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Fixups *fx;
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{
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int i;
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char *f = frag_more(4);
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insn |= FM11;
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/* printf("INSN: %08x\n",insn); */
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/* printf("INSN: %08x\n",insn); */
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number_to_chars_bigendian (f, insn, 4);
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for (i=0; i<fc; i++)
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for (i=0; i < fx->fc; i++)
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{
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if (get_reloc((struct d10v_operand *)&d10v_operands[fixups[i].reloc]))
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if (get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc]))
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{
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/*
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printf("fix_new_exp: where:%x size:4\n ",f - frag_now->fr_literal);
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print_expr_1(stdout,&fixups[i].exp);
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print_expr_1(stdout,&(fx->fix[i].exp));
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printf("\n");
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*/
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fix_new_exp (frag_now,
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f - frag_now->fr_literal,
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4,
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&fixups[i].exp,
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&(fx->fix[i].exp),
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1,
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fixups[i].reloc);
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fx->fix[i].reloc);
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}
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}
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fx->fc = 0;
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}
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/* write out a short form instruction by itself */
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static void
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write_1_short (opcode, insn)
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write_1_short (opcode, insn, fx)
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struct d10v_opcode *opcode;
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unsigned long insn;
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Fixups *fx;
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{
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char *f = frag_more(4);
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int i;
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insn |= FM00 | (NOP << 15);
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/* printf("INSN: %08x\n",insn); */
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/* printf("INSN: %08x\n",insn); */
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number_to_chars_bigendian (f, insn, 4);
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for (i=0; i<fc; i++)
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for (i=0; i < fx->fc; i++)
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{
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if (get_reloc((struct d10v_operand *)&d10v_operands[fixups[i].reloc]))
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if (get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc]))
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{
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/*
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printf("fix_new_exp: where:%x size:4\n ",f - frag_now->fr_literal);
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print_expr_1(stdout,&fixups[i].exp);
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print_expr_1(stdout,&(fx->fix[i].exp));
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printf("\n");
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*/
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fix_new_exp (frag_now,
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f - frag_now->fr_literal,
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4,
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&fixups[i].exp,
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&(fx->fix[i].exp),
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1,
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fixups[i].reloc);
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fx->fix[i].reloc);
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}
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}
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fx->fc = 0;
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}
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/* write out a short form instruction if possible */
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/* return number of instructions not written out */
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static int
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write_2_short (opcode1, insn1, opcode2, insn2, exec_type)
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write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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struct d10v_opcode *opcode1, *opcode2;
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unsigned long insn1, insn2;
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int exec_type;
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Fixups *fx;
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{
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unsigned long insn;
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char *f;
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int i,j;
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if(opcode1->exec_type == BRANCH_LINK)
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{
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/* subroutines must be called from 32-bit boundaries */
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/* so the return address will be correct */
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write_1_short (opcode1, insn1);
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write_1_short (opcode1, insn1, fx->next);
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return (1);
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}
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@ -549,18 +529,22 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type)
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case 0:
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if (opcode1->unit == IU)
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{
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/* reverse sequential */
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insn = FM10 | (insn2 << 15) | insn1;
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}
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else
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{
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insn = FM01 | (insn1 << 15) | insn2;
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insn = FM01 | (insn1 << 15) | insn2;
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fx = fx->next;
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}
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break;
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case 1: /* parallel */
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insn = FM00 | (insn1 << 15) | insn2;
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fx = fx->next;
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break;
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case 2: /* sequential */
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insn = FM01 | (insn1 << 15) | insn2;
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fx = fx->next;
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break;
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case 3: /* reverse sequential */
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insn = FM10 | (insn1 << 15) | insn2;
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@ -570,7 +554,37 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type)
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}
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/* printf("INSN: %08x\n",insn); */
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number_to_chars_bigendian (frag_more(4), insn, 4);
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f = frag_more(4);
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number_to_chars_bigendian (f, insn, 4);
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for (j=0; j<2; j++)
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{
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bfd_reloc_code_real_type reloc;
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for (i=0; i < fx->fc; i++)
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{
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reloc = get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc]);
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if (reloc)
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{
|
||||
if ( (reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) )
|
||||
fx->fix[i].reloc |= 1024;
|
||||
|
||||
/*
|
||||
printf("fix_new_exp: where:%x reloc:%d\n ",f - frag_now->fr_literal,fx->fix[i].reloc);
|
||||
print_expr_1(stdout,&(fx->fix[i].exp));
|
||||
printf("\n");
|
||||
*/
|
||||
fix_new_exp (frag_now,
|
||||
f - frag_now->fr_literal,
|
||||
4,
|
||||
&(fx->fix[i].exp),
|
||||
1,
|
||||
fx->fix[i].reloc);
|
||||
}
|
||||
}
|
||||
fx->fc = 0;
|
||||
fx = fx->next;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -583,6 +597,8 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type)
|
||||
|
||||
static unsigned long prev_insn;
|
||||
static struct d10v_opcode *prev_opcode = 0;
|
||||
static subsegT prev_subseg;
|
||||
static segT prev_seg;
|
||||
|
||||
void
|
||||
md_assemble (str)
|
||||
@ -594,8 +610,7 @@ md_assemble (str)
|
||||
char *str2;
|
||||
|
||||
/* printf("md_assemble: str=%s\n",str); */
|
||||
fc = 0;
|
||||
|
||||
|
||||
/* look for the special multiple instruction seperators */
|
||||
str2 = strstr (str, "||");
|
||||
if (str2)
|
||||
@ -622,10 +637,11 @@ md_assemble (str)
|
||||
/* if two instructions are present and we already have one saved
|
||||
then first write it out */
|
||||
if (prev_opcode)
|
||||
write_1_short (prev_opcode, prev_insn);
|
||||
write_1_short (prev_opcode, prev_insn, fixups->next);
|
||||
|
||||
/* assemble first instruction and save it */
|
||||
prev_insn = do_assemble (str, &prev_opcode);
|
||||
fixups = fixups->next;
|
||||
str = str2 + 2;
|
||||
}
|
||||
|
||||
@ -638,15 +654,15 @@ md_assemble (str)
|
||||
as_fatal("Unable to mix instructions as specified");
|
||||
if (prev_opcode)
|
||||
{
|
||||
write_1_short (prev_opcode, prev_insn);
|
||||
write_1_short (prev_opcode, prev_insn, fixups->next);
|
||||
prev_opcode = NULL;
|
||||
}
|
||||
write_long (opcode, insn);
|
||||
write_long (opcode, insn, fixups);
|
||||
prev_opcode = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, t) == 0))
|
||||
if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, t, fixups) == 0))
|
||||
{
|
||||
/* no instructions saved */
|
||||
prev_opcode = NULL;
|
||||
@ -658,6 +674,9 @@ md_assemble (str)
|
||||
/* save off last instruction so it may be packed on next pass */
|
||||
prev_opcode = opcode;
|
||||
prev_insn = insn;
|
||||
prev_seg = now_seg;
|
||||
prev_subseg = now_subseg;
|
||||
fixups = fixups->next;
|
||||
}
|
||||
}
|
||||
|
||||
@ -675,7 +694,7 @@ do_assemble (str, opcode)
|
||||
expressionS myops[6];
|
||||
unsigned long insn;
|
||||
|
||||
/* printf("do_assemble: str=%s\n",str);*/
|
||||
/* printf("do_assemble: str=%s\n",str); */
|
||||
|
||||
/* Drop leading whitespace */
|
||||
while (*str == ' ')
|
||||
@ -780,7 +799,9 @@ do_assemble (str, opcode)
|
||||
if (!(d10v_operands[(*opcode)->operands[i]].flags & OPERAND_REG))
|
||||
{
|
||||
myops[i].X_op = O_symbol;
|
||||
myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol);
|
||||
myops[i].X_add_number = 0;
|
||||
myops[i].X_op_symbol = NULL;
|
||||
/* FIXME create a fixup */
|
||||
}
|
||||
}
|
||||
@ -849,6 +870,7 @@ md_apply_fix3 (fixp, valuep, seg)
|
||||
char *where;
|
||||
unsigned long insn;
|
||||
int op_type;
|
||||
int left=0;
|
||||
|
||||
if (fixp->fx_addsy == (symbolS *) NULL)
|
||||
{
|
||||
@ -873,20 +895,25 @@ md_apply_fix3 (fixp, valuep, seg)
|
||||
}
|
||||
}
|
||||
|
||||
/* printf("md_apply_fix: value=0x%x type=%d\n", value, fixp->fx_r_type); */
|
||||
/* printf("md_apply_fix: value=0x%x type=%d\n", value, fixp->fx_r_type); */
|
||||
|
||||
op_type = fixp->fx_r_type;
|
||||
fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]);
|
||||
|
||||
/* printf("reloc=%d\n",fixp->fx_r_type); */
|
||||
if (op_type & 1024)
|
||||
{
|
||||
op_type -= 1024;
|
||||
fixp->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
|
||||
left = 1;
|
||||
}
|
||||
else
|
||||
fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]);
|
||||
|
||||
/* Fetch the instruction, insert the fully resolved operand
|
||||
value, and stuff the instruction back again. */
|
||||
where = fixp->fx_frag->fr_literal + fixp->fx_where;
|
||||
insn = bfd_getb32 ((unsigned char *) where);
|
||||
/* printf(" insn=%x value=%x\n",insn,value); */
|
||||
/* printf(" insn=%x value=%x\n",insn,value); */
|
||||
|
||||
insn = d10v_insert_operand (insn, op_type, (offsetT) value);
|
||||
insn = d10v_insert_operand (insn, op_type, (offsetT) value, left);
|
||||
|
||||
/* printf(" new insn=%x\n",insn); */
|
||||
|
||||
@ -899,29 +926,24 @@ md_apply_fix3 (fixp, valuep, seg)
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* This is called after the assembler has finished parsing the input
|
||||
file. Because the D10V assembler sometimes saves short instructions
|
||||
to see if it can package them with the next instruction, there may
|
||||
|
||||
/* d10v_cleanup() is called after the assembler has finished parsing the input
|
||||
file or after a label is defined. Because the D10V assembler sometimes saves short
|
||||
instructions to see if it can package them with the next instruction, there may
|
||||
be a short instruction that still needs written. */
|
||||
|
||||
int md_after_pass()
|
||||
{
|
||||
if (prev_opcode)
|
||||
{
|
||||
write_1_short (prev_opcode, prev_insn);
|
||||
prev_opcode = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* there is a label to be defined. Any saved instruction must
|
||||
be written out. */
|
||||
int
|
||||
start_label()
|
||||
d10v_cleanup()
|
||||
{
|
||||
segT seg;
|
||||
subsegT subseg;
|
||||
|
||||
if (prev_opcode)
|
||||
{
|
||||
write_1_short (prev_opcode, prev_insn);
|
||||
seg = now_seg;
|
||||
subseg = now_subseg;
|
||||
subseg_set (prev_seg, prev_subseg);
|
||||
write_1_short (prev_opcode, prev_insn, fixups);
|
||||
subseg_set (seg, subseg);
|
||||
prev_opcode = NULL;
|
||||
}
|
||||
return 1;
|
||||
|
||||
@ -46,12 +46,10 @@
|
||||
/* We don't need to handle .word strangely. */
|
||||
#define WORKING_DOT_WORD
|
||||
|
||||
|
||||
#define md_number_to_chars number_to_chars_bigendian
|
||||
|
||||
#define md_after_pass_hook md_after_pass
|
||||
|
||||
extern int start_label PARAMS ((void));
|
||||
#define TC_START_LABEL(ch, ptr) (ch == ':' && start_label())
|
||||
int d10v_cleanup PARAMS ((void));
|
||||
#define md_after_pass_hook() d10v_cleanup()
|
||||
#define TC_START_LABEL(ch, ptr) (ch == ':' && d10v_cleanup())
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user