* ppc.h (struct powerpc_operand): New field `reloc'.
* ppc-opc.c: Include "bfd.h". (powerpc_operands): Add new field for reloc type.
This commit is contained in:
parent
179c732cf6
commit
0f1bac05bb
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@ -1,3 +1,8 @@
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2001-08-08 Alan Modra <amodra@one.net.au>
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1999-10-25 Torbjorn Granlund <tege@swox.com>
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* ppc.h (struct powerpc_operand): New field `reloc'.
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2001-07-11 Frank Ch. Eigler <fche@redhat.com>
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* cgen.h (CGEN_MACH): Add insn_chunk_bitsize field.
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@ -144,6 +144,7 @@ struct powerpc_operand
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/* One bit syntax flags. */
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unsigned long flags;
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int reloc;
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};
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/* Elements in the table are retrieved by indexing with values from
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@ -1,3 +1,9 @@
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2001-08-08 Alan Modra <amodra@bigpond.net.au>
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1999-10-25 Torbjorn Granlund <tege@swox.com>
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* ppc-opc.c: Include "bfd.h".
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(powerpc_operands): Add new field for reloc type.
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2001-07-21 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
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* mips-dis.c (print_insn_arg): Don't use software integer registers
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@ -24,6 +24,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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#include "sysdep.h"
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#include "opcode/ppc.h"
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#include "opintl.h"
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#include "bfd.h"
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/* This file holds the PowerPC opcode table. The opcode table
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includes almost all of the extended instruction mnemonics. This
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@ -93,241 +94,247 @@ const struct powerpc_operand powerpc_operands[] =
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/* The zero index is used to indicate the end of the list of
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operands. */
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#define UNUSED 0
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{ 0, 0, 0, 0, 0 },
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{ 0, 0, 0, 0, 0, 0},
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/* The BA field in an XL form instruction. */
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#define BA UNUSED + 1
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#define BA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_CR },
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{ 5, 16, 0, 0, PPC_OPERAND_CR, 0 },
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/* The BA field in an XL form instruction when it must be the same
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as the BT field in the same instruction. */
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#define BAT BA + 1
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{ 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
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{ 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE, 0 },
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/* The BB field in an XL form instruction. */
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#define BB BAT + 1
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#define BB_MASK (0x1f << 11)
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{ 5, 11, 0, 0, PPC_OPERAND_CR },
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{ 5, 11, 0, 0, PPC_OPERAND_CR, 0 },
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/* The BB field in an XL form instruction when it must be the same
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as the BA field in the same instruction. */
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#define BBA BB + 1
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{ 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
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{ 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE, 0 },
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/* The BD field in a B form instruction. The lower two bits are
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forced to zero. */
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#define BD BBA + 1
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{ 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
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{ 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED,
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BFD_RELOC_PPC_B16 },
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/* The BD field in a B form instruction when absolute addressing is
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used. */
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#define BDA BD + 1
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{ 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
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{ 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED,
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BFD_RELOC_PPC_BA16 },
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/* The BD field in a B form instruction when the - modifier is used.
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This sets the y bit of the BO field appropriately. */
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#define BDM BDA + 1
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{ 16, 0, insert_bdm, extract_bdm,
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PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
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{ 16, 0, insert_bdm, extract_bdm, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED,
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BFD_RELOC_PPC_B16 },
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/* The BD field in a B form instruction when the - modifier is used
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and absolute address is used. */
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#define BDMA BDM + 1
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{ 16, 0, insert_bdm, extract_bdm,
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PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
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{ 16, 0, insert_bdm, extract_bdm, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED,
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BFD_RELOC_PPC_BA16 },
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/* The BD field in a B form instruction when the + modifier is used.
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This sets the y bit of the BO field appropriately. */
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#define BDP BDMA + 1
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{ 16, 0, insert_bdp, extract_bdp,
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PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
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{ 16, 0, insert_bdp, extract_bdp, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED,
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BFD_RELOC_PPC_B16 },
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/* The BD field in a B form instruction when the + modifier is used
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and absolute addressing is used. */
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#define BDPA BDP + 1
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{ 16, 0, insert_bdp, extract_bdp,
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PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
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{ 16, 0, insert_bdp, extract_bdp, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED,
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BFD_RELOC_PPC_BA16 },
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/* The BF field in an X or XL form instruction. */
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#define BF BDPA + 1
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{ 3, 23, 0, 0, PPC_OPERAND_CR },
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{ 3, 23, 0, 0, PPC_OPERAND_CR, 0 },
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/* An optional BF field. This is used for comparison instructions,
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in which an omitted BF field is taken as zero. */
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#define OBF BF + 1
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{ 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
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{ 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL, 0 },
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/* The BFA field in an X or XL form instruction. */
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#define BFA OBF + 1
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{ 3, 18, 0, 0, PPC_OPERAND_CR },
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{ 3, 18, 0, 0, PPC_OPERAND_CR, 0 },
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/* The BI field in a B form or XL form instruction. */
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#define BI BFA + 1
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#define BI_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_CR },
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{ 5, 16, 0, 0, PPC_OPERAND_CR, 0 },
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/* The BO field in a B form instruction. Certain values are
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illegal. */
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#define BO BI + 1
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#define BO_MASK (0x1f << 21)
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{ 5, 21, insert_bo, extract_bo, 0 },
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{ 5, 21, insert_bo, extract_bo, 0, 0 },
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/* The BO field in a B form instruction when the + or - modifier is
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used. This is like the BO field, but it must be even. */
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#define BOE BO + 1
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{ 5, 21, insert_boe, extract_boe, 0 },
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{ 5, 21, insert_boe, extract_boe, 0, 0 },
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/* The BT field in an X or XL form instruction. */
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#define BT BOE + 1
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{ 5, 21, 0, 0, PPC_OPERAND_CR },
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{ 5, 21, 0, 0, PPC_OPERAND_CR, 0 },
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/* The condition register number portion of the BI field in a B form
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or XL form instruction. This is used for the extended
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conditional branch mnemonics, which set the lower two bits of the
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BI field. This field is optional. */
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#define CR BT + 1
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{ 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
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{ 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL, 0 },
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/* The D field in a D form instruction. This is a displacement off
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a register, and implies that the next operand is a register in
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parentheses. */
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#define D CR + 1
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{ 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
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{ 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED,
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BFD_RELOC_PPC_TOC16 },
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/* The DS field in a DS form instruction. This is like D, but the
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lower two bits are forced to zero. */
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#define DS D + 1
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{ 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
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{ 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED,
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BFD_RELOC_PPC_TOC16 },
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/* The E field in a wrteei instruction. */
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#define E DS + 1
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{ 1, 15, 0, 0, 0 },
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{ 1, 15, 0, 0, 0, 0 },
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/* The FL1 field in a POWER SC form instruction. */
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#define FL1 E + 1
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{ 4, 12, 0, 0, 0 },
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{ 4, 12, 0, 0, 0, 0 },
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/* The FL2 field in a POWER SC form instruction. */
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#define FL2 FL1 + 1
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{ 3, 2, 0, 0, 0 },
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{ 3, 2, 0, 0, 0, 0 },
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/* The FLM field in an XFL form instruction. */
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#define FLM FL2 + 1
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{ 8, 17, 0, 0, 0 },
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{ 8, 17, 0, 0, 0, 0 },
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/* The FRA field in an X or A form instruction. */
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#define FRA FLM + 1
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#define FRA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_FPR },
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{ 5, 16, 0, 0, PPC_OPERAND_FPR, 0 },
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/* The FRB field in an X or A form instruction. */
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#define FRB FRA + 1
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#define FRB_MASK (0x1f << 11)
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{ 5, 11, 0, 0, PPC_OPERAND_FPR },
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{ 5, 11, 0, 0, PPC_OPERAND_FPR, 0 },
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/* The FRC field in an A form instruction. */
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#define FRC FRB + 1
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#define FRC_MASK (0x1f << 6)
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{ 5, 6, 0, 0, PPC_OPERAND_FPR },
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{ 5, 6, 0, 0, PPC_OPERAND_FPR, 0 },
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/* The FRS field in an X form instruction or the FRT field in a D, X
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or A form instruction. */
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#define FRS FRC + 1
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#define FRT FRS
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{ 5, 21, 0, 0, PPC_OPERAND_FPR },
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{ 5, 21, 0, 0, PPC_OPERAND_FPR, 0 },
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/* The FXM field in an XFX instruction. */
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#define FXM FRS + 1
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#define FXM_MASK (0xff << 12)
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{ 8, 12, 0, 0, 0 },
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{ 8, 12, 0, 0, 0, 0 },
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/* The L field in a D or X form instruction. */
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#define L FXM + 1
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{ 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
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{ 1, 21, 0, 0, PPC_OPERAND_OPTIONAL, 0 },
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/* The LEV field in a POWER SC form instruction. */
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#define LEV L + 1
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{ 7, 5, 0, 0, 0 },
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{ 7, 5, 0, 0, 0, 0 },
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/* The LI field in an I form instruction. The lower two bits are
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forced to zero. */
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#define LI LEV + 1
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{ 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
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{ 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED,
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BFD_RELOC_PPC_B26 },
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/* The LI field in an I form instruction when used as an absolute
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address. */
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#define LIA LI + 1
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{ 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
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{ 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED,
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BFD_RELOC_PPC_BA26 },
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/* The MB field in an M form instruction. */
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#define MB LIA + 1
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#define MB_MASK (0x1f << 6)
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{ 5, 6, 0, 0, 0 },
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{ 5, 6, 0, 0, 0, 0 },
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/* The ME field in an M form instruction. */
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#define ME MB + 1
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#define ME_MASK (0x1f << 1)
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{ 5, 1, 0, 0, 0 },
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{ 5, 1, 0, 0, 0, 0 },
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/* The MB and ME fields in an M form instruction expressed a single
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operand which is a bitmask indicating which bits to select. This
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is a two operand form using PPC_OPERAND_NEXT. See the
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description in opcode/ppc.h for what this means. */
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#define MBE ME + 1
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{ 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
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{ 32, 0, insert_mbe, extract_mbe, 0 },
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{ 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT, 0 },
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{ 32, 0, insert_mbe, extract_mbe, 0, 0 },
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/* The MB or ME field in an MD or MDS form instruction. The high
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bit is wrapped to the low end. */
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#define MB6 MBE + 2
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#define ME6 MB6
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#define MB6_MASK (0x3f << 5)
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{ 6, 5, insert_mb6, extract_mb6, 0 },
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{ 6, 5, insert_mb6, extract_mb6, 0, 0 },
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/* The NB field in an X form instruction. The value 32 is stored as
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0. */
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#define NB MB6 + 1
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{ 6, 11, insert_nb, extract_nb, 0 },
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{ 6, 11, insert_nb, extract_nb, 0, 0 },
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/* The NSI field in a D form instruction. This is the same as the
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SI field, only negated. */
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#define NSI NB + 1
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{ 16, 0, insert_nsi, extract_nsi,
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PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
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PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED, 0 },
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/* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
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#define RA NSI + 1
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#define RA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_GPR },
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{ 5, 16, 0, 0, PPC_OPERAND_GPR, 0 },
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/* The RA field in a D or X form instruction which is an updating
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load, which means that the RA field may not be zero and may not
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equal the RT field. */
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#define RAL RA + 1
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{ 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
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{ 5, 16, insert_ral, 0, PPC_OPERAND_GPR, 0 },
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/* The RA field in an lmw instruction, which has special value
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restrictions. */
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#define RAM RAL + 1
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{ 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
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{ 5, 16, insert_ram, 0, PPC_OPERAND_GPR, 0 },
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/* The RA field in a D or X form instruction which is an updating
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store or an updating floating point load, which means that the RA
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field may not be zero. */
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#define RAS RAM + 1
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{ 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
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{ 5, 16, insert_ras, 0, PPC_OPERAND_GPR, 0 },
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/* The RB field in an X, XO, M, or MDS form instruction. */
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#define RB RAS + 1
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#define RB_MASK (0x1f << 11)
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{ 5, 11, 0, 0, PPC_OPERAND_GPR },
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{ 5, 11, 0, 0, PPC_OPERAND_GPR, 0 },
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/* The RB field in an X form instruction when it must be the same as
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the RS field in the instruction. This is used for extended
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mnemonics like mr. */
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#define RBS RB + 1
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{ 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
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{ 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE, 0 },
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/* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
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instruction or the RT field in a D, DS, X, XFX or XO form
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@ -335,101 +342,101 @@ const struct powerpc_operand powerpc_operands[] =
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#define RS RBS + 1
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#define RT RS
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#define RT_MASK (0x1f << 21)
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{ 5, 21, 0, 0, PPC_OPERAND_GPR },
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{ 5, 21, 0, 0, PPC_OPERAND_GPR, 0 },
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/* The SH field in an X or M form instruction. */
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#define SH RS + 1
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#define SH_MASK (0x1f << 11)
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{ 5, 11, 0, 0, 0 },
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{ 5, 11, 0, 0, 0, 0 },
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/* The SH field in an MD form instruction. This is split. */
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#define SH6 SH + 1
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#define SH6_MASK ((0x1f << 11) | (1 << 1))
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{ 6, 1, insert_sh6, extract_sh6, 0 },
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{ 6, 1, insert_sh6, extract_sh6, 0, 0 },
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/* The SI field in a D form instruction. */
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#define SI SH6 + 1
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{ 16, 0, 0, 0, PPC_OPERAND_SIGNED },
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{ 16, 0, 0, 0, PPC_OPERAND_SIGNED, 0 },
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/* The SI field in a D form instruction when we accept a wide range
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of positive values. */
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#define SISIGNOPT SI + 1
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{ 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
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{ 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT, 0 },
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/* The SPR field in an XFX form instruction. This is flipped--the
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lower 5 bits are stored in the upper 5 and vice- versa. */
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#define SPR SISIGNOPT + 1
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#define SPR_MASK (0x3ff << 11)
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{ 10, 11, insert_spr, extract_spr, 0 },
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{ 10, 11, insert_spr, extract_spr, 0, 0 },
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/* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
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#define SPRBAT SPR + 1
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#define SPRBAT_MASK (0x3 << 17)
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{ 2, 17, 0, 0, 0 },
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{ 2, 17, 0, 0, 0, 0 },
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/* The SPRG register number in an XFX form m[ft]sprg instruction. */
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#define SPRG SPRBAT + 1
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#define SPRG_MASK (0x3 << 16)
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{ 2, 16, 0, 0, 0 },
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{ 2, 16, 0, 0, 0, 0 },
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/* The SR field in an X form instruction. */
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#define SR SPRG + 1
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{ 4, 16, 0, 0, 0 },
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{ 4, 16, 0, 0, 0, 0 },
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/* The SV field in a POWER SC form instruction. */
|
||||
#define SV SR + 1
|
||||
{ 14, 2, 0, 0, 0 },
|
||||
{ 14, 2, 0, 0, 0, 0 },
|
||||
|
||||
/* The TBR field in an XFX form instruction. This is like the SPR
|
||||
field, but it is optional. */
|
||||
#define TBR SV + 1
|
||||
{ 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
|
||||
{ 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL, 0 },
|
||||
|
||||
/* The TO field in a D or X form instruction. */
|
||||
#define TO TBR + 1
|
||||
#define TO_MASK (0x1f << 21)
|
||||
{ 5, 21, 0, 0, 0 },
|
||||
{ 5, 21, 0, 0, 0, 0 },
|
||||
|
||||
/* The U field in an X form instruction. */
|
||||
#define U TO + 1
|
||||
{ 4, 12, 0, 0, 0 },
|
||||
{ 4, 12, 0, 0, 0, 0 },
|
||||
|
||||
/* The UI field in a D form instruction. */
|
||||
#define UI U + 1
|
||||
{ 16, 0, 0, 0, 0 },
|
||||
{ 16, 0, 0, 0, 0, 0 },
|
||||
|
||||
/* The VA field in a VA, VX or VXR form instruction. */
|
||||
#define VA UI + 1
|
||||
#define VA_MASK (0x1f << 16)
|
||||
{5, 16, 0, 0, PPC_OPERAND_VR},
|
||||
{5, 16, 0, 0, PPC_OPERAND_VR, 0},
|
||||
|
||||
/* The VB field in a VA, VX or VXR form instruction. */
|
||||
#define VB VA + 1
|
||||
#define VB_MASK (0x1f << 11)
|
||||
{5, 11, 0, 0, PPC_OPERAND_VR},
|
||||
{5, 11, 0, 0, PPC_OPERAND_VR, 0},
|
||||
|
||||
/* The VC field in a VA form instruction. */
|
||||
#define VC VB + 1
|
||||
#define VC_MASK (0x1f << 6)
|
||||
{5, 6, 0, 0, PPC_OPERAND_VR},
|
||||
{5, 6, 0, 0, PPC_OPERAND_VR, 0},
|
||||
|
||||
/* The VD or VS field in a VA, VX, VXR or X form instruction. */
|
||||
#define VD VC + 1
|
||||
#define VS VD
|
||||
#define VD_MASK (0x1f << 21)
|
||||
{5, 21, 0, 0, PPC_OPERAND_VR},
|
||||
{5, 21, 0, 0, PPC_OPERAND_VR, 0},
|
||||
|
||||
/* The SIMM field in a VX form instruction. */
|
||||
#define SIMM VD + 1
|
||||
{ 5, 16, 0, 0, PPC_OPERAND_SIGNED},
|
||||
{ 5, 16, 0, 0, PPC_OPERAND_SIGNED, 0},
|
||||
|
||||
/* The UIMM field in a VX form instruction. */
|
||||
#define UIMM SIMM + 1
|
||||
{ 5, 16, 0, 0, 0 },
|
||||
{ 5, 16, 0, 0, 0, 0 },
|
||||
|
||||
/* The SHB field in a VA form instruction. */
|
||||
#define SHB UIMM + 1
|
||||
{ 4, 6, 0, 0, 0 },
|
||||
{ 4, 6, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
/* The functions used to insert and extract complicated operands. */
|
||||
|
|
Loading…
Reference in New Issue