Use consistent types for holding instructions, instruction masks, etc.
include/ * opcode/ppc.h (PPC_INT_FMT): Define. (struct powerpc_opcode) <opcode>: Update type. (struct powerpc_opcode) <mask>: Likewise. (struct powerpc_opcode) <bitm>: Likewise. (struct powerpc_opcode) <insert>: Likewise. (struct powerpc_opcode) <extract>: Likewise. (ppc_optional_operand_value): Likewise. gas/ * config/tc-ppc.c (last_insn): Update type. (insn_validate) <omask, mask>: Likewise. (ppc_setup_opcodes) <mask, right_bit>: Likewise. <PRINT_OPCODE_TABLE>: Update types and printf format specifiers. (ppc_insert_operand): Update return and argument types and remove unneeded type casts. <min, max, right, tmp>: Update type. (md_assemble): Remove unneeded type casts. <insn, val, tmp_insn>: Update type. opcodes/ * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space. (operand_value_powerpc): Update return and argument type. <value, top>: Update type. (skip_optional_operands): Update argument type. (lookup_powerpc): Likewise. (lookup_vle): Likewise. <table_opcd, table_mask, insn2>: Update type. (lookup_spe2): Update argument type. <table_opcd, table_mask, insn2>: Update type. (print_insn_powerpc) <insn, value>: Update type. Use PPC_INT_FMT for printing instructions and operands. * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary, insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat, insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp, extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo, extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm, extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls, insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6, extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi, insert_ral, extract_ral, insert_ram, extract_ram, insert_raq, extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs, insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n, extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w, insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr, extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr, insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6, extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s, insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi, extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui, extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0, extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0, insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0, extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8, insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even, extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2, extract_off_spe2, insert_Ddd, extract_Ddd): Update types. (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15, BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX, DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK, SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST, VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET, VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA, VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK, XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK, XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK, XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB, XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
This commit is contained in:
Peter Bergner
parent
d0df06af9b
commit
0f873fd58b
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@ -1,3 +1,15 @@
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2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
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* config/tc-ppc.c (last_insn): Update type.
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(insn_validate) <omask, mask>: Likewise.
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(ppc_setup_opcodes) <mask, right_bit>: Likewise.
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<PRINT_OPCODE_TABLE>: Update types and printf format specifiers.
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(ppc_insert_operand): Update return and argument types and remove
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unneeded type casts.
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<min, max, right, tmp>: Update type.
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(md_assemble): Remove unneeded type casts.
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<insn, val, tmp_insn>: Update type.
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2017-11-29 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (enum i386_error): Remove try_vector_disp8.
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@ -217,7 +217,7 @@ static enum {
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/* Warn on emitting data to code sections. */
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int warn_476;
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unsigned long last_insn;
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uint64_t last_insn;
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segT last_seg;
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subsegT last_subseg;
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@ -1497,7 +1497,7 @@ static bfd_boolean
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insn_validate (const struct powerpc_opcode *op)
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{
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const unsigned char *o;
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unsigned long omask = op->mask;
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uint64_t omask = op->mask;
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/* The mask had better not trim off opcode bits. */
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if ((op->opcode & omask) != op->opcode)
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@ -1519,7 +1519,7 @@ insn_validate (const struct powerpc_opcode *op)
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const struct powerpc_operand *operand = &powerpc_operands[*o];
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if (operand->shift != (int) PPC_OPSHIFT_INV)
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{
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unsigned long mask;
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uint64_t mask;
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if (operand->shift >= 0)
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mask = operand->bitm << operand->shift;
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@ -1570,8 +1570,8 @@ ppc_setup_opcodes (void)
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all the 1's in the mask are contiguous. */
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for (i = 0; i < num_powerpc_operands; ++i)
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{
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unsigned long mask = powerpc_operands[i].bitm;
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unsigned long right_bit;
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uint64_t mask = powerpc_operands[i].bitm;
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uint64_t right_bit;
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unsigned int j;
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right_bit = mask & -mask;
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@ -1604,10 +1604,10 @@ ppc_setup_opcodes (void)
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int new_opcode = PPC_OP (op[0].opcode);
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#ifdef PRINT_OPCODE_TABLE
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printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n",
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printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
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op->name, (unsigned int) (op - powerpc_opcodes),
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(unsigned int) new_opcode, (unsigned int) op->opcode,
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(unsigned int) op->mask, (unsigned long long) op->flags);
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(unsigned int) new_opcode, (unsigned long long) op->opcode,
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(unsigned long long) op->mask, (unsigned long long) op->flags);
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#endif
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/* The major opcodes had better be sorted. Code in the
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@ -1669,10 +1669,10 @@ ppc_setup_opcodes (void)
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new_seg = VLE_OP_TO_SEG (new_seg);
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#ifdef PRINT_OPCODE_TABLE
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printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n",
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printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
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op->name, (unsigned int) (op - powerpc_opcodes),
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(unsigned int) new_seg, (unsigned int) op->opcode,
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(unsigned int) op->mask, (unsigned long long) op->flags);
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(unsigned int) new_seg, (unsigned long long) op->opcode,
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(unsigned long long) op->mask, (unsigned long long) op->flags);
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#endif
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/* The major opcodes had better be sorted. Code in the
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disassembler assumes the insns are sorted according to
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@ -1884,15 +1884,15 @@ ppc_cleanup (void)
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/* Insert an operand value into an instruction. */
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static unsigned long
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ppc_insert_operand (unsigned long insn,
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static uint64_t
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ppc_insert_operand (uint64_t insn,
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const struct powerpc_operand *operand,
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offsetT val,
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int64_t val,
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ppc_cpu_t cpu,
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const char *file,
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unsigned int line)
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{
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long min, max, right;
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int64_t min, max, right;
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max = operand->bitm;
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right = max & -max;
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@ -1921,7 +1921,7 @@ ppc_insert_operand (unsigned long insn,
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if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
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{
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long tmp = min;
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int64_t tmp = min;
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min = -max;
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max = -tmp;
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}
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@ -1934,18 +1934,18 @@ ppc_insert_operand (unsigned long insn,
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sign extend the 32-bit value to 64 bits if so doing makes the
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value valid. */
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if (val > max
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&& (offsetT) (val - 0x80000000 - 0x80000000) >= min
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&& (offsetT) (val - 0x80000000 - 0x80000000) <= max
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&& ((val - 0x80000000 - 0x80000000) & (right - 1)) == 0)
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val = val - 0x80000000 - 0x80000000;
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&& (val - (1LL << 32)) >= min
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&& (val - (1LL << 32)) <= max
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&& ((val - (1LL << 32)) & (right - 1)) == 0)
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val = val - (1LL << 32);
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/* Similarly, people write expressions like ~(1<<15), and expect
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this to be OK for a 32-bit unsigned value. */
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else if (val < min
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&& (offsetT) (val + 0x80000000 + 0x80000000) >= min
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&& (offsetT) (val + 0x80000000 + 0x80000000) <= max
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&& ((val + 0x80000000 + 0x80000000) & (right - 1)) == 0)
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val = val + 0x80000000 + 0x80000000;
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&& (val + (1LL << 32)) >= min
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&& (val + (1LL << 32)) <= max
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&& ((val + (1LL << 32)) & (right - 1)) == 0)
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val = val + (1LL << 32);
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else if (val < min
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|| val > max
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@ -1958,14 +1958,14 @@ ppc_insert_operand (unsigned long insn,
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const char *errmsg;
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errmsg = NULL;
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insn = (*operand->insert) (insn, (long) val, cpu, &errmsg);
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insn = (*operand->insert) (insn, val, cpu, &errmsg);
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if (errmsg != (const char *) NULL)
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as_bad_where (file, line, "%s", errmsg);
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}
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else if (operand->shift >= 0)
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insn |= ((long) val & operand->bitm) << operand->shift;
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insn |= (val & operand->bitm) << operand->shift;
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else
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insn |= ((long) val & operand->bitm) >> -operand->shift;
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insn |= (val & operand->bitm) >> -operand->shift;
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return insn;
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}
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@ -2739,7 +2739,7 @@ md_assemble (char *str)
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{
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char *s;
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const struct powerpc_opcode *opcode;
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unsigned long insn;
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uint64_t insn;
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const unsigned char *opindex_ptr;
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int skip_optional;
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int need_paren;
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@ -2868,7 +2868,7 @@ md_assemble (char *str)
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&& !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)
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&& skip_optional)
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{
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long val = ppc_optional_operand_value (operand);
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int64_t val = ppc_optional_operand_value (operand);
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if (operand->insert)
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{
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insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg);
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@ -2876,9 +2876,9 @@ md_assemble (char *str)
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as_bad ("%s", errmsg);
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}
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else if (operand->shift >= 0)
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insn |= ((long) val & operand->bitm) << operand->shift;
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insn |= (val & operand->bitm) << operand->shift;
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else
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insn |= ((long) val & operand->bitm) >> -operand->shift;
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insn |= (val & operand->bitm) >> -operand->shift;
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if ((operand->flags & PPC_OPERAND_NEXT) != 0)
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next_opindex = *opindex_ptr + 1;
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@ -3219,7 +3219,7 @@ md_assemble (char *str)
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/* If VLE-mode convert LO/HI/HA relocations. */
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if (opcode->flags & PPC_OPCODE_VLE)
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{
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int tmp_insn = insn & opcode->mask;
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uint64_t tmp_insn = insn & opcode->mask;
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int use_a_reloc = (tmp_insn == E_OR2I_INSN
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|| tmp_insn == E_AND2I_DOT_INSN
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@ -1,3 +1,13 @@
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2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
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* opcode/ppc.h (PPC_INT_FMT): Define.
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(struct powerpc_opcode) <opcode>: Update type.
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(struct powerpc_opcode) <mask>: Likewise.
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(struct powerpc_opcode) <bitm>: Likewise.
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(struct powerpc_opcode) <insert>: Likewise.
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(struct powerpc_opcode) <extract>: Likewise.
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(ppc_optional_operand_value): Likewise.
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2017-11-24 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/22444
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@ -30,6 +30,14 @@ extern "C" {
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typedef uint64_t ppc_cpu_t;
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#if BFD_HOST_64BIT_LONG
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# define PPC_INT_FMT "l"
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#elif defined (__MSVCRT__)
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# define PPC_INT_FMT "I64"
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#else
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# define PPC_INT_FMT "ll"
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#endif
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/* The opcode table is an array of struct powerpc_opcode. */
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struct powerpc_opcode
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/* The opcode itself. Those bits which will be filled in with
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operands are zeroes. */
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unsigned long opcode;
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uint64_t opcode;
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/* The opcode mask. This is used by the disassembler. This is a
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mask containing ones indicating those bits which must match the
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opcode field, and zeroes indicating those bits which need not
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match (and are presumably filled in by operands). */
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unsigned long mask;
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uint64_t mask;
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/* One bit flags for the opcode. These are used to indicate which
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specific processors support the instructions. The defined values
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@ -249,7 +257,7 @@ extern const int spe2_num_opcodes;
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struct powerpc_operand
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{
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/* A bitmask of bits in the operand. */
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unsigned int bitm;
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uint64_t bitm;
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/* The shift operation to be applied to the operand. No shift
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is made if this is zero. For positive values, the operand
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@ -277,8 +285,8 @@ struct powerpc_operand
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged (most operands
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can accept any value). */
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unsigned long (*insert)
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(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
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uint64_t (*insert)
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(uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg);
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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@ -299,7 +307,7 @@ struct powerpc_operand
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non-zero if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed. */
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long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
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int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid);
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/* One bit syntax flags. */
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unsigned long flags;
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@ -463,7 +471,7 @@ extern const int powerpc_num_macros;
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extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
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static inline long
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static inline int64_t
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ppc_optional_operand_value (const struct powerpc_operand *operand)
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{
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if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
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@ -1,3 +1,54 @@
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2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
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* opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
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(operand_value_powerpc): Update return and argument type.
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<value, top>: Update type.
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(skip_optional_operands): Update argument type.
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(lookup_powerpc): Likewise.
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(lookup_vle): Likewise.
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<table_opcd, table_mask, insn2>: Update type.
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(lookup_spe2): Update argument type.
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<table_opcd, table_mask, insn2>: Update type.
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(print_insn_powerpc) <insn, value>: Update type.
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Use PPC_INT_FMT for printing instructions and operands.
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* opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
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insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
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insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
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extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
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extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
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insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
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extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
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insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
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extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
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insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
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extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
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insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
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extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
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insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
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extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
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insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
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||||
extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
|
||||
insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
|
||||
extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
|
||||
extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
|
||||
extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
|
||||
insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
|
||||
extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
|
||||
insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
|
||||
extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
|
||||
extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
|
||||
(OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
|
||||
BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
|
||||
DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
|
||||
SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
|
||||
VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
|
||||
VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
|
||||
VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
|
||||
XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
|
||||
XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
|
||||
XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
|
||||
XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
|
||||
|
||||
2017-11-29 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-gen.c (active_cpu_flags, active_isstring, enum stage):
|
||||
|
|
|
|||
|
|
@ -381,39 +381,36 @@ disassemble_init_powerpc (struct disassemble_info *info)
|
|||
|
||||
if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
|
||||
{
|
||||
|
||||
i = powerpc_num_opcodes;
|
||||
while (--i >= 0)
|
||||
{
|
||||
unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
|
||||
|
||||
powerpc_opcd_indices[op] = i;
|
||||
}
|
||||
{
|
||||
unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
|
||||
powerpc_opcd_indices[op] = i;
|
||||
}
|
||||
|
||||
last = powerpc_num_opcodes;
|
||||
for (i = PPC_OPCD_SEGS; i > 0; --i)
|
||||
{
|
||||
if (powerpc_opcd_indices[i] == 0)
|
||||
{
|
||||
if (powerpc_opcd_indices[i] == 0)
|
||||
powerpc_opcd_indices[i] = last;
|
||||
last = powerpc_opcd_indices[i];
|
||||
}
|
||||
last = powerpc_opcd_indices[i];
|
||||
}
|
||||
|
||||
i = vle_num_opcodes;
|
||||
while (--i >= 0)
|
||||
{
|
||||
unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
|
||||
unsigned seg = VLE_OP_TO_SEG (op);
|
||||
|
||||
vle_opcd_indices[seg] = i;
|
||||
}
|
||||
{
|
||||
unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
|
||||
unsigned seg = VLE_OP_TO_SEG (op);
|
||||
vle_opcd_indices[seg] = i;
|
||||
}
|
||||
|
||||
last = vle_num_opcodes;
|
||||
for (i = VLE_OPCD_SEGS; i > 0; --i)
|
||||
{
|
||||
if (vle_opcd_indices[i] == 0)
|
||||
{
|
||||
if (vle_opcd_indices[i] == 0)
|
||||
vle_opcd_indices[i] = last;
|
||||
last = vle_opcd_indices[i];
|
||||
}
|
||||
last = vle_opcd_indices[i];
|
||||
}
|
||||
}
|
||||
|
||||
/* SPE2 opcodes */
|
||||
|
|
@ -422,7 +419,6 @@ disassemble_init_powerpc (struct disassemble_info *info)
|
|||
{
|
||||
unsigned xop = SPE2_XOP (spe2_opcodes[i].opcode);
|
||||
unsigned seg = SPE2_XOP_TO_SEG (xop);
|
||||
|
||||
spe2_opcd_indices[seg] = i;
|
||||
}
|
||||
|
||||
|
|
@ -464,11 +460,11 @@ print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
|
|||
|
||||
/* Extract the operand value from the PowerPC or POWER instruction. */
|
||||
|
||||
static long
|
||||
static int64_t
|
||||
operand_value_powerpc (const struct powerpc_operand *operand,
|
||||
unsigned long insn, ppc_cpu_t dialect)
|
||||
uint64_t insn, ppc_cpu_t dialect)
|
||||
{
|
||||
long value;
|
||||
int64_t value;
|
||||
int invalid;
|
||||
/* Extract the value from the instruction. */
|
||||
if (operand->extract)
|
||||
|
|
@ -483,7 +479,7 @@ operand_value_powerpc (const struct powerpc_operand *operand,
|
|||
{
|
||||
/* BITM is always some number of zeros followed by some
|
||||
number of ones, followed by some number of zeros. */
|
||||
unsigned long top = operand->bitm;
|
||||
uint64_t top = operand->bitm;
|
||||
/* top & -top gives the rightmost 1 bit, so this
|
||||
fills in any trailing zeros. */
|
||||
top |= (top & -top) - 1;
|
||||
|
|
@ -499,7 +495,7 @@ operand_value_powerpc (const struct powerpc_operand *operand,
|
|||
|
||||
static int
|
||||
skip_optional_operands (const unsigned char *opindex,
|
||||
unsigned long insn, ppc_cpu_t dialect)
|
||||
uint64_t insn, ppc_cpu_t dialect)
|
||||
{
|
||||
const struct powerpc_operand *operand;
|
||||
|
||||
|
|
@ -519,7 +515,7 @@ skip_optional_operands (const unsigned char *opindex,
|
|||
/* Find a match for INSN in the opcode table, given machine DIALECT. */
|
||||
|
||||
static const struct powerpc_opcode *
|
||||
lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
|
||||
lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
|
||||
{
|
||||
const struct powerpc_opcode *opcode, *opcode_end, *last;
|
||||
unsigned long op;
|
||||
|
|
@ -570,7 +566,7 @@ lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
|
|||
/* Find a match for INSN in the VLE opcode table. */
|
||||
|
||||
static const struct powerpc_opcode *
|
||||
lookup_vle (unsigned long insn)
|
||||
lookup_vle (uint64_t insn)
|
||||
{
|
||||
const struct powerpc_opcode *opcode;
|
||||
const struct powerpc_opcode *opcode_end;
|
||||
|
|
@ -590,10 +586,10 @@ lookup_vle (unsigned long insn)
|
|||
opcode < opcode_end;
|
||||
++opcode)
|
||||
{
|
||||
unsigned long table_opcd = opcode->opcode;
|
||||
unsigned long table_mask = opcode->mask;
|
||||
uint64_t table_opcd = opcode->opcode;
|
||||
uint64_t table_mask = opcode->mask;
|
||||
bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
|
||||
unsigned long insn2;
|
||||
uint64_t insn2;
|
||||
const unsigned char *opindex;
|
||||
const struct powerpc_operand *operand;
|
||||
int invalid;
|
||||
|
|
@ -624,7 +620,7 @@ lookup_vle (unsigned long insn)
|
|||
/* Find a match for INSN in the SPE2 opcode table. */
|
||||
|
||||
static const struct powerpc_opcode *
|
||||
lookup_spe2 (unsigned long insn)
|
||||
lookup_spe2 (uint64_t insn)
|
||||
{
|
||||
const struct powerpc_opcode *opcode, *opcode_end;
|
||||
unsigned op, xop, seg;
|
||||
|
|
@ -645,9 +641,9 @@ lookup_spe2 (unsigned long insn)
|
|||
opcode < opcode_end;
|
||||
++opcode)
|
||||
{
|
||||
unsigned long table_opcd = opcode->opcode;
|
||||
unsigned long table_mask = opcode->mask;
|
||||
unsigned long insn2;
|
||||
uint64_t table_opcd = opcode->opcode;
|
||||
uint64_t table_mask = opcode->mask;
|
||||
uint64_t insn2;
|
||||
const unsigned char *opindex;
|
||||
const struct powerpc_operand *operand;
|
||||
int invalid;
|
||||
|
|
@ -683,7 +679,7 @@ print_insn_powerpc (bfd_vma memaddr,
|
|||
{
|
||||
bfd_byte buffer[4];
|
||||
int status;
|
||||
unsigned long insn;
|
||||
uint64_t insn;
|
||||
const struct powerpc_opcode *opcode;
|
||||
bfd_boolean insn_is_short;
|
||||
|
||||
|
|
@ -753,7 +749,7 @@ print_insn_powerpc (bfd_vma memaddr,
|
|||
skip_optional = -1;
|
||||
for (opindex = opcode->operands; *opindex != 0; opindex++)
|
||||
{
|
||||
long value;
|
||||
int64_t value;
|
||||
|
||||
operand = powerpc_operands + *opindex;
|
||||
|
||||
|
|
@ -785,27 +781,27 @@ print_insn_powerpc (bfd_vma memaddr,
|
|||
/* Print the operand as directed by the flags. */
|
||||
if ((operand->flags & PPC_OPERAND_GPR) != 0
|
||||
|| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
|
||||
(*info->fprintf_func) (info->stream, "r%ld", value);
|
||||
(*info->fprintf_func) (info->stream, "r%" PPC_INT_FMT "d", value);
|
||||
else if ((operand->flags & PPC_OPERAND_FPR) != 0)
|
||||
(*info->fprintf_func) (info->stream, "f%ld", value);
|
||||
(*info->fprintf_func) (info->stream, "f%" PPC_INT_FMT "d", value);
|
||||
else if ((operand->flags & PPC_OPERAND_VR) != 0)
|
||||
(*info->fprintf_func) (info->stream, "v%ld", value);
|
||||
(*info->fprintf_func) (info->stream, "v%" PPC_INT_FMT "d", value);
|
||||
else if ((operand->flags & PPC_OPERAND_VSR) != 0)
|
||||
(*info->fprintf_func) (info->stream, "vs%ld", value);
|
||||
(*info->fprintf_func) (info->stream, "vs%" PPC_INT_FMT "d", value);
|
||||
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
|
||||
(*info->print_address_func) (memaddr + value, info);
|
||||
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
|
||||
(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
|
||||
else if ((operand->flags & PPC_OPERAND_FSL) != 0)
|
||||
(*info->fprintf_func) (info->stream, "fsl%ld", value);
|
||||
(*info->fprintf_func) (info->stream, "fsl%" PPC_INT_FMT "d", value);
|
||||
else if ((operand->flags & PPC_OPERAND_FCR) != 0)
|
||||
(*info->fprintf_func) (info->stream, "fcr%ld", value);
|
||||
(*info->fprintf_func) (info->stream, "fcr%" PPC_INT_FMT "d", value);
|
||||
else if ((operand->flags & PPC_OPERAND_UDI) != 0)
|
||||
(*info->fprintf_func) (info->stream, "%ld", value);
|
||||
(*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
|
||||
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
|
||||
&& (((dialect & PPC_OPCODE_PPC) != 0)
|
||||
|| ((dialect & PPC_OPCODE_VLE) != 0)))
|
||||
(*info->fprintf_func) (info->stream, "cr%ld", value);
|
||||
(*info->fprintf_func) (info->stream, "cr%" PPC_INT_FMT "d", value);
|
||||
else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
|
||||
&& (((dialect & PPC_OPCODE_PPC) != 0)
|
||||
|| ((dialect & PPC_OPCODE_VLE) != 0)))
|
||||
|
|
@ -821,7 +817,7 @@ print_insn_powerpc (bfd_vma memaddr,
|
|||
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
|
||||
}
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%d", (int) value);
|
||||
(*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
|
||||
|
||||
if (need_paren)
|
||||
{
|
||||
|
|
@ -851,7 +847,7 @@ print_insn_powerpc (bfd_vma memaddr,
|
|||
}
|
||||
|
||||
/* We could not find a match. */
|
||||
(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
|
||||
(*info->fprintf_func) (info->stream, ".long 0x%" PPC_INT_FMT "x", insn);
|
||||
|
||||
return 4;
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue