* mips-tdep.c (mips16_decode_reg_save): Delete, no longer used.
(mips_insn16_frame_cache): Pass frame cache in call to
heuristic_proc_desc. Move some code to mips16_heuristic_proc_desc.
Remove code that became redundant as a consequence.
(mips32_heuristic_proc_desc): No longer compute a fake
procedure descriptor. Compute the full frame cache instead.
Some minor comment reformatting.
This commit is contained in:
Joel Brobecker
parent
ed7aa6d6f8
commit
0fce082197
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@ -1,3 +1,13 @@
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2004-10-10 Joel Brobecker <brobecker@gnat.com>
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* mips-tdep.c (mips16_decode_reg_save): Delete, no longer used.
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(mips_insn16_frame_cache): Pass frame cache in call to
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heuristic_proc_desc. Move some code to mips16_heuristic_proc_desc.
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Remove code that became redundant as a consequence.
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(mips32_heuristic_proc_desc): No longer compute a fake
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procedure descriptor. Compute the full frame cache instead.
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Some minor comment reformatting.
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2004-10-10 Jim Blandy <jimb@redhat.com>
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* MAINTAINERS (generic symtabs, dwarf readers, elf reader, stabs
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242
gdb/mips-tdep.c
242
gdb/mips-tdep.c
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@ -945,30 +945,6 @@ after_prologue (CORE_ADDR pc)
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return 0;
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}
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/* Decode a MIPS16 instruction that saves a register in the stack, and
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set the appropriate bit in the general register or float register mask
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to indicate which register is saved. This is a helper function
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for mips_find_saved_regs. */
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static void
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mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
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{
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if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
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{
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int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
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*gen_mask |= (1 << reg);
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}
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else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
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{
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int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
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*gen_mask |= (1 << reg);
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}
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else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
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|| (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
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*gen_mask |= (1 << RA_REGNUM);
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}
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/* Fetch and return instruction from the specified location. If the PC
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is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
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@ -1765,154 +1741,9 @@ mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache)
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if (start_addr == 0)
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start_addr = heuristic_proc_start (pc);
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#ifdef NOT_YET
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proc_desc = heuristic_proc_desc (start_addr, pc, next_frame, *this_cache);
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#else
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proc_desc = heuristic_proc_desc (start_addr, pc, next_frame, NULL);
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#endif
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}
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/* Extract the frame's base. */
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cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc))
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+ PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
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kernel_trap = PROC_REG_MASK (proc_desc) & 1;
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gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
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float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
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/* In any frame other than the innermost or a frame interrupted by a
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signal, we assume that all registers have been saved. This
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assumes that all register saves in a function happen before the
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first function call. */
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if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc))
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/* Not sure exactly what kernel_trap means, but if it means the
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kernel saves the registers without a prologue doing it, we
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better not examine the prologue to see whether registers
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have been saved yet. */
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&& !kernel_trap)
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{
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/* We need to figure out whether the registers that the
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proc_desc claims are saved have been saved yet. */
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CORE_ADDR addr;
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/* Bitmasks; set if we have found a save for the register. */
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unsigned long gen_save_found = 0;
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unsigned long float_save_found = 0;
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int mips16;
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/* If the address is odd, assume this is MIPS16 code. */
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addr = PROC_LOW_ADDR (proc_desc);
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/* Scan through this function's instructions preceding the
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current PC, and look for those that save registers. */
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while (addr < frame_pc_unwind (next_frame))
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{
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mips16_decode_reg_save (mips16_fetch_instruction (addr),
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&gen_save_found);
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addr += MIPS16_INSTLEN;
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}
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gen_mask = gen_save_found;
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float_mask = float_save_found;
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}
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/* Fill in the offsets for the registers which gen_mask says were
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saved. */
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{
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CORE_ADDR reg_position = (cache->base
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+ PROC_REG_OFFSET (proc_desc));
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int ireg;
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for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
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if (gen_mask & 0x80000000)
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{
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cache->saved_regs[NUM_REGS + ireg].addr = reg_position;
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reg_position -= mips_abi_regsize (gdbarch);
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}
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}
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/* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
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order of that normally used by gcc. Therefore, we have to fetch
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the first instruction of the function, and if it's an entry
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instruction that saves $s0 or $s1, correct their saved addresses. */
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{
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ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc));
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if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700)
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/* entry */
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{
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int reg;
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int sreg_count = (inst >> 6) & 3;
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/* Check if the ra register was pushed on the stack. */
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CORE_ADDR reg_position = (cache->base
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+ PROC_REG_OFFSET (proc_desc));
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if (inst & 0x20)
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reg_position -= mips_abi_regsize (gdbarch);
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/* Check if the s0 and s1 registers were pushed on the
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stack. */
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/* NOTE: cagney/2004-02-08: Huh? This is doing no such
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check. */
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for (reg = 16; reg < sreg_count + 16; reg++)
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{
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cache->saved_regs[NUM_REGS + reg].addr = reg_position;
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reg_position -= mips_abi_regsize (gdbarch);
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}
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}
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}
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/* Fill in the offsets for the registers which float_mask says were
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saved. */
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{
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CORE_ADDR reg_position = (cache->base
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+ PROC_FREG_OFFSET (proc_desc));
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int ireg;
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/* Fill in the offsets for the float registers which float_mask
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says were saved. */
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for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
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if (float_mask & 0x80000000)
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{
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if (mips_abi_regsize (gdbarch) == 4
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&& TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
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{
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/* On a big endian 32 bit ABI, floating point registers
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are paired to form doubles such that the most
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significant part is in $f[N+1] and the least
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significant in $f[N] vis: $f[N+1] ||| $f[N]. The
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registers are also spilled as a pair and stored as a
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double.
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When little-endian the least significant part is
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stored first leading to the memory order $f[N] and
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then $f[N+1].
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Unfortunately, when big-endian the most significant
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part of the double is stored first, and the least
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significant is stored second. This leads to the
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registers being ordered in memory as firt $f[N+1] and
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then $f[N].
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For the big-endian case make certain that the
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addresses point at the correct (swapped) locations
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$f[N] and $f[N+1] pair (keep in mind that
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reg_position is decremented each time through the
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loop). */
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if ((ireg & 1))
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position - mips_abi_regsize (gdbarch);
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else
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position + mips_abi_regsize (gdbarch);
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}
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else
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position;
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reg_position -= mips_abi_regsize (gdbarch);
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}
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
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= cache->saved_regs[NUM_REGS + RA_REGNUM];
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}
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/* SP_REGNUM, contains the value and not the address. */
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trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base);
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@ -2445,14 +2276,13 @@ mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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{
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CORE_ADDR cur_pc;
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CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
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long frame_offset = 0; /* Size of stack frame. */
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long frame_adjust = 0; /* Offset of FP from SP. */
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int frame_reg = MIPS_SP_REGNUM;
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unsigned short prev_inst = 0; /* saved copy of previous instruction */
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unsigned inst = 0; /* current instruction */
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unsigned entry_inst = 0; /* the entry instruction */
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int reg, offset;
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struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
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PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
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PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
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for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
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{
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@ -2467,7 +2297,7 @@ mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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{
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offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
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if (offset < 0) /* negative stack adjustment? */
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PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
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frame_offset -= offset;
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else
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/* Exit loop if a positive stack adjustment is found, which
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usually means that the stack cleanup code in the function
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@ -2478,55 +2308,50 @@ mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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{
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offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
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reg = mips16_to_32_reg[(inst & 0x700) >> 8];
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PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
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set_reg_offset (this_cache, reg, sp + offset);
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}
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else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
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{
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offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
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reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
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PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
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set_reg_offset (this_cache, reg, sp + offset);
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}
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else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
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{
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offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
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PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
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set_reg_offset (this_cache, RA_REGNUM, sp + offset);
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}
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else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
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{
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offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
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PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
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set_reg_offset (this_cache, RA_REGNUM, sp + offset);
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}
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else if (inst == 0x673d) /* move $s1, $sp */
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{
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frame_addr = sp;
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PROC_FRAME_REG (&temp_proc_desc) = 17;
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frame_reg = 17;
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}
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else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
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{
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offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
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frame_addr = sp + offset;
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PROC_FRAME_REG (&temp_proc_desc) = 17;
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PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
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frame_reg = 17;
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frame_adjust = offset;
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}
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else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
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{
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offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
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reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
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PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
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set_reg_offset (this_cache, reg, frame_addr + offset);
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}
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else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
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{
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offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
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reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
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PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
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set_reg_offset (this_cache, reg, frame_addr + offset);
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}
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else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
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else if ((inst & 0xf81f) == 0xe809
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&& (inst & 0x700) != 0x700) /* entry */
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entry_inst = inst; /* save for later processing */
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else if ((inst & 0xf800) == 0x1800) /* jal(x) */
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cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
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@ -2544,16 +2369,15 @@ mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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int sreg_count = (entry_inst >> 6) & 3;
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/* The entry instruction always subtracts 32 from the SP. */
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PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
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frame_offset += 32;
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/* Now we can calculate what the SP must have been at the
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start of the function prologue. */
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sp += PROC_FRAME_OFFSET (&temp_proc_desc);
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sp += frame_offset;
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/* Check if a0-a3 were saved in the caller's argument save area. */
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for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
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{
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PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
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set_reg_offset (this_cache, reg, sp + offset);
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offset += mips_abi_regsize (current_gdbarch);
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}
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@ -2562,7 +2386,6 @@ mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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offset = -4;
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if (entry_inst & 0x20)
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{
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PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
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set_reg_offset (this_cache, RA_REGNUM, sp + offset);
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offset -= mips_abi_regsize (current_gdbarch);
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}
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@ -2570,11 +2393,52 @@ mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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/* Check if the s0 and s1 registers were pushed on the stack. */
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for (reg = 16; reg < sreg_count + 16; reg++)
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{
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PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
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set_reg_offset (this_cache, reg, sp + offset);
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offset -= mips_abi_regsize (current_gdbarch);
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}
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}
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if (this_cache != NULL)
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{
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this_cache->base =
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(frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg)
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+ frame_offset - frame_adjust);
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/* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
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be able to get rid of the assignment below, evetually. But it's
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still needed for now. */
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this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
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= this_cache->saved_regs[NUM_REGS + RA_REGNUM];
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}
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/* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
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order of that normally used by gcc. Therefore, we have to fetch
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the first instruction of the function, and if it's an entry
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instruction that saves $s0 or $s1, correct their saved addresses. */
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/* FIXME: brobecker/2004-10-10: This code was moved here from
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mips_insn16_frame_cache(), but can be merged with the block above
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handling entry_inst. Will be done in a separate pass, to make changes
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more atomic. Actually, this code seems completely redundant! */
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{
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ULONGEST inst = mips16_fetch_instruction (start_pc);
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if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
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{
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int reg;
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int sreg_count = (inst >> 6) & 3;
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CORE_ADDR reg_position = (this_cache->base);
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/* Check if the ra register was pushed on the stack. */
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if (inst & 0x20)
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reg_position -= mips_abi_regsize (current_gdbarch);
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/* Check if the s0 and s1 registers were pushed on the stack. */
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/* NOTE: cagney/2004-02-08: Huh? This is doing no such check. */
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for (reg = 16; reg < sreg_count + 16; reg++)
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{
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this_cache->saved_regs[NUM_REGS + reg].addr = reg_position;
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reg_position -= mips_abi_regsize (current_gdbarch);
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}
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}
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}
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}
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/* Mark all the registers as unset in the saved_regs array
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Loading…
Reference in New Issue