[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds support for the mitigation for Spectre Variant 4 by adding the PSTATE bit SSBS which are accessible using MSR and MRS instructions. Although this is a mandatory addition to the ARMv8.5-A, it is permitted to be added to any version of the ARMv8 architecture. This is enabled using the command line option of +ssbs for older versions. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SSBS): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (operand_general_constraint_met_p): Add SSBS in the check for one-bit immediate. (aarch64_sys_regs): New entry for SSBS. (aarch64_sys_reg_supported_p): New check for above. (aarch64_pstatefields): New entry for SSBS. (aarch64_pstatefield_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): Add new "ssbs". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/ssbs-illegal1.d: New test. * testsuite/gas/aarch64/ssbs-illegal1.l: New test. * testsuite/gas/aarch64/ssbs-illegal2.d: New test. * testsuite/gas/aarch64/ssbs-illegal2.l: New test. * testsuite/gas/aarch64/ssbs.s: New test. * testsuite/gas/aarch64/ssbs1.d: Test with +ssbs * testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
This commit is contained in:
Sudakshina Das
Richard Earnshaw
parent
a97330e723
commit
104fefeebb
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@ -1,3 +1,15 @@
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (aarch64_features): Add new "ssbs".
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* doc/c-aarch64.texi: Document the same.
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* testsuite/gas/aarch64/ssbs-illegal1.d: New test.
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* testsuite/gas/aarch64/ssbs-illegal1.l: New test.
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* testsuite/gas/aarch64/ssbs-illegal2.d: New test.
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* testsuite/gas/aarch64/ssbs-illegal2.l: New test.
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* testsuite/gas/aarch64/ssbs.s: New test.
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* testsuite/gas/aarch64/ssbs1.d: Test with +ssbs
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* testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* testsuite/gas/aarch64/sysreg-4.s: Test registers
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@ -8827,6 +8827,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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AARCH64_ARCH_NONE},
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{"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG, 0),
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AARCH64_ARCH_NONE},
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{"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS, 0),
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AARCH64_ARCH_NONE},
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{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
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};
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@ -187,6 +187,8 @@ automatically cause those extensions to be disabled.
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@tab Enable the Execution and Data and Prediction instructions.
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@item @code{rng} @tab ARMv8.5-A @tab No
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@tab Enable ARMv8.5-A random number instructions.
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@item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
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@tab Enable Speculative Store Bypassing Safe state read and write.
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@end multitable
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@node AArch64 Syntax
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@ -0,0 +1,3 @@
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#as: -march=armv8-a+ssbs --defsym ERROR1=1
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#source: ssbs.s
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#error_output: ssbs-illegal1.l
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@ -0,0 +1,15 @@
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[^:]*: Assembler messages:
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#2'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#3'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#4'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#5'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#6'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#7'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#8'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#9'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#10'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#11'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#12'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#13'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#14'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#15'
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@ -0,0 +1,3 @@
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#as: -march=armv8-a --defsym ERROR2=1
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#source: ssbs.s
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#error_output: ssbs-illegal2.l
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@ -0,0 +1,6 @@
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[^:]*: Assembler messages:
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[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'ssbs'
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[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'ssbs'
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[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'ssbs'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'ssbs'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'ssbs'
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@ -0,0 +1,31 @@
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/* Test SSBS. */
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func:
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.ifdef SUCCESS
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msr ssbs, #1
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msr ssbs, #0
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.irp N,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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msr ssbs, x\N
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mrs x\N, ssbs
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.endr
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.irp N,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
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msr ssbs, x\N
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mrs x\N, ssbs
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.endr
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.endif
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/* Constant >1 Failure. */
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.ifdef ERROR1
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.irp N,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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msr ssbs, #\N
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.endr
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.endif
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/* No +ssbs Failure. */
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.ifdef ERROR2
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msr ssbs, #0
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msr ssbs, #1
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msr ssbs, x6
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mrs x25, ssbs
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.endif
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@ -0,0 +1,73 @@
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#source: ssbs.s
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#objdump: -dr
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#as: -march=armv8-a+ssbs --defsym SUCCESS=1
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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.*: d503413f msr ssbs, #0x1
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.*: d503403f msr ssbs, #0x0
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.*: d51b42c0 msr ssbs, x0
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.*: d53b42c0 mrs x0, ssbs
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.*: d51b42c1 msr ssbs, x1
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.*: d53b42c1 mrs x1, ssbs
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.*: d51b42c2 msr ssbs, x2
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.*: d53b42c2 mrs x2, ssbs
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.*: d51b42c3 msr ssbs, x3
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.*: d53b42c3 mrs x3, ssbs
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.*: d51b42c4 msr ssbs, x4
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.*: d53b42c4 mrs x4, ssbs
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.*: d51b42c5 msr ssbs, x5
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.*: d53b42c5 mrs x5, ssbs
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.*: d51b42c6 msr ssbs, x6
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.*: d53b42c6 mrs x6, ssbs
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.*: d51b42c7 msr ssbs, x7
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.*: d53b42c7 mrs x7, ssbs
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.*: d51b42c8 msr ssbs, x8
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.*: d53b42c8 mrs x8, ssbs
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.*: d51b42c9 msr ssbs, x9
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.*: d53b42c9 mrs x9, ssbs
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.*: d51b42ca msr ssbs, x10
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.*: d53b42ca mrs x10, ssbs
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.*: d51b42cb msr ssbs, x11
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.*: d53b42cb mrs x11, ssbs
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.*: d51b42cc msr ssbs, x12
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.*: d53b42cc mrs x12, ssbs
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.*: d51b42cd msr ssbs, x13
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.*: d53b42cd mrs x13, ssbs
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.*: d51b42ce msr ssbs, x14
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.*: d53b42ce mrs x14, ssbs
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.*: d51b42cf msr ssbs, x15
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.*: d53b42cf mrs x15, ssbs
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.*: d51b42d0 msr ssbs, x16
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.*: d53b42d0 mrs x16, ssbs
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.*: d51b42d1 msr ssbs, x17
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.*: d53b42d1 mrs x17, ssbs
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.*: d51b42d2 msr ssbs, x18
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.*: d53b42d2 mrs x18, ssbs
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.*: d51b42d3 msr ssbs, x19
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.*: d53b42d3 mrs x19, ssbs
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.*: d51b42d4 msr ssbs, x20
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.*: d53b42d4 mrs x20, ssbs
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.*: d51b42d5 msr ssbs, x21
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.*: d53b42d5 mrs x21, ssbs
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.*: d51b42d6 msr ssbs, x22
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.*: d53b42d6 mrs x22, ssbs
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.*: d51b42d7 msr ssbs, x23
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.*: d53b42d7 mrs x23, ssbs
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.*: d51b42d8 msr ssbs, x24
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.*: d53b42d8 mrs x24, ssbs
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.*: d51b42d9 msr ssbs, x25
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.*: d53b42d9 mrs x25, ssbs
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.*: d51b42da msr ssbs, x26
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.*: d53b42da mrs x26, ssbs
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.*: d51b42db msr ssbs, x27
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.*: d53b42db mrs x27, ssbs
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.*: d51b42dc msr ssbs, x28
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.*: d53b42dc mrs x28, ssbs
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.*: d51b42dd msr ssbs, x29
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.*: d53b42dd mrs x29, ssbs
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.*: d51b42de msr ssbs, x30
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.*: d53b42de mrs x30, ssbs
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@ -0,0 +1,73 @@
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#source: ssbs.s
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#objdump: -dr
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#as: -march=armv8.5-a --defsym SUCCESS=1
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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.*: d503413f msr ssbs, #0x1
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.*: d503403f msr ssbs, #0x0
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.*: d51b42c0 msr ssbs, x0
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.*: d53b42c0 mrs x0, ssbs
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.*: d51b42c1 msr ssbs, x1
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.*: d53b42c1 mrs x1, ssbs
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.*: d51b42c2 msr ssbs, x2
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.*: d53b42c2 mrs x2, ssbs
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.*: d51b42c3 msr ssbs, x3
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.*: d53b42c3 mrs x3, ssbs
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.*: d51b42c4 msr ssbs, x4
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.*: d53b42c4 mrs x4, ssbs
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.*: d51b42c5 msr ssbs, x5
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.*: d53b42c5 mrs x5, ssbs
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.*: d51b42c6 msr ssbs, x6
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.*: d53b42c6 mrs x6, ssbs
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.*: d51b42c7 msr ssbs, x7
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.*: d53b42c7 mrs x7, ssbs
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.*: d51b42c8 msr ssbs, x8
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.*: d53b42c8 mrs x8, ssbs
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.*: d51b42c9 msr ssbs, x9
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.*: d53b42c9 mrs x9, ssbs
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.*: d51b42ca msr ssbs, x10
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.*: d53b42ca mrs x10, ssbs
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.*: d51b42cb msr ssbs, x11
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.*: d53b42cb mrs x11, ssbs
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.*: d51b42cc msr ssbs, x12
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.*: d53b42cc mrs x12, ssbs
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.*: d51b42cd msr ssbs, x13
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.*: d53b42cd mrs x13, ssbs
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.*: d51b42ce msr ssbs, x14
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.*: d53b42ce mrs x14, ssbs
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.*: d51b42cf msr ssbs, x15
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.*: d53b42cf mrs x15, ssbs
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.*: d51b42d0 msr ssbs, x16
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.*: d53b42d0 mrs x16, ssbs
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.*: d51b42d1 msr ssbs, x17
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.*: d53b42d1 mrs x17, ssbs
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.*: d51b42d2 msr ssbs, x18
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.*: d53b42d2 mrs x18, ssbs
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.*: d51b42d3 msr ssbs, x19
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.*: d53b42d3 mrs x19, ssbs
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.*: d51b42d4 msr ssbs, x20
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.*: d53b42d4 mrs x20, ssbs
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.*: d51b42d5 msr ssbs, x21
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.*: d53b42d5 mrs x21, ssbs
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.*: d51b42d6 msr ssbs, x22
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.*: d53b42d6 mrs x22, ssbs
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.*: d51b42d7 msr ssbs, x23
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.*: d53b42d7 mrs x23, ssbs
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.*: d51b42d8 msr ssbs, x24
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.*: d53b42d8 mrs x24, ssbs
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.*: d51b42d9 msr ssbs, x25
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.*: d53b42d9 mrs x25, ssbs
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.*: d51b42da msr ssbs, x26
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.*: d53b42da mrs x26, ssbs
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.*: d51b42db msr ssbs, x27
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.*: d53b42db mrs x27, ssbs
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.*: d51b42dc msr ssbs, x28
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.*: d53b42dc mrs x28, ssbs
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.*: d51b42dd msr ssbs, x29
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.*: d53b42dd mrs x29, ssbs
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.*: d51b42de msr ssbs, x30
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.*: d53b42de mrs x30, ssbs
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@ -1,3 +1,8 @@
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
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(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
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@ -82,6 +82,8 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
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/* ID_PFR2 instructions. */
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#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
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/* SSBS mechanism enabled. */
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#define AARCH64_FEATURE_SSBS 0x800000000000ULL
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/* Architectures are the sum of the base and extensions. */
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@ -115,7 +117,8 @@ typedef uint32_t aarch64_insn;
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| AARCH64_FEATURE_CVADP \
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| AARCH64_FEATURE_BTI \
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| AARCH64_FEATURE_SCXTNUM \
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| AARCH64_FEATURE_ID_PFR2)
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| AARCH64_FEATURE_ID_PFR2 \
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| AARCH64_FEATURE_SSBS)
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#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
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@ -1,3 +1,12 @@
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (operand_general_constraint_met_p): Add
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SSBS in the check for one-bit immediate.
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(aarch64_sys_regs): New entry for SSBS.
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(aarch64_sys_reg_supported_p): New check for above.
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(aarch64_pstatefields): New entry for SSBS.
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(aarch64_pstatefield_supported_p): New check for above.
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_sys_regs): New entries for
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@ -2490,9 +2490,11 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
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assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
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/* MSR UAO, #uimm4
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MSR PAN, #uimm4
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MSR SSBS,#uimm4
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The immediate must be #0 or #1. */
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if ((opnd->pstatefield == 0x03 /* UAO. */
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|| opnd->pstatefield == 0x04 /* PAN. */
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|| opnd->pstatefield == 0x19 /* SSBS. */
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|| opnd->pstatefield == 0x1a) /* DIT. */
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&& opnds[1].imm.value > 1)
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{
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@ -3708,6 +3710,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
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{ "pan", CPEN_(0,C2,3), F_ARCHEXT },
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{ "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
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{ "nzcv", CPEN_(3,C2,0), 0 },
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{ "ssbs", CPEN_(3,C2,6), F_ARCHEXT },
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{ "fpcr", CPEN_(3,C4,0), 0 },
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{ "fpsr", CPEN_(3,C4,1), 0 },
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{ "dspsr_el0", CPEN_(3,C5,0), 0 },
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@ -4128,6 +4131,11 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
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&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
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return FALSE;
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/* SSBS. Values are from aarch64_sys_regs. */
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if (reg->value == CPEN_(3,C2,6)
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&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
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return FALSE;
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/* Virtualization host extensions: system registers. */
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if ((reg->value == CPENC (3, 4, C2, C0, 1)
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|| reg->value == CPENC (3, 4, C13, C0, 1)
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@ -4340,6 +4348,7 @@ const aarch64_sys_reg aarch64_pstatefields [] =
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{ "daifclr", 0x1f, 0 },
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{ "pan", 0x04, F_ARCHEXT },
|
||||
{ "uao", 0x03, F_ARCHEXT },
|
||||
{ "ssbs", 0x19, F_ARCHEXT },
|
||||
{ "dit", 0x1a, F_ARCHEXT },
|
||||
{ 0, CPENC(0,0,0,0,0), 0 },
|
||||
};
|
||||
|
|
@ -4361,6 +4370,11 @@ aarch64_pstatefield_supported_p (const aarch64_feature_set features,
|
|||
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
|
||||
return FALSE;
|
||||
|
||||
/* SSBS. Values are from aarch64_pstatefields. */
|
||||
if (reg->value == 0x19
|
||||
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
|
||||
return FALSE;
|
||||
|
||||
/* DIT. Values are from aarch64_pstatefields. */
|
||||
if (reg->value == 0x1a
|
||||
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
|
||||
|
|
|
|||
Loading…
Reference in New Issue