[ARM] Support ARMv8.2 RAS extension.
The ARMv8.2 architecture includes the RAS extension which adds an instruction, ESB, and a number of coprocessor registers. This patch adds the instruction to binutils, making it available when -march=armv8.2-a is selected. It also adds tests for the instruction and for the coprocessor registers. gas/ 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (arm_ext_v8_2): New. (insns): Add "esb". * testsuite/gas/arm/armv8_2-a.d: New. * testsuite/gas/arm/armv8_2-a.s: New. opcodes/ 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> * arm-dis.c (arm_opcodes): Add "esb". (thumb_opcodes): Likewise. Change-Id: I67f3d70789db78d1c66a56c4994675f99ac15e34
This commit is contained in:
Matthew Wahab
parent
ac06903dcf
commit
105bde5771
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@ -1,3 +1,10 @@
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2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
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* config/tc-arm.c (arm_ext_v8_2): New.
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(insns): Add "esb".
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* testsuite/gas/arm/armv8_2-a.d: New.
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* testsuite/gas/arm/armv8_2-a.s: New.
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2016-01-12 Alan Modra <amodra@gmail.com>
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* testsuite/gas/ppc/vsx3.d: Accept nop padding.
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@ -214,6 +214,8 @@ static const arm_feature_set arm_ext_v6t2_v8m =
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/* Instructions shared between ARMv8-A and ARMv8-M. */
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static const arm_feature_set arm_ext_atomics =
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ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
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static const arm_feature_set arm_ext_v8_2 =
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ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
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static const arm_feature_set arm_arch_any = ARM_ANY;
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static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1, -1);
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@ -19340,6 +19342,13 @@ static const struct asm_opcode insns[] =
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TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
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TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
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/* ARMv8.2 RAS extension. */
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#undef ARM_VARIANT
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#define ARM_VARIANT & arm_ext_v8_2
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v8_2
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TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
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#undef THUMB_VARIANT
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@ -0,0 +1,51 @@
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#name: ARMv8.2-A
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#objdump: -dr
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.*: +file format .*arm.*
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Disassembly of section .text:
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[0-9a-f]+ <.*>:
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[0-9a-f]+: e320f010 esb
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[0-9a-f]+ <.*>:
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[0-9a-f]+: f3af 8010 esb
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[0-9a-f]+ <.*>:
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[0-9a-f]+: ee100f11 mrc 15, 0, r0, cr0, cr1, \{0\}
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[0-9a-f]+: ee100fd2 mrc 15, 0, r0, cr0, cr2, \{6\}
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[0-9a-f]+: ee150f13 mrc 15, 0, r0, cr5, cr3, \{0\}
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[0-9a-f]+: ee150f33 mrc 15, 0, r0, cr5, cr3, \{1\}
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[0-9a-f]+: ee051f33 mcr 15, 0, r1, cr5, cr3, \{1\}
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[0-9a-f]+: ee150f14 mrc 15, 0, r0, cr5, cr4, \{0\}
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[0-9a-f]+: ee150f34 mrc 15, 0, r0, cr5, cr4, \{1\}
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[0-9a-f]+: ee051f34 mcr 15, 0, r1, cr5, cr4, \{1\}
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[0-9a-f]+: ee150f54 mrc 15, 0, r0, cr5, cr4, \{2\}
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[0-9a-f]+: ee051f54 mcr 15, 0, r1, cr5, cr4, \{2\}
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[0-9a-f]+: ee150f74 mrc 15, 0, r0, cr5, cr4, \{3\}
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[0-9a-f]+: ee051f74 mcr 15, 0, r1, cr5, cr4, \{3\}
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[0-9a-f]+: ee150f94 mrc 15, 0, r0, cr5, cr4, \{4\}
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[0-9a-f]+: ee150fb4 mrc 15, 0, r0, cr5, cr4, \{5\}
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[0-9a-f]+: ee051fb4 mcr 15, 0, r1, cr5, cr4, \{5\}
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[0-9a-f]+: ee150ff4 mrc 15, 0, r0, cr5, cr4, \{7\}
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[0-9a-f]+: ee051ff4 mcr 15, 0, r1, cr5, cr4, \{7\}
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[0-9a-f]+: ee150f15 mrc 15, 0, r0, cr5, cr5, \{0\}
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[0-9a-f]+: ee051f15 mcr 15, 0, r1, cr5, cr5, \{0\}
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[0-9a-f]+: ee150f35 mrc 15, 0, r0, cr5, cr5, \{1\}
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[0-9a-f]+: ee051f35 mcr 15, 0, r1, cr5, cr5, \{1\}
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[0-9a-f]+: ee150f95 mrc 15, 0, r0, cr5, cr5, \{4\}
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[0-9a-f]+: ee051f95 mcr 15, 0, r1, cr5, cr5, \{4\}
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[0-9a-f]+: ee150fb5 mrc 15, 0, r0, cr5, cr5, \{5\}
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[0-9a-f]+: ee051fb5 mcr 15, 0, r1, cr5, cr5, \{5\}
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[0-9a-f]+: ee1c0f31 mrc 15, 0, r0, cr12, cr1, \{1\}
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[0-9a-f]+: ee0c1f31 mcr 15, 0, r1, cr12, cr1, \{1\}
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[0-9a-f]+: ee910f91 mrc 15, 4, r0, cr1, cr1, \{4\}
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[0-9a-f]+: ee811f91 mcr 15, 4, r1, cr1, cr1, \{4\}
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[0-9a-f]+: ee950f72 mrc 15, 4, r0, cr5, cr2, \{3\}
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[0-9a-f]+: ee851f72 mcr 15, 4, r1, cr5, cr2, \{3\}
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[0-9a-f]+: ee910f31 mrc 15, 4, r0, cr1, cr1, \{1\}
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[0-9a-f]+: ee811f31 mcr 15, 4, r1, cr1, cr1, \{1\}
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[0-9a-f]+: ee9c0f31 mrc 15, 4, r0, cr12, cr1, \{1\}
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[0-9a-f]+: ee8c1f31 mcr 15, 4, r1, cr12, cr1, \{1\}
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[0-9a-f]+: eed10f11 mrc 15, 6, r0, cr1, cr1, \{0\}
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[0-9a-f]+: eec11f11 mcr 15, 6, r1, cr1, cr1, \{0\}
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@ -0,0 +1,44 @@
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/* ARMv8.2 features. */
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/* RAS instructions. */
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A1:
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.arm
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esb
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T1: .thumb
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esb
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/* RAS system registers. */
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.macro test_sysreg Opc1 CRn CRm Opc2 rw
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mrc p15, \Opc1,\() r0, \CRn\(), \CRm\(), \Opc2\()
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.if \rw
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mcr p15, \Opc1\(), r1, \CRn\(), \CRm\(), \Opc2\()
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.endif
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.endm
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A2:
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.arm
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test_sysreg 0 c0 c1 0 0
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test_sysreg 0 c0 c2 6 0
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test_sysreg 0 c5 c3 0 0
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test_sysreg 0 c5 c3 1 1
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test_sysreg 0 c5 c4 0 0
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test_sysreg 0 c5 c4 1 1
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test_sysreg 0 c5 c4 2 1
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test_sysreg 0 c5 c4 3 1
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test_sysreg 0 c5 c4 4 0
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test_sysreg 0 c5 c4 5 1
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test_sysreg 0 c5 c4 7 1
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test_sysreg 0 c5 c5 0 1
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test_sysreg 0 c5 c5 1 1
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test_sysreg 0 c5 c5 4 1
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test_sysreg 0 c5 c5 5 1
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test_sysreg 0 c12 c1 1 1
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test_sysreg 4 c1 c1 4 1
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test_sysreg 4 c5 c2 3 1
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test_sysreg 4 c1 c1 1 1
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test_sysreg 4 c12 c1 1 1
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test_sysreg 6 c1 c1 0 1
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@ -1,3 +1,8 @@
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2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
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* arm-dis.c (arm_opcodes): Add "esb".
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(thumb_opcodes): Likewise.
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2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c <xscmpnedp>: Delete.
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@ -1576,6 +1576,10 @@ static const struct opcode32 arm_opcodes[] =
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0x00a00090, 0x0fa000f0,
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"%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
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/* V8.2 RAS extension instructions. */
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
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0xe320f010, 0xffffffff, "esb"},
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/* V8 instructions. */
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
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0x0320f005, 0x0fffffff, "sevl"},
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@ -2532,6 +2536,10 @@ static const struct opcode32 thumb32_opcodes[] =
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
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0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
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/* ARM V8.2 RAS extension instructions. */
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
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0xf3af8010, 0xffffffff, "esb"},
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/* V8 instructions. */
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
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0xf3af8005, 0xffffffff, "sevl%c.w"},
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