* mips-opc.c (mula.s): Renamed from multa.s.
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@ -1,3 +1,9 @@
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start-sanitize-r5900
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Fri Feb 20 01:23:16 1998 Jeffrey A Law (law@cygnus.com)
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* mips-opc.c (mula.s): Renamed from multa.s.
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end-sanitize-r5900
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Thu Feb 19 16:51:13 1998 Doug Evans <devans@canuck.cygnus.com>
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* m32r-opc.[ch]: Regenerate.
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@ -528,7 +528,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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/* end-sanitize-vr5400 */
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{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
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{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
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{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s,L1 },
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{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
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{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
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/* start-sanitize-r5900 */
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@ -552,7 +551,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"max.s", "D,S,T", 0x46000028, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, T5 },
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{"min.s", "D,S,T", 0x46000030, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, T5 },
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{"msuba.s", "S,T", 0x4600001f, 0xffe007ff, RD_S|RD_T|FP_S, T5 },
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{"multa.s", "S,T", 0x4600001a, 0xffe007ff, RD_S|RD_T|FP_S, T5 },
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{"mult.s", "S,T", 0x4600001a, 0xffe007ff, RD_S|RD_T|FP_S, T5 },
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{"suba.s", "S,T", 0x46000019, 0xffe007ff, RD_S|RD_T|FP_S, T5 },
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{"di", "", 0x42000039, 0xffffffff, WR_C0, T5 },
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{"ei", "", 0x42000038, 0xffffffff, WR_C0, T5 },
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@ -676,7 +675,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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/* end-sanitize-vr5400 */
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{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, P3 },
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{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3},
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{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
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{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
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{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
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@ -1114,6 +1113,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 },
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{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 },
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{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 },
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/* Conflicts with the 4650's "mul" instruction. Nobody's using the
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4010 any more, so move this insn out of the way. If the object
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format gave us more info, we could do this right. */
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{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s,L1 },
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};
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#define MIPS_NUM_OPCODES \
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